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Merge tag 'tegra-for-7.1-dt-bindings' of https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/drivers

Browse Source 
dt-bindings: Changes for v7.1-rc1

This contains a few conversions to DT schema along with various
additions and fixes to reduce the amount of validation warnings.

Included are also a new binding for the PCIe controller found on
Tegra264 as well as compatible strings for the Jetson AGX Thor
Developer Kit.

* tag 'tegra-for-7.1-dt-bindings' of https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  dt-bindings: arm: tegra: Document Jetson AGX Thor DevKit
  dt-bindings: display: tegra: Document Tegra20 HDMI port
  dt-bindings: arm: tegra: Add Tegra238 CBB compatible strings
  dt-bindings: memory: tegra210: Mark EMC as cooling device
  dt-bindings: memory: Add Tegra210 memory controller bindings
  dt-bindings: phy: tegra: Document Tegra210 USB PHY
  dt-bindings: arm: tegra: Add missing compatible strings
  dt-bindings: interrupt-controller: tegra: Fix reg entries
  dt-bindings: clock: tegra124-dfll: Convert to json-schema
  dt-bindings: phy: tegra-xusb: Document Type C support
  dt-bindings: pci: Document the NVIDIA Tegra264 PCIe controller

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
This commit is contained in:
Krzysztof Kozlowski
2026-04-04 16:09:43 +02:00
parent a66cc657ef bed2f5b4de
commit d7dbdadad2
11 changed files with 649 additions and 164 deletions
Download Patch File Download Diff File Expand all files Collapse all files

56
Documentation/devicetree/bindings/arm/tegra.yaml
View File

@@ -131,6 +131,33 @@ properties:
- const: toradex,apalis-tk1-v1.2
- const: toradex,apalis-tk1
- const: nvidia,tegra124
- items:
- const: google,nyan-big-rev7
- const: google,nyan-big-rev6
- const: google,nyan-big-rev5
- const: google,nyan-big-rev4
- const: google,nyan-big-rev3
- const: google,nyan-big-rev2
- const: google,nyan-big-rev1
- const: google,nyan-big-rev0
- const: google,nyan-big
- const: google,nyan
- const: nvidia,tegra124
- items:
- const: google,nyan-blaze-rev10
- const: google,nyan-blaze-rev9
- const: google,nyan-blaze-rev8
- const: google,nyan-blaze-rev7
- const: google,nyan-blaze-rev6
- const: google,nyan-blaze-rev5
- const: google,nyan-blaze-rev4
- const: google,nyan-blaze-rev3
- const: google,nyan-blaze-rev2
- const: google,nyan-blaze-rev1
- const: google,nyan-blaze-rev0
- const: google,nyan-blaze
- const: google,nyan
- const: nvidia,tegra124
- items:
- enum:
- nvidia,norrin
@@ -184,17 +211,35 @@ properties:
- const: nvidia,tegra124
- items:
- enum:
- nvidia,darcy
- nvidia,p2371-0000
- nvidia,p2371-2180
- nvidia,p2571
- nvidia,p2894-0050-a08
- nvidia,p3450-0000
- const: nvidia,tegra210
- items:
- const: nvidia,p3541-0000
- const: nvidia,p3450-0000
- const: nvidia,tegra210
- description: NVIDIA Jetson Nano
items:
- const: nvidia,p3450-0000
- const: nvidia,tegra210
- description: NVIDIA Shield TV
items:
- const: nvidia,p2894-0050-a08
- const: nvidia,darcy
- const: nvidia,tegra210
- description: Google Pixel C
items:
- const: google,smaug-rev8
- const: google,smaug-rev7
- const: google,smaug-rev6
- const: google,smaug-rev5
- const: google,smaug-rev4
- const: google,smaug-rev3
- const: google,smaug-rev2
- const: google,smaug-rev1
- const: google,smaug
- const: nvidia,tegra210
- description: Jetson TX2 Developer Kit
items:
- const: nvidia,p2771-0000
@@ -268,5 +313,10 @@ properties:
- const: nvidia,p3971-0089+p3834-0008
- const: nvidia,p3834-0008
- const: nvidia,tegra264
- description: Jetson AGX Thor Developer Kit
items:
- const: nvidia,p4071-0000+p3834-0008
- const: nvidia,p3834-0008
- const: nvidia,tegra264
additionalProperties: true

4
Documentation/devicetree/bindings/arm/tegra/nvidia,tegra234-cbb.yaml
View File

@@ -48,6 +48,10 @@ properties:
- nvidia,tegra234-dce-fabric
- nvidia,tegra234-rce-fabric
- nvidia,tegra234-sce-fabric
- nvidia,tegra238-ape-fabric
- nvidia,tegra238-aon-fabric
- nvidia,tegra238-bpmp-fabric
- nvidia,tegra238-cbb-fabric
reg:
maxItems: 1

155
Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt
View File

@@ -1,155 +0,0 @@
NVIDIA Tegra124 DFLL FCPU clocksource
This binding uses the common clock binding:
Documentation/devicetree/bindings/clock/clock-bindings.txt
The DFLL IP block on Tegra is a root clocksource designed for clocking
the fast CPU cluster. It consists of a free-running voltage controlled
oscillator connected to the CPU voltage rail (VDD_CPU), and a closed loop
control module that will automatically adjust the VDD_CPU voltage by
communicating with an off-chip PMIC either via an I2C bus or via PWM signals.
Required properties:
- compatible : should be one of:
- "nvidia,tegra124-dfll": for Tegra124
- "nvidia,tegra210-dfll": for Tegra210
- reg : Defines the following set of registers, in the order listed:
- registers for the DFLL control logic.
- registers for the I2C output logic.
- registers for the integrated I2C master controller.
- look-up table RAM for voltage register values.
- interrupts: Should contain the DFLL block interrupt.
- clocks: Must contain an entry for each entry in clock-names.
See clock-bindings.txt for details.
- clock-names: Must include the following entries:
- soc: Clock source for the DFLL control logic.
- ref: The closed loop reference clock
- i2c: Clock source for the integrated I2C master.
- resets: Must contain an entry for each entry in reset-names.
See ../reset/reset.txt for details.
- reset-names: Must include the following entries:
- dvco: Reset control for the DFLL DVCO.
- #clock-cells: Must be 0.
- clock-output-names: Name of the clock output.
- vdd-cpu-supply: Regulator for the CPU voltage rail that the DFLL
hardware will start controlling. The regulator will be queried for
the I2C register, control values and supported voltages.
Required properties for the control loop parameters:
- nvidia,sample-rate: Sample rate of the DFLL control loop.
- nvidia,droop-ctrl: See the register CL_DVFS_DROOP_CTRL in the TRM.
- nvidia,force-mode: See the field DFLL_PARAMS_FORCE_MODE in the TRM.
- nvidia,cf: Numeric value, see the field DFLL_PARAMS_CF_PARAM in the TRM.
- nvidia,ci: Numeric value, see the field DFLL_PARAMS_CI_PARAM in the TRM.
- nvidia,cg: Numeric value, see the field DFLL_PARAMS_CG_PARAM in the TRM.
Optional properties for the control loop parameters:
- nvidia,cg-scale: Boolean value, see the field DFLL_PARAMS_CG_SCALE in the TRM.
Optional properties for mode selection:
- nvidia,pwm-to-pmic: Use PWM to control regulator rather then I2C.
Required properties for I2C mode:
- nvidia,i2c-fs-rate: I2C transfer rate, if using full speed mode.
Required properties for PWM mode:
- nvidia,pwm-period-nanoseconds: period of PWM square wave in nanoseconds.
- nvidia,pwm-tristate-microvolts: Regulator voltage in micro volts when PWM
control is disabled and the PWM output is tristated. Note that this voltage is
configured in hardware, typically via a resistor divider.
- nvidia,pwm-min-microvolts: Regulator voltage in micro volts when PWM control
is enabled and PWM output is low. Hence, this is the minimum output voltage
that the regulator supports when PWM control is enabled.
- nvidia,pwm-voltage-step-microvolts: Voltage increase in micro volts
corresponding to a 1/33th increase in duty cycle. Eg the voltage for 2/33th
duty cycle would be: nvidia,pwm-min-microvolts +
nvidia,pwm-voltage-step-microvolts * 2.
- pinctrl-0: I/O pad configuration when PWM control is enabled.
- pinctrl-1: I/O pad configuration when PWM control is disabled.
- pinctrl-names: must include the following entries:
- dvfs_pwm_enable: I/O pad configuration when PWM control is enabled.
- dvfs_pwm_disable: I/O pad configuration when PWM control is disabled.
Example for I2C:
clock@70110000 {
compatible = "nvidia,tegra124-dfll";
reg = <0 0x70110000 0 0x100>, /* DFLL control */
<0 0x70110000 0 0x100>, /* I2C output control */
<0 0x70110100 0 0x100>, /* Integrated I2C controller */
<0 0x70110200 0 0x100>; /* Look-up table RAM */
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA124_CLK_DFLL_SOC>,
<&tegra_car TEGRA124_CLK_DFLL_REF>,
<&tegra_car TEGRA124_CLK_I2C5>;
clock-names = "soc", "ref", "i2c";
resets = <&tegra_car TEGRA124_RST_DFLL_DVCO>;
reset-names = "dvco";
#clock-cells = <0>;
clock-output-names = "dfllCPU_out";
vdd-cpu-supply = <&vdd_cpu>;
nvidia,sample-rate = <12500>;
nvidia,droop-ctrl = <0x00000f00>;
nvidia,force-mode = <1>;
nvidia,cf = <10>;
nvidia,ci = <0>;
nvidia,cg = <2>;
nvidia,i2c-fs-rate = <400000>;
};
Example for PWM:
clock@70110000 {
compatible = "nvidia,tegra124-dfll";
reg = <0 0x70110000 0 0x100>, /* DFLL control */
<0 0x70110000 0 0x100>, /* I2C output control */
<0 0x70110100 0 0x100>, /* Integrated I2C controller */
<0 0x70110200 0 0x100>; /* Look-up table RAM */
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA210_CLK_DFLL_SOC>,
<&tegra_car TEGRA210_CLK_DFLL_REF>,
<&tegra_car TEGRA124_CLK_I2C5>;;
clock-names = "soc", "ref", "i2c";
resets = <&tegra_car TEGRA124_RST_DFLL_DVCO>;
reset-names = "dvco";
#clock-cells = <0>;
clock-output-names = "dfllCPU_out";
nvidia,sample-rate = <25000>;
nvidia,droop-ctrl = <0x00000f00>;
nvidia,force-mode = <1>;
nvidia,cf = <6>;
nvidia,ci = <0>;
nvidia,cg = <2>;
nvidia,pwm-min-microvolts = <708000>; /* 708mV */
nvidia,pwm-period-nanoseconds = <2500>; /* 2.5us */
nvidia,pwm-to-pmic;
nvidia,pwm-tristate-microvolts = <1000000>;
nvidia,pwm-voltage-step-microvolts = <19200>; /* 19.2mV */
pinctrl-names = "dvfs_pwm_enable", "dvfs_pwm_disable";
pinctrl-0 = <&dvfs_pwm_active_state>;
pinctrl-1 = <&dvfs_pwm_inactive_state>;
};
/* pinmux nodes added for completeness. Binding doc can be found in:
* Documentation/devicetree/bindings/pinctrl/nvidia,tegra210-pinmux.yaml
*/
pinmux: pinmux@700008d4 {
dvfs_pwm_active_state: dvfs_pwm_active {
dvfs_pwm_pbb1 {
nvidia,pins = "dvfs_pwm_pbb1";
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
};
dvfs_pwm_inactive_state: dvfs_pwm_inactive {
dvfs_pwm_pbb1 {
nvidia,pins = "dvfs_pwm_pbb1";
nvidia,tristate = <TEGRA_PIN_ENABLE>;
};
};
};

290
Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.yaml Normal file
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@@ -0,0 +1,290 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/nvidia,tegra124-dfll.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra124 (and later) DFLL FCPU clocksource
maintainers:
- Thierry Reding <thierry.reding@gmail.com>
- Jon Hunter <jonathanh@nvidia.com>
description:
The DFLL IP block on Tegra is a root clocksource designed for clocking
the fast CPU cluster. It consists of a free-running voltage controlled
oscillator connected to the CPU voltage rail (VDD_CPU), and a closed
loop control module that will automatically adjust the VDD_CPU voltage
by communicating with an off-chip PMIC either via an I2C bus or via
PWM signals.
properties:
compatible:
enum:
- nvidia,tegra124-dfll
- nvidia,tegra210-dfll
reg:
items:
- description: DFLL control logic
- description: I2C output logic
- description: Integrated I2C controller
- description: Look-up table RAM for voltage register values
interrupts:
maxItems: 1
"#clock-cells":
const: 0
clocks:
items:
- description: Clock source for the DFLL control logic
- description: Closed loop reference clock
- description: Clock source for the integrated I2C controller
clock-names:
items:
- const: soc
- const: ref
- const: i2c
clock-output-names:
description: Name of the clock output
items:
- const: dfllCPU_out
resets:
minItems: 1
maxItems: 2
reset-names:
minItems: 1
items:
- const: dvco
- const: dfll
vdd-cpu-supply:
description: Regulator for the CPU voltage rail that the DFLL
hardware will start controlling. The regulator will be queried for
the I2C register, control values and supported voltages.
nvidia,sample-rate:
description: Sample rate of the DFLL control loop
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 12500
maximum: 25000
nvidia,droop-ctrl:
description: Droop control parameter (CL_DVFS_DROOP_CTRL) in the TRM
$ref: /schemas/types.yaml#/definitions/uint32
nvidia,force-mode:
description: See the field DFLL_PARAMS_FORCE_MODE in the TRM
$ref: /schemas/types.yaml#/definitions/uint32
oneOf:
- description: disabled
const: 0
- description: fixed delay mode
const: 1
- description: auto mode
const: 2
nvidia,cf:
description: Numeric value, see the field DFLL_PARAMS_CF_PARAM in the TRM
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 63
nvidia,ci:
description: Numeric value, see the field DFLL_PARAMS_CI_PARAM in the TRM
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 7
nvidia,cg:
description: Numeric value, see the field DFLL_PARAMS_CG_PARAM in the TRM
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 255
# optional properties
nvidia,cg-scale:
description: Boolean value, see the field DFLL_PARAMS_CG_SCALE in the TRM
$ref: /schemas/types.yaml#/definitions/flag
nvidia,pwm-to-pmic:
description: Use PWM to control regulator rather than I2C
$ref: /schemas/types.yaml#/definitions/flag
nvidia,i2c-fs-rate:
description: I2C transfer rate, if using full speed mode
$ref: /schemas/types.yaml#/definitions/uint32
enum: [100000, 400000]
# required properties for PWM mode
nvidia,pwm-period-nanoseconds:
description: Period of PWM square wave in nanoseconds
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 1000
maximum: 1000000000
nvidia,pwm-tristate-microvolts:
description: Regulator voltage in microvolts when PWM control is disabled
and the PWM output is tristated. Note that this voltage is configured in
hardware, typically via a resistor divider.
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 3300000
nvidia,pwm-min-microvolts:
description: Regulator voltage in microvolts when PWM control is enabled
and PWM output is low. Hence, this is the minimum output voltage that
the regulator supports when PWM control is enabled.
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 3300000
nvidia,pwm-voltage-step-microvolts:
description: |
Voltage increase in micro volts corresponding to a 1/33th increase
in duty cycle. For example, the voltage for 2/33th duty cycle would be:
nvidia,pwm-min-microvolts + nvidia,pwm-voltage-step-microvolts * 2
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 100000
pinctrl-0:
description: I/O pad configuration when PWM control is enabled
pinctrl-1:
description: I/O pad configuration when PWM control is disabled
pinctrl-names:
items:
- const: dvfs_pwm_enable
- const: dvfs_pwm_disable
required:
- compatible
- reg
- interrupts
- "#clock-cells"
- clocks
- clock-names
- clock-output-names
- resets
- reset-names
- nvidia,sample-rate
- nvidia,droop-ctrl
- nvidia,force-mode
- nvidia,cf
- nvidia,ci
- nvidia,cg
additionalProperties: false
allOf:
- if:
properties:
compatible:
contains:
const: nvidia,tegra124-dfll
then:
properties:
resets:
maxItems: 1
reset-names:
maxItems: 1
else:
properties:
resets:
minItems: 2
reset-names:
minItems: 2
- if:
required:
- nvidia,pwm-to-pmic
then:
required:
- nvidia,pwm-min-microvolts
- nvidia,pwm-period-nanoseconds
- nvidia,pwm-tristate-microvolts
- nvidia,pwm-voltage-step-microvolts
else:
required:
- vdd-cpu-supply
examples:
- |
#include <dt-bindings/clock/tegra124-car.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset/tegra124-car.h>
clock@70110000 {
compatible = "nvidia,tegra124-dfll";
reg = <0x70110000 0x100>, /* DFLL control */
<0x70110000 0x100>, /* I2C output control */
<0x70110100 0x100>, /* Integrated I2C controller */
<0x70110200 0x100>; /* Look-up table RAM */
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA124_CLK_DFLL_SOC>,
<&tegra_car TEGRA124_CLK_DFLL_REF>,
<&tegra_car TEGRA124_CLK_I2C5>;
clock-names = "soc", "ref", "i2c";
resets = <&tegra_car TEGRA124_RST_DFLL_DVCO>;
reset-names = "dvco";
#clock-cells = <0>;
clock-output-names = "dfllCPU_out";
vdd-cpu-supply = <&vdd_cpu>;
nvidia,sample-rate = <12500>;
nvidia,droop-ctrl = <0x00000f00>;
nvidia,force-mode = <1>;
nvidia,cf = <10>;
nvidia,ci = <0>;
nvidia,cg = <2>;
nvidia,i2c-fs-rate = <400000>;
};
- |
#include <dt-bindings/clock/tegra210-car.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset/tegra210-car.h>
clock@70110000 {
compatible = "nvidia,tegra210-dfll";
reg = <0x70110000 0x100>, /* DFLL control */
<0x70110000 0x100>, /* I2C output control */
<0x70110100 0x100>, /* Integrated I2C controller */
<0x70110200 0x100>; /* Look-up table RAM */
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA210_CLK_DFLL_SOC>,
<&tegra_car TEGRA210_CLK_DFLL_REF>,
<&tegra_car TEGRA210_CLK_I2C5>;
clock-names = "soc", "ref", "i2c";
resets = <&tegra_car TEGRA210_RST_DFLL_DVCO>,
<&tegra_car 155>;
reset-names = "dvco", "dfll";
#clock-cells = <0>;
clock-output-names = "dfllCPU_out";
vdd-cpu-supply = <&vdd_cpu>;
nvidia,sample-rate = <25000>;
nvidia,droop-ctrl = <0x00000f00>;
nvidia,force-mode = <1>;
nvidia,cf = <6>;
nvidia,ci = <0>;
nvidia,cg = <2>;
nvidia,pwm-min-microvolts = <708000>; /* 708mV */
nvidia,pwm-period-nanoseconds = <2500>; /* 2.5us */
nvidia,pwm-to-pmic;
nvidia,pwm-tristate-microvolts = <1000000>;
nvidia,pwm-voltage-step-microvolts = <19200>; /* 19.2mV */
};

13
Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-hdmi.yaml
View File

@@ -82,6 +82,10 @@ properties:
description: phandle of a display panel
$ref: /schemas/types.yaml#/definitions/phandle
port:
description: HDMI output port for connection to HDMI connector or bridge
$ref: /schemas/graph.yaml#/properties/port
"#sound-dai-cells":
const: 0
@@ -97,8 +101,13 @@ required:
- reset-names
- pll-supply
- vdd-supply
- nvidia,ddc-i2c-bus
- nvidia,hpd-gpio
anyOf:
- required:
- nvidia,ddc-i2c-bus
- nvidia,hpd-gpio
- required:
- port
examples:
- |

23
Documentation/devicetree/bindings/interrupt-controller/nvidia,tegra20-ictlr.yaml
View File

@@ -35,11 +35,12 @@ properties:
- enum:
- nvidia,tegra20-ictlr
- nvidia,tegra30-ictlr
- nvidia,tegra210-ictlr
reg:
description: Each entry is a block of 32 interrupts
minItems: 4
maxItems: 5
maxItems: 6
interrupt-controller: true
@@ -64,10 +65,28 @@ allOf:
properties:
reg:
maxItems: 4
else:
- if:
properties:
compatible:
contains:
const: nvidia,tegra30-ictlr
then:
properties:
reg:
minItems: 5
maxItems: 5
- if:
properties:
compatible:
contains:
const: nvidia,tegra210-ictlr
then:
properties:
reg:
minItems: 6
maxItems: 6
examples:
- |

6
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-emc.yaml
View File

@@ -52,6 +52,9 @@ properties:
Should contain freqs and voltages and opp-supported-hw property, which
is a bitfield indicating SoC speedo ID mask.
allOf:
- $ref: /schemas/thermal/thermal-cooling-devices.yaml
required:
- compatible
- reg
@@ -59,7 +62,7 @@ required:
- clock-names
- nvidia,memory-controller
additionalProperties: false
unevaluatedProperties: false
examples:
- |
@@ -90,4 +93,5 @@ examples:
operating-points-v2 = <&dvfs_opp_table>;
#interconnect-cells = <0>;
#cooling-cells = <2>;
};

77
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-mc.yaml Normal file
View File

@@ -0,0 +1,77 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra210-mc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra210 SoC Memory Controller
maintainers:
- Thierry Reding <thierry.reding@gmail.com>
- Jon Hunter <jonathanh@nvidia.com>
description: |
The NVIDIA Tegra210 SoC features a 64 bit memory controller that is split
into two 32 bit channels to support LPDDR3 and LPDDR4 with x16 subpartitions.
The MC handles memory requests for 34-bit virtual addresses from internal
clients and arbitrates among them to allocate memory bandwidth.
Up to 8 GiB of physical memory can be supported. Security features such as
encryption of traffic to and from DRAM via general security apertures are
available for video and other secure applications.
properties:
$nodename:
pattern: "^memory-controller@[0-9a-f]+$"
compatible:
items:
- enum:
- nvidia,tegra210-mc
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
items:
- description: module clock
clock-names:
items:
- const: mc
"#iommu-cells":
const: 1
"#reset-cells":
const: 1
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
- "#iommu-cells"
- "#reset-cells"
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/tegra210-car.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
memory-controller@70019000 {
compatible = "nvidia,tegra210-mc";
reg = <0x70019000 0x1000>;
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA210_CLK_MC>;
clock-names = "mc";
#iommu-cells = <1>;
#reset-cells = <1>;
};

149
Documentation/devicetree/bindings/pci/nvidia,tegra264-pcie.yaml Normal file
View File

@@ -0,0 +1,149 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/nvidia,tegra264-pcie.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra264 PCIe controller
maintainers:
- Thierry Reding <thierry.reding@gmail.com>
- Jon Hunter <jonathanh@nvidia.com>
properties:
compatible:
const: nvidia,tegra264-pcie
reg:
description: |
Of the six PCIe controllers found on Tegra264, one (C0) is used for the
internal GPU and the other five (C1-C5) are routed to connectors such as
PCI or M.2 slots. Therefore the UPHY registers (XPL) exist only for C1
through C5, but not for C0.
minItems: 4
items:
- description: ECAM-compatible configuration space
- description: application layer registers
- description: transaction layer registers
- description: privileged transaction layer registers
- description: data link/physical layer registers (not available on C0)
reg-names:
minItems: 4
items:
- const: ecam
- const: xal
- const: xtl
- const: xtl-pri
- const: xpl
interrupts:
minItems: 1
maxItems: 4
dma-coherent: true
nvidia,bpmp:
$ref: /schemas/types.yaml#/definitions/phandle-array
description: |
Must contain a pair of phandle (to the BPMP controller node) and
controller ID. The following are the controller IDs for each controller:
0: C0
1: C1
2: C2
3: C3
4: C4
5: C5
items:
- items:
- description: phandle to the BPMP controller node
- description: PCIe controller ID
maximum: 5
required:
- interrupt-map
- interrupt-map-mask
- iommu-map
- msi-map
- nvidia,bpmp
allOf:
- $ref: /schemas/pci/pci-host-bridge.yaml#
unevaluatedProperties: false
examples:
- |
bus {
#address-cells = <2>;
#size-cells = <2>;
pci@c000000 {
compatible = "nvidia,tegra264-pcie";
reg = <0xd0 0xb0000000 0x0 0x10000000>,
<0x00 0x0c000000 0x0 0x00004000>,
<0x00 0x0c004000 0x0 0x00001000>,
<0x00 0x0c005000 0x0 0x00001000>;
reg-names = "ecam", "xal", "xtl", "xtl-pri";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
linux,pci-domain = <0x00>;
#interrupt-cells = <0x1>;
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 155 4>,
<0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 156 4>,
<0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 157 4>,
<0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 158 4>;
iommu-map = <0x0 &smmu2 0x10000 0x10000>;
msi-map = <0x0 &its 0x210000 0x10000>;
dma-coherent;
ranges = <0x81000000 0x00 0x84000000 0xd0 0x84000000 0x00 0x00200000>,
<0x82000000 0x00 0x20000000 0x00 0x20000000 0x00 0x08000000>,
<0xc3000000 0xd0 0xc0000000 0xd0 0xc0000000 0x07 0xc0000000>;
bus-range = <0x0 0xff>;
nvidia,bpmp = <&bpmp 0>;
};
};
- |
bus {
#address-cells = <2>;
#size-cells = <2>;
pci@8400000 {
compatible = "nvidia,tegra264-pcie";
reg = <0xa8 0xb0000000 0x0 0x10000000>,
<0x00 0x08400000 0x0 0x00004000>,
<0x00 0x08404000 0x0 0x00001000>,
<0x00 0x08405000 0x0 0x00001000>,
<0x00 0x08410000 0x0 0x00010000>;
reg-names = "ecam", "xal", "xtl", "xtl-pri", "xpl";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
linux,pci-domain = <0x01>;
#interrupt-cells = <1>;
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 908 4>,
<0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 909 4>,
<0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 910 4>,
<0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 911 4>;
iommu-map = <0x0 &smmu1 0x10000 0x10000>;
msi-map = <0x0 &its 0x110000 0x10000>;
dma-coherent;
ranges = <0x81000000 0x00 0x84000000 0xa8 0x84000000 0x00 0x00200000>,
<0x82000000 0x00 0x28000000 0x00 0x28000000 0x00 0x08000000>,
<0xc3000000 0xa8 0xc0000000 0xa8 0xc0000000 0x07 0xc0000000>;
bus-range = <0x00 0xff>;
nvidia,bpmp = <&bpmp 1>;
};
};

39
Documentation/devicetree/bindings/phy/nvidia,tegra194-xusb-padctl.yaml
View File

@@ -230,6 +230,10 @@ properties:
connector:
type: object
port:
description: connection to a USB Type C controller
$ref: /schemas/graph.yaml#/properties/port
mode:
description: A string that determines the mode in which to
run the port.
@@ -256,7 +260,12 @@ properties:
voltage.
dependencies:
usb-role-switch: [ connector ]
usb-role-switch:
oneOf:
- required:
- connector
- required:
- port
usb2-1:
type: object
@@ -268,6 +277,10 @@ properties:
connector:
type: object
port:
description: connection to a USB Type C controller
$ref: /schemas/graph.yaml#/properties/port
mode:
description: A string that determines the mode in which to
run the port.
@@ -306,6 +319,10 @@ properties:
connector:
type: object
port:
description: connection to a USB Type C controller
$ref: /schemas/graph.yaml#/properties/port
mode:
description: A string that determines the mode in which to
run the port.
@@ -344,6 +361,10 @@ properties:
connector:
type: object
port:
description: connection to a USB Type C controller
$ref: /schemas/graph.yaml#/properties/port
mode:
description: A string that determines the mode in which to
run the port.
@@ -405,6 +426,10 @@ properties:
description: A phandle to the regulator supplying the VBUS
voltage.
port:
description: connection to a USB Type C controller
$ref: /schemas/graph.yaml#/properties/port
usb3-1:
type: object
additionalProperties: false
@@ -438,6 +463,10 @@ properties:
description: A phandle to the regulator supplying the VBUS
voltage.
port:
description: connection to a USB Type C controller
$ref: /schemas/graph.yaml#/properties/port
usb3-2:
type: object
additionalProperties: false
@@ -471,6 +500,10 @@ properties:
description: A phandle to the regulator supplying the VBUS
voltage.
port:
description: connection to a USB Type C controller
$ref: /schemas/graph.yaml#/properties/port
usb3-3:
type: object
additionalProperties: false
@@ -504,6 +537,10 @@ properties:
description: A phandle to the regulator supplying the VBUS
voltage.
port:
description: connection to a USB Type C controller
$ref: /schemas/graph.yaml#/properties/port
additionalProperties: false
required:

1
Documentation/devicetree/bindings/phy/nvidia,tegra20-usb-phy.yaml
View File

@@ -16,6 +16,7 @@ properties:
oneOf:
- items:
- enum:
- nvidia,tegra210-usb-phy
- nvidia,tegra124-usb-phy
- nvidia,tegra114-usb-phy
- enum: