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arm64: dts: amlogic: move CPU OPP table and clock assignment to SoC.dtsi

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Move the assignment of the CPU clocks and the CPU OPP table(s) from
board.dts to SoC.dtsi to reduce the code duplication.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://patch.msgid.link/20260109210217.828961-1-martin.blumenstingl@googlemail.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
This commit is contained in:
Martin Blumenstingl
2026-01-09 22:02:17 +01:00
committed by Neil Armstrong
parent 7bcbedd64e
commit d7b70ebf2b
24 changed files with 71 additions and 186 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
arch/arm64/boot/dts/amlogic/meson-g12a-fbx8am.dts
View File

@@ -265,26 +265,18 @@ &clkc_audio {
&cpu0 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU_CLK>;
};
&cpu1 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU_CLK>;
};
&cpu2 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU_CLK>;
};
&cpu3 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU_CLK>;
};
&ethmac {

8
arch/arm64/boot/dts/amlogic/meson-g12a-radxa-zero.dts
View File

@@ -218,26 +218,18 @@ &clkc_audio {
&cpu0 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU_CLK>;
};
&cpu1 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU_CLK>;
};
&cpu2 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU_CLK>;
};
&cpu3 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU_CLK>;
};
&cvbs_vdac_port {

8
arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts
View File

@@ -312,26 +312,18 @@ &clkc_audio {
&cpu0 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU_CLK>;
};
&cpu1 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU_CLK>;
};
&cpu2 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU_CLK>;
};
&cpu3 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU_CLK>;
};
&cvbs_vdac_port {

8
arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts
View File

@@ -405,26 +405,18 @@ &clkc_audio {
&cpu0 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU_CLK>;
};
&cpu1 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU_CLK>;
};
&cpu2 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU_CLK>;
};
&cpu3 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU_CLK>;
};
&clkc_audio {

8
arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts
View File

@@ -261,26 +261,18 @@ &clkc_audio {
&cpu0 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU_CLK>;
};
&cpu1 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU_CLK>;
};
&cpu2 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU_CLK>;
};
&cpu3 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU_CLK>;
};
&cvbs_vdac_port {

8
arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
View File

@@ -25,6 +25,8 @@ cpu0: cpu@0 {
i-cache-sets = <32>;
next-level-cache = <&l2>;
#cooling-cells = <2>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU_CLK>;
};
cpu1: cpu@1 {
@@ -40,6 +42,8 @@ cpu1: cpu@1 {
i-cache-sets = <32>;
next-level-cache = <&l2>;
#cooling-cells = <2>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU_CLK>;
};
cpu2: cpu@2 {
@@ -55,6 +59,8 @@ cpu2: cpu@2 {
i-cache-sets = <32>;
next-level-cache = <&l2>;
#cooling-cells = <2>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU_CLK>;
};
cpu3: cpu@3 {
@@ -70,6 +76,8 @@ cpu3: cpu@3 {
i-cache-sets = <32>;
next-level-cache = <&l2>;
#cooling-cells = <2>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU_CLK>;
};
l2: l2-cache0 {

13
arch/arm64/boot/dts/amlogic/meson-g12b-a311d-libretech-cc.dts
View File

@@ -6,7 +6,6 @@
/dts-v1/;
#include <dt-bindings/clock/g12a-clkc.h>
#include "meson-g12b-a311d.dtsi"
#include "meson-libretech-cottonwood.dtsi"
@@ -74,38 +73,26 @@ sound {
&cpu0 {
cpu-supply = <&vddcpu_b>;
operating-points-v2 = <&cpu_opp_table_0>;
clocks = <&clkc CLKID_CPU_CLK>;
};
&cpu1 {
cpu-supply = <&vddcpu_b>;
operating-points-v2 = <&cpu_opp_table_0>;
clocks = <&clkc CLKID_CPU_CLK>;
};
&cpu100 {
cpu-supply = <&vddcpu_a>;
operating-points-v2 = <&cpub_opp_table_1>;
clocks = <&clkc CLKID_CPUB_CLK>;
};
&cpu101 {
cpu-supply = <&vddcpu_a>;
operating-points-v2 = <&cpub_opp_table_1>;
clocks = <&clkc CLKID_CPUB_CLK>;
};
&cpu102 {
cpu-supply = <&vddcpu_a>;
operating-points-v2 = <&cpub_opp_table_1>;
clocks = <&clkc CLKID_CPUB_CLK>;
};
&cpu103 {
cpu-supply = <&vddcpu_a>;
operating-points-v2 = <&cpub_opp_table_1>;
clocks = <&clkc CLKID_CPUB_CLK>;
};
&pwm_ab {

24
arch/arm64/boot/dts/amlogic/meson-g12b-a311d.dtsi
View File

@@ -109,3 +109,27 @@ opp-2208000000 {
};
};
};
&cpu0 {
operating-points-v2 = <&cpu_opp_table_0>;
};
&cpu1 {
operating-points-v2 = <&cpu_opp_table_0>;
};
&cpu100 {
operating-points-v2 = <&cpub_opp_table_1>;
};
&cpu101 {
operating-points-v2 = <&cpub_opp_table_1>;
};
&cpu102 {
operating-points-v2 = <&cpub_opp_table_1>;
};
&cpu103 {
operating-points-v2 = <&cpub_opp_table_1>;
};

12
arch/arm64/boot/dts/amlogic/meson-g12b-bananapi-cm4.dtsi
View File

@@ -153,38 +153,26 @@ &cecb_AO {
&cpu0 {
cpu-supply = <&vddcpu_b>;
operating-points-v2 = <&cpu_opp_table_0>;
clocks = <&clkc CLKID_CPU_CLK>;
};
&cpu1 {
cpu-supply = <&vddcpu_b>;
operating-points-v2 = <&cpu_opp_table_0>;
clocks = <&clkc CLKID_CPU_CLK>;
};
&cpu100 {
cpu-supply = <&vddcpu_a>;
operating-points-v2 = <&cpub_opp_table_1>;
clocks = <&clkc CLKID_CPUB_CLK>;
};
&cpu101 {
cpu-supply = <&vddcpu_a>;
operating-points-v2 = <&cpub_opp_table_1>;
clocks = <&clkc CLKID_CPUB_CLK>;
};
&cpu102 {
cpu-supply = <&vddcpu_a>;
operating-points-v2 = <&cpub_opp_table_1>;
clocks = <&clkc CLKID_CPUB_CLK>;
};
&cpu103 {
cpu-supply = <&vddcpu_a>;
operating-points-v2 = <&cpub_opp_table_1>;
clocks = <&clkc CLKID_CPUB_CLK>;
};
&ext_mdio {

12
arch/arm64/boot/dts/amlogic/meson-g12b-bananapi.dtsi
View File

@@ -261,38 +261,26 @@ &cecb_AO {
&cpu0 {
cpu-supply = <&vddcpu_b>;
operating-points-v2 = <&cpu_opp_table_0>;
clocks = <&clkc CLKID_CPU_CLK>;
};
&cpu1 {
cpu-supply = <&vddcpu_b>;
operating-points-v2 = <&cpu_opp_table_0>;
clocks = <&clkc CLKID_CPU_CLK>;
};
&cpu100 {
cpu-supply = <&vddcpu_a>;
operating-points-v2 = <&cpub_opp_table_1>;
clocks = <&clkc CLKID_CPUB_CLK>;
};
&cpu101 {
cpu-supply = <&vddcpu_a>;
operating-points-v2 = <&cpub_opp_table_1>;
clocks = <&clkc CLKID_CPUB_CLK>;
};
&cpu102 {
cpu-supply = <&vddcpu_a>;
operating-points-v2 = <&cpub_opp_table_1>;
clocks = <&clkc CLKID_CPUB_CLK>;
};
&cpu103 {
cpu-supply = <&vddcpu_a>;
operating-points-v2 = <&cpub_opp_table_1>;
clocks = <&clkc CLKID_CPUB_CLK>;
};
&ethmac {

12
arch/arm64/boot/dts/amlogic/meson-g12b-khadas-vim3.dtsi
View File

@@ -49,38 +49,26 @@ vddcpu_b: regulator-vddcpu-b {
&cpu0 {
cpu-supply = <&vddcpu_b>;
operating-points-v2 = <&cpu_opp_table_0>;
clocks = <&clkc CLKID_CPU_CLK>;
};
&cpu1 {
cpu-supply = <&vddcpu_b>;
operating-points-v2 = <&cpu_opp_table_0>;
clocks = <&clkc CLKID_CPU_CLK>;
};
&cpu100 {
cpu-supply = <&vddcpu_a>;
operating-points-v2 = <&cpub_opp_table_1>;
clocks = <&clkc CLKID_CPUB_CLK>;
};
&cpu101 {
cpu-supply = <&vddcpu_a>;
operating-points-v2 = <&cpub_opp_table_1>;
clocks = <&clkc CLKID_CPUB_CLK>;
};
&cpu102 {
cpu-supply = <&vddcpu_a>;
operating-points-v2 = <&cpub_opp_table_1>;
clocks = <&clkc CLKID_CPUB_CLK>;
};
&cpu103 {
cpu-supply = <&vddcpu_a>;
operating-points-v2 = <&cpub_opp_table_1>;
clocks = <&clkc CLKID_CPUB_CLK>;
};
&pwm_ab {

12
arch/arm64/boot/dts/amlogic/meson-g12b-odroid-go-ultra.dts
View File

@@ -279,38 +279,26 @@ &arb {
&cpu0 {
cpu-supply = <&vddcpu_b>;
operating-points-v2 = <&cpu_opp_table_0>;
clocks = <&clkc CLKID_CPU_CLK>;
};
&cpu1 {
cpu-supply = <&vddcpu_b>;
operating-points-v2 = <&cpu_opp_table_0>;
clocks = <&clkc CLKID_CPU_CLK>;
};
&cpu100 {
cpu-supply = <&vddcpu_a>;
operating-points-v2 = <&cpub_opp_table_1>;
clocks = <&clkc CLKID_CPUB_CLK>;
};
&cpu101 {
cpu-supply = <&vddcpu_a>;
operating-points-v2 = <&cpub_opp_table_1>;
clocks = <&clkc CLKID_CPUB_CLK>;
};
&cpu102 {
cpu-supply = <&vddcpu_a>;
operating-points-v2 = <&cpub_opp_table_1>;
clocks = <&clkc CLKID_CPUB_CLK>;
};
&cpu103 {
cpu-supply = <&vddcpu_a>;
operating-points-v2 = <&cpub_opp_table_1>;
clocks = <&clkc CLKID_CPUB_CLK>;
};
/* RK817 only supports 12.5mV steps, round up the values */

12
arch/arm64/boot/dts/amlogic/meson-g12b-odroid.dtsi
View File

@@ -225,38 +225,26 @@ &clkc_audio {
&cpu0 {
cpu-supply = <&vddcpu_b>;
operating-points-v2 = <&cpu_opp_table_0>;
clocks = <&clkc CLKID_CPU_CLK>;
};
&cpu1 {
cpu-supply = <&vddcpu_b>;
operating-points-v2 = <&cpu_opp_table_0>;
clocks = <&clkc CLKID_CPU_CLK>;
};
&cpu100 {
cpu-supply = <&vddcpu_a>;
operating-points-v2 = <&cpub_opp_table_1>;
clocks = <&clkc CLKID_CPUB_CLK>;
};
&cpu101 {
cpu-supply = <&vddcpu_a>;
operating-points-v2 = <&cpub_opp_table_1>;
clocks = <&clkc CLKID_CPUB_CLK>;
};
&cpu102 {
cpu-supply = <&vddcpu_a>;
operating-points-v2 = <&cpub_opp_table_1>;
clocks = <&clkc CLKID_CPUB_CLK>;
};
&cpu103 {
cpu-supply = <&vddcpu_a>;
operating-points-v2 = <&cpub_opp_table_1>;
clocks = <&clkc CLKID_CPUB_CLK>;
};
&cpu_thermal {

12
arch/arm64/boot/dts/amlogic/meson-g12b-radxa-zero2.dts
View File

@@ -257,38 +257,26 @@ &clkc_audio {
&cpu0 {
cpu-supply = <&vddcpu_b>;
operating-points-v2 = <&cpu_opp_table_0>;
clocks = <&clkc CLKID_CPU_CLK>;
};
&cpu1 {
cpu-supply = <&vddcpu_b>;
operating-points-v2 = <&cpu_opp_table_0>;
clocks = <&clkc CLKID_CPU_CLK>;
};
&cpu100 {
cpu-supply = <&vddcpu_a>;
operating-points-v2 = <&cpub_opp_table_1>;
clocks = <&clkc CLKID_CPUB_CLK>;
};
&cpu101 {
cpu-supply = <&vddcpu_a>;
operating-points-v2 = <&cpub_opp_table_1>;
clocks = <&clkc CLKID_CPUB_CLK>;
};
&cpu102 {
cpu-supply = <&vddcpu_a>;
operating-points-v2 = <&cpub_opp_table_1>;
clocks = <&clkc CLKID_CPUB_CLK>;
};
&cpu103 {
cpu-supply = <&vddcpu_a>;
operating-points-v2 = <&cpub_opp_table_1>;
clocks = <&clkc CLKID_CPUB_CLK>;
};
&cpu_thermal {

24
arch/arm64/boot/dts/amlogic/meson-g12b-s922x.dtsi
View File

@@ -99,3 +99,27 @@ opp-1908000000 {
};
};
};
&cpu0 {
operating-points-v2 = <&cpu_opp_table_0>;
};
&cpu1 {
operating-points-v2 = <&cpu_opp_table_0>;
};
&cpu100 {
operating-points-v2 = <&cpub_opp_table_1>;
};
&cpu101 {
operating-points-v2 = <&cpub_opp_table_1>;
};
&cpu102 {
operating-points-v2 = <&cpub_opp_table_1>;
};
&cpu103 {
operating-points-v2 = <&cpub_opp_table_1>;
};

12
arch/arm64/boot/dts/amlogic/meson-g12b-w400.dtsi
View File

@@ -211,38 +211,26 @@ &cecb_AO {
&cpu0 {
cpu-supply = <&vddcpu_b>;
operating-points-v2 = <&cpu_opp_table_0>;
clocks = <&clkc CLKID_CPU_CLK>;
};
&cpu1 {
cpu-supply = <&vddcpu_b>;
operating-points-v2 = <&cpu_opp_table_0>;
clocks = <&clkc CLKID_CPU_CLK>;
};
&cpu100 {
cpu-supply = <&vddcpu_a>;
operating-points-v2 = <&cpub_opp_table_1>;
clocks = <&clkc CLKID_CPUB_CLK>;
};
&cpu101 {
cpu-supply = <&vddcpu_a>;
operating-points-v2 = <&cpub_opp_table_1>;
clocks = <&clkc CLKID_CPUB_CLK>;
};
&cpu102 {
cpu-supply = <&vddcpu_a>;
operating-points-v2 = <&cpub_opp_table_1>;
clocks = <&clkc CLKID_CPUB_CLK>;
};
&cpu103 {
cpu-supply = <&vddcpu_a>;
operating-points-v2 = <&cpub_opp_table_1>;
clocks = <&clkc CLKID_CPUB_CLK>;
};
&cvbs_vdac_port {

7
arch/arm64/boot/dts/amlogic/meson-g12b.dtsi
View File

@@ -57,6 +57,7 @@ cpu0: cpu@0 {
i-cache-sets = <32>;
next-level-cache = <&l2_cache_l>;
#cooling-cells = <2>;
clocks = <&clkc CLKID_CPU_CLK>;
};
cpu1: cpu@1 {
@@ -73,6 +74,7 @@ cpu1: cpu@1 {
i-cache-sets = <32>;
next-level-cache = <&l2_cache_l>;
#cooling-cells = <2>;
clocks = <&clkc CLKID_CPU_CLK>;
};
cpu100: cpu@100 {
@@ -89,6 +91,7 @@ cpu100: cpu@100 {
i-cache-sets = <32>;
next-level-cache = <&l2_cache_b>;
#cooling-cells = <2>;
clocks = <&clkc CLKID_CPUB_CLK>;
};
cpu101: cpu@101 {
@@ -105,6 +108,7 @@ cpu101: cpu@101 {
i-cache-sets = <32>;
next-level-cache = <&l2_cache_b>;
#cooling-cells = <2>;
clocks = <&clkc CLKID_CPUB_CLK>;
};
cpu102: cpu@102 {
@@ -121,6 +125,7 @@ cpu102: cpu@102 {
i-cache-sets = <64>;
next-level-cache = <&l2_cache_b>;
#cooling-cells = <2>;
clocks = <&clkc CLKID_CPUB_CLK>;
};
cpu103: cpu@103 {
@@ -137,6 +142,8 @@ cpu103: cpu@103 {
i-cache-sets = <64>;
next-level-cache = <&l2_cache_b>;
#cooling-cells = <2>;
operating-points-v2 = <&cpub_opp_table_1>;
clocks = <&clkc CLKID_CPUB_CLK>;
};
l2_cache_l: l2-cache-cluster0 {

8
arch/arm64/boot/dts/amlogic/meson-sm1-ac2xx.dtsi
View File

@@ -145,26 +145,18 @@ &cecb_AO {
&cpu0 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU_CLK>;
};
&cpu1 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU1_CLK>;
};
&cpu2 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU2_CLK>;
};
&cpu3 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU3_CLK>;
};
&cvbs_vdac_port {

8
arch/arm64/boot/dts/amlogic/meson-sm1-bananapi.dtsi
View File

@@ -183,26 +183,18 @@ &arb {
&cpu0 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU_CLK>;
};
&cpu1 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU1_CLK>;
};
&cpu2 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU2_CLK>;
};
&cpu3 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU3_CLK>;
};
&ext_mdio {

8
arch/arm64/boot/dts/amlogic/meson-sm1-khadas-vim3l.dts
View File

@@ -49,26 +49,18 @@ sound {
&cpu0 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU_CLK>;
};
&cpu1 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU1_CLK>;
};
&cpu2 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU2_CLK>;
};
&cpu3 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU3_CLK>;
};
&pwm_AO_cd {

8
arch/arm64/boot/dts/amlogic/meson-sm1-odroid.dtsi
View File

@@ -248,26 +248,18 @@ &clkc_audio {
&cpu0 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU_CLK>;
};
&cpu1 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU1_CLK>;
};
&cpu2 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU2_CLK>;
};
&cpu3 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU3_CLK>;
};
&ext_mdio {

9
arch/arm64/boot/dts/amlogic/meson-sm1-s905d3-libretech-cc.dts
View File

@@ -6,7 +6,6 @@
/dts-v1/;
#include <dt-bindings/clock/g12a-clkc.h>
#include "meson-sm1.dtsi"
#include "meson-libretech-cottonwood.dtsi"
@@ -62,24 +61,16 @@ sound {
&cpu0 {
cpu-supply = <&vddcpu_b>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU_CLK>;
};
&cpu1 {
cpu-supply = <&vddcpu_b>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU1_CLK>;
};
&cpu2 {
cpu-supply = <&vddcpu_b>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU2_CLK>;
};
&cpu3 {
cpu-supply = <&vddcpu_b>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU3_CLK>;
};

8
arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts
View File

@@ -357,26 +357,18 @@ &clkc_audio {
&cpu0 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU_CLK>;
};
&cpu1 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU1_CLK>;
};
&cpu2 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU2_CLK>;
};
&cpu3 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU3_CLK>;
};
&ethmac {

8
arch/arm64/boot/dts/amlogic/meson-sm1.dtsi
View File

@@ -63,6 +63,8 @@ cpu0: cpu@0 {
i-cache-sets = <32>;
next-level-cache = <&l2>;
#cooling-cells = <2>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU_CLK>;
};
cpu1: cpu@1 {
@@ -78,6 +80,8 @@ cpu1: cpu@1 {
i-cache-sets = <32>;
next-level-cache = <&l2>;
#cooling-cells = <2>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU1_CLK>;
};
cpu2: cpu@2 {
@@ -93,6 +97,8 @@ cpu2: cpu@2 {
i-cache-sets = <32>;
next-level-cache = <&l2>;
#cooling-cells = <2>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU2_CLK>;
};
cpu3: cpu@3 {
@@ -108,6 +114,8 @@ cpu3: cpu@3 {
i-cache-sets = <32>;
next-level-cache = <&l2>;
#cooling-cells = <2>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU3_CLK>;
};
l2: l2-cache0 {