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arm64: dts: renesas: rcar-gen3: Add reset control properties for display

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Add reset control properties to the device nodes for the Display Units
on all supported R-Car Gen3 SoCs.  Note that on these SoCs, there is
only a single reset for each pair of DU channels.

The display nodes on R-Car V3M and V3H already had "resets" properties,
but lacked the corresponding "reset-names" properties.

Join the clocks lines while at it, to increase uniformity.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Ulrich Hecht <uli+renesas@fpond.eu>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Link: https://lore.kernel.org/r/20200218133019.22299-4-geert+renesas@glider.be
This commit is contained in:
Geert Uytterhoeven
2020-02-18 14:30:18 +01:00
parent 361c5dbb44
commit d745c72da9
7 changed files with 14 additions and 12 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
arch/arm64/boot/dts/renesas/r8a77951.dtsi
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@@ -3177,11 +3177,11 @@ du: display@feb00000 {
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 724>,
<&cpg CPG_MOD 723>,
<&cpg CPG_MOD 722>,
<&cpg CPG_MOD 721>;
clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
<&cpg CPG_MOD 722>, <&cpg CPG_MOD 721>;
clock-names = "du.0", "du.1", "du.2", "du.3";
resets = <&cpg 724>, <&cpg 722>;
reset-names = "du.0", "du.2";
renesas,cmms = <&cmm0>, <&cmm1>, <&cmm2>, <&cmm3>;
renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>,

5
arch/arm64/boot/dts/renesas/r8a77960.dtsi
View File

@@ -2827,10 +2827,11 @@ du: display@feb00000 {
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 724>,
<&cpg CPG_MOD 723>,
clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
<&cpg CPG_MOD 722>;
clock-names = "du.0", "du.1", "du.2";
resets = <&cpg 724>, <&cpg 722>;
reset-names = "du.0", "du.2";
renesas,cmms = <&cmm0>, <&cmm1>, <&cmm2>;
renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>;

5
arch/arm64/boot/dts/renesas/r8a77965.dtsi
View File

@@ -2503,10 +2503,11 @@ du: display@feb00000 {
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 724>,
<&cpg CPG_MOD 723>,
clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
<&cpg CPG_MOD 721>;
clock-names = "du.0", "du.1", "du.3";
resets = <&cpg 724>, <&cpg 722>;
reset-names = "du.0", "du.3";
renesas,cmms = <&cmm0>, <&cmm1>, <&cmm3>;
renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd0 1>;

1
arch/arm64/boot/dts/renesas/r8a77970.dtsi
View File

@@ -1121,6 +1121,7 @@ du: display@feb00000 {
clock-names = "du.0";
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
resets = <&cpg 724>;
reset-names = "du.0";
renesas,vsps = <&vspd0 0>;
status = "disabled";

1
arch/arm64/boot/dts/renesas/r8a77980.dtsi
View File

@@ -1491,6 +1491,7 @@ du: display@feb00000 {
clock-names = "du.0";
power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
resets = <&cpg 724>;
reset-names = "du.0";
renesas,vsps = <&vspd0 0>;
status = "disabled";

3
arch/arm64/boot/dts/renesas/r8a77990.dtsi
View File

@@ -1793,8 +1793,7 @@ du: display@feb00000 {
reg = <0 0xfeb00000 0 0x40000>;
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 724>,
<&cpg CPG_MOD 723>;
clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>;
clock-names = "du.0", "du.1";
resets = <&cpg 724>;
reset-names = "du.0";

3
arch/arm64/boot/dts/renesas/r8a77995.dtsi
View File

@@ -1026,8 +1026,7 @@ du: display@feb00000 {
reg = <0 0xfeb00000 0 0x40000>;
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 724>,
<&cpg CPG_MOD 723>;
clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>;
clock-names = "du.0", "du.1";
resets = <&cpg 724>;
reset-names = "du.0";