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Merge tag 'renesas-dts-for-v6.4-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt

Browse Source 
Renesas DTS updates for v6.4

  - Add USB3 support for the RZ/V2M SoC and the RZ/V2M Evaluation Kit 2.0,
  - Add uSD card and eMMC support for the  RZ/V2M Evaluation Kit 2.0,
  - Add CAN-FD, thermal, GMSL2 video capture, and sound support for the
    R-Car V4H SoC and the White-Hawk development board,
  - Add PMU support for the RZ/G2UL, RZ/G2L{,C}, and RZ/V2L SoCs,
  - Drop support for the obsolete R-Car H3 ES1.* (R8A77950) SoC,
  - Add I2C EEPROM support for the Atmark Techno Armadillo-800-EVA, and
    the Renesas Condor and ULCB development boards,
  - Miscellaneous fixes and improvements.

* tag 'renesas-dts-for-v6.4-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: (30 commits)
  arm64: dts: renesas: r8a779a0: Update CAN-FD to R-Car Gen4 compatible value
  arm64: dts: renesas: ulcb: Add I2C EEPROM for PMIC
  arm64: dts: renesas: condor: Add I2C EEPROM for PMIC
  ARM: dts: armadillo800eva: Add I2C EEPROM for MAC address
  arm64: dts: renesas: Remove R-Car H3 ES1.* devicetrees
  arm64: dts: renesas: white-hawk: Add R-Car Sound support
  arm64: dts: renesas: r8a779g0: R-Car Sound support
  arm64: dts: renesas: r9a07g043: Update IRQ numbers for SSI channels
  arm64: dts: renesas: r9a07g054: Update IRQ numbers for SSI channels
  arm64: dts: renesas: r9a07g044: Update IRQ numbers for SSI channels
  arm64: dts: renesas: r8a774c0: Remove bogus voltages from OPP table
  arm64: dts: renesas: r8a77990: Remove bogus voltages from OPP table
  arm64: dts: renesas: r9a07g054: Add Cortex-A55 PMU node
  arm64: dts: renesas: white-hawk-csi-dsi: Add and connect MAX96712
  arm64: dts: renesas: r8a779g0: Add and connect all CSI-2, ISP and VIN nodes
  arm64: dts: renesas: r8a779f0: Use proper labels for thermal zones
  arm64: dts: renesas: r8a779g0: Add thermal nodes
  arm64: dts: renesas: rzv2mevk2: Add uart0 pins
  arm64: dts: renesas: Drop specifying the GIC_CPU_MASK_SIMPLE() for GICv3 systems
  arm64: dts: renesas: r9a07g044: Add Cortex-A55 PMU node
  ...

Link: https://lore.kernel.org/r/cover.1679907064.git.geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
2023-04-04 16:17:15 +02:00
parent 5b9d72921f 4db0ce4038
commit d707810efa
34 changed files with 1650 additions and 548 deletions
Download Patch File Download Diff File Expand all files Collapse all files

19
arch/arm/boot/dts/r8a7740-armadillo800eva.dts
View File

@@ -196,6 +196,19 @@ &cmt1 {
&i2c0 {
status = "okay";
wm8978: codec@1a {
#sound-dai-cells = <0>;
compatible = "wlf,wm8978";
reg = <0x1a>;
};
eeprom@50 {
compatible = "st,24c01", "atmel,24c01";
reg = <0x50>;
pagesize = <16>;
};
touchscreen@55 {
compatible = "sitronix,st1232";
reg = <0x55>;
@@ -205,12 +218,6 @@ touchscreen@55 {
pinctrl-names = "default";
gpios = <&pfc 166 GPIO_ACTIVE_LOW>;
};
wm8978: codec@1a {
#sound-dai-cells = <0>;
compatible = "wlf,wm8978";
reg = <0x1a>;
};
};
&i2c2 {

5
arch/arm64/boot/dts/renesas/Makefile
View File

@@ -28,10 +28,6 @@ dtb-$(CONFIG_ARCH_R8A774E1) += r8a774e1-hihope-rzg2h-ex.dtb
dtb-$(CONFIG_ARCH_R8A774E1) += r8a774e1-hihope-rzg2h-ex-idk-1110wr.dtb
dtb-$(CONFIG_ARCH_R8A774E1) += r8a774e1-hihope-rzg2h-ex-mipi-2.1.dtb
dtb-$(CONFIG_ARCH_R8A77950) += r8a77950-salvator-x.dtb
dtb-$(CONFIG_ARCH_R8A77950) += r8a77950-ulcb.dtb
dtb-$(CONFIG_ARCH_R8A77950) += r8a77950-ulcb-kf.dtb
dtb-$(CONFIG_ARCH_R8A77951) += r8a77951-salvator-x.dtb
dtb-$(CONFIG_ARCH_R8A77951) += r8a77951-salvator-xs.dtb
dtb-$(CONFIG_ARCH_R8A77951) += r8a77951-ulcb.dtb
@@ -67,6 +63,7 @@ dtb-$(CONFIG_ARCH_R8A779A0) += r8a779a0-falcon.dtb
dtb-$(CONFIG_ARCH_R8A779F0) += r8a779f0-spider.dtb
dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g0-white-hawk.dtb
dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g0-white-hawk-ard-audio-da7212.dtbo
dtb-$(CONFIG_ARCH_R8A77951) += r8a779m1-salvator-xs.dtb
dtb-$(CONFIG_ARCH_R8A77951) += r8a779m1-ulcb.dtb

3
arch/arm64/boot/dts/renesas/r8a774c0.dtsi
View File

@@ -49,17 +49,14 @@ cluster1_opp: opp-table-1 {
opp-shared;
opp-800000000 {
opp-hz = /bits/ 64 <800000000>;
opp-microvolt = <820000>;
clock-latency-ns = <300000>;
};
opp-1000000000 {
opp-hz = /bits/ 64 <1000000000>;
opp-microvolt = <820000>;
clock-latency-ns = <300000>;
};
opp-1200000000 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <820000>;
clock-latency-ns = <300000>;
opp-suspend;
};

49
arch/arm64/boot/dts/renesas/r8a77950-salvator-x.dts
View File

@@ -1,49 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the Salvator-X board with R-Car H3 ES1.x
*
* Copyright (C) 2015 Renesas Electronics Corp.
*/
/dts-v1/;
#include "r8a77950.dtsi"
#include "salvator-x.dtsi"
/ {
model = "Renesas Salvator-X board based on r8a77950";
compatible = "renesas,salvator-x", "renesas,r8a7795";
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
reg = <0x0 0x48000000 0x0 0x38000000>;
};
memory@500000000 {
device_type = "memory";
reg = <0x5 0x00000000 0x0 0x40000000>;
};
memory@600000000 {
device_type = "memory";
reg = <0x6 0x00000000 0x0 0x40000000>;
};
memory@700000000 {
device_type = "memory";
reg = <0x7 0x00000000 0x0 0x40000000>;
};
};
&du {
clocks = <&cpg CPG_MOD 724>,
<&cpg CPG_MOD 723>,
<&cpg CPG_MOD 722>,
<&cpg CPG_MOD 721>,
<&versaclock5 1>,
<&x21_clk>,
<&x22_clk>,
<&versaclock5 2>;
clock-names = "du.0", "du.1", "du.2", "du.3",
"dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3";
};

16
arch/arm64/boot/dts/renesas/r8a77950-ulcb-kf.dts
View File

@@ -1,16 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the H3ULCB Kingfisher board with R-Car H3 ES1.x
*
* Copyright (C) 2017 Renesas Electronics Corp.
* Copyright (C) 2017 Cogent Embedded, Inc.
*/
#include "r8a77950-ulcb.dts"
#include "ulcb-kf.dtsi"
/ {
model = "Renesas H3ULCB Kingfisher board based on r8a77950";
compatible = "shimafuji,kingfisher", "renesas,h3ulcb",
"renesas,r8a7795";
};

37
arch/arm64/boot/dts/renesas/r8a77950-ulcb.dts
View File

@@ -1,37 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the H3ULCB (R-Car Starter Kit Premier) board with R-Car H3 ES1.x
*
* Copyright (C) 2016 Renesas Electronics Corp.
* Copyright (C) 2016 Cogent Embedded, Inc.
*/
/dts-v1/;
#include "r8a77950.dtsi"
#include "ulcb.dtsi"
/ {
model = "Renesas H3ULCB board based on r8a77950";
compatible = "renesas,h3ulcb", "renesas,r8a7795";
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
reg = <0x0 0x48000000 0x0 0x38000000>;
};
memory@500000000 {
device_type = "memory";
reg = <0x5 0x00000000 0x0 0x40000000>;
};
memory@600000000 {
device_type = "memory";
reg = <0x6 0x00000000 0x0 0x40000000>;
};
memory@700000000 {
device_type = "memory";
reg = <0x7 0x00000000 0x0 0x40000000>;
};
};

330
arch/arm64/boot/dts/renesas/r8a77950.dtsi
View File

@@ -1,330 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the R-Car H3 (R8A77950) SoC
*
* Copyright (C) 2015 Renesas Electronics Corp.
*/
#include "r8a77951.dtsi"
#undef SOC_HAS_USB2_CH3
&audma0 {
iommus = <&ipmmu_mp1 0>, <&ipmmu_mp1 1>,
<&ipmmu_mp1 2>, <&ipmmu_mp1 3>,
<&ipmmu_mp1 4>, <&ipmmu_mp1 5>,
<&ipmmu_mp1 6>, <&ipmmu_mp1 7>,
<&ipmmu_mp1 8>, <&ipmmu_mp1 9>,
<&ipmmu_mp1 10>, <&ipmmu_mp1 11>,
<&ipmmu_mp1 12>, <&ipmmu_mp1 13>,
<&ipmmu_mp1 14>, <&ipmmu_mp1 15>;
};
&audma1 {
iommus = <&ipmmu_mp1 16>, <&ipmmu_mp1 17>,
<&ipmmu_mp1 18>, <&ipmmu_mp1 19>,
<&ipmmu_mp1 20>, <&ipmmu_mp1 21>,
<&ipmmu_mp1 22>, <&ipmmu_mp1 23>,
<&ipmmu_mp1 24>, <&ipmmu_mp1 25>,
<&ipmmu_mp1 26>, <&ipmmu_mp1 27>,
<&ipmmu_mp1 28>, <&ipmmu_mp1 29>,
<&ipmmu_mp1 30>, <&ipmmu_mp1 31>;
};
&cluster0_opp {
/delete-node/ opp-1600000000;
/delete-node/ opp-1700000000;
};
&du {
renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>, <&vspd3 0>;
};
&fcpvb1 {
iommus = <&ipmmu_vp0 7>;
};
&fcpf1 {
iommus = <&ipmmu_vp0 1>;
};
&fcpvi1 {
iommus = <&ipmmu_vp0 9>;
};
&fcpvd2 {
iommus = <&ipmmu_vi0 10>;
};
&gpio1 {
gpio-ranges = <&pfc 0 32 28>;
};
&ipmmu_vi0 {
renesas,ipmmu-main = <&ipmmu_mm 11>;
};
&ipmmu_vp0 {
renesas,ipmmu-main = <&ipmmu_mm 12>;
};
&ipmmu_vc0 {
renesas,ipmmu-main = <&ipmmu_mm 9>;
};
&ipmmu_vc1 {
renesas,ipmmu-main = <&ipmmu_mm 10>;
};
&ipmmu_rt {
renesas,ipmmu-main = <&ipmmu_mm 7>;
};
&soc {
/delete-node/ dma-controller@e6460000;
/delete-node/ dma-controller@e6470000;
ipmmu_mp1: iommu@ec680000 {
compatible = "renesas,ipmmu-r8a7795";
reg = <0 0xec680000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 5>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
ipmmu_sy: iommu@e7730000 {
compatible = "renesas,ipmmu-r8a7795";
reg = <0 0xe7730000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 8>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
/delete-node/ iommu@fd950000;
/delete-node/ iommu@fd960000;
/delete-node/ iommu@fd970000;
/delete-node/ iommu@febe0000;
/delete-node/ iommu@fe980000;
xhci1: usb@ee040000 {
compatible = "renesas,xhci-r8a7795", "renesas,rcar-gen3-xhci";
reg = <0 0xee040000 0 0xc00>;
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 327>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 327>;
status = "disabled";
};
/delete-node/ usb@e659c000;
/delete-node/ usb@ee0e0000;
/delete-node/ usb@ee0e0100;
/delete-node/ usb-phy@ee0e0200;
fdp1@fe948000 {
compatible = "renesas,fdp1";
reg = <0 0xfe948000 0 0x2400>;
interrupts = <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 117>;
power-domains = <&sysc R8A7795_PD_A3VP>;
resets = <&cpg 117>;
renesas,fcp = <&fcpf2>;
};
fcpf2: fcp@fe952000 {
compatible = "renesas,fcpf";
reg = <0 0xfe952000 0 0x200>;
clocks = <&cpg CPG_MOD 613>;
power-domains = <&sysc R8A7795_PD_A3VP>;
resets = <&cpg 613>;
iommus = <&ipmmu_vp0 2>;
};
fcpvd3: fcp@fea3f000 {
compatible = "renesas,fcpv";
reg = <0 0xfea3f000 0 0x200>;
clocks = <&cpg CPG_MOD 600>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 600>;
iommus = <&ipmmu_vi0 11>;
};
fcpvi2: fcp@fe9cf000 {
compatible = "renesas,fcpv";
reg = <0 0xfe9cf000 0 0x200>;
clocks = <&cpg CPG_MOD 609>;
power-domains = <&sysc R8A7795_PD_A3VP>;
resets = <&cpg 609>;
iommus = <&ipmmu_vp0 10>;
};
vspd3: vsp@fea38000 {
compatible = "renesas,vsp2";
reg = <0 0xfea38000 0 0x5000>;
interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 620>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 620>;
renesas,fcp = <&fcpvd3>;
};
vspi2: vsp@fe9c0000 {
compatible = "renesas,vsp2";
reg = <0 0xfe9c0000 0 0x8000>;
interrupts = <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 629>;
power-domains = <&sysc R8A7795_PD_A3VP>;
resets = <&cpg 629>;
renesas,fcp = <&fcpvi2>;
};
csi21: csi2@fea90000 {
compatible = "renesas,r8a7795-csi2";
reg = <0 0xfea90000 0 0x10000>;
interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 713>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 713>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
};
port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
csi21vin0: endpoint@0 {
reg = <0>;
remote-endpoint = <&vin0csi21>;
};
csi21vin1: endpoint@1 {
reg = <1>;
remote-endpoint = <&vin1csi21>;
};
csi21vin2: endpoint@2 {
reg = <2>;
remote-endpoint = <&vin2csi21>;
};
csi21vin3: endpoint@3 {
reg = <3>;
remote-endpoint = <&vin3csi21>;
};
csi21vin4: endpoint@4 {
reg = <4>;
remote-endpoint = <&vin4csi21>;
};
csi21vin5: endpoint@5 {
reg = <5>;
remote-endpoint = <&vin5csi21>;
};
csi21vin6: endpoint@6 {
reg = <6>;
remote-endpoint = <&vin6csi21>;
};
csi21vin7: endpoint@7 {
reg = <7>;
remote-endpoint = <&vin7csi21>;
};
};
};
};
};
&vin0 {
ports {
port@1 {
vin0csi21: endpoint@1 {
reg = <1>;
remote-endpoint = <&csi21vin0>;
};
};
};
};
&vin1 {
ports {
port@1 {
vin1csi21: endpoint@1 {
reg = <1>;
remote-endpoint = <&csi21vin1>;
};
};
};
};
&vin2 {
ports {
port@1 {
vin2csi21: endpoint@1 {
reg = <1>;
remote-endpoint = <&csi21vin2>;
};
};
};
};
&vin3 {
ports {
port@1 {
vin3csi21: endpoint@1 {
reg = <1>;
remote-endpoint = <&csi21vin3>;
};
};
};
};
&vin4 {
ports {
port@1 {
vin4csi21: endpoint@1 {
reg = <1>;
remote-endpoint = <&csi21vin4>;
};
};
};
};
&vin5 {
ports {
port@1 {
vin5csi21: endpoint@1 {
reg = <1>;
remote-endpoint = <&csi21vin5>;
};
};
};
};
&vin6 {
ports {
port@1 {
vin6csi21: endpoint@1 {
reg = <1>;
remote-endpoint = <&csi21vin6>;
};
};
};
};
&vin7 {
ports {
port@1 {
vin7csi21: endpoint@1 {
reg = <1>;
remote-endpoint = <&csi21vin7>;
};
};
};
};

1
arch/arm64/boot/dts/renesas/r8a77951.dtsi
View File

@@ -75,7 +75,6 @@ opp-1600000000 {
opp-hz = /bits/ 64 <1600000000>;
opp-microvolt = <900000>;
clock-latency-ns = <300000>;
turbo-mode;
};
opp-1700000000 {
opp-hz = /bits/ 64 <1700000000>;

2
arch/arm64/boot/dts/renesas/r8a77960.dtsi
View File

@@ -70,13 +70,11 @@ opp-1600000000 {
opp-hz = /bits/ 64 <1600000000>;
opp-microvolt = <900000>;
clock-latency-ns = <300000>;
turbo-mode;
};
opp-1700000000 {
opp-hz = /bits/ 64 <1700000000>;
opp-microvolt = <900000>;
clock-latency-ns = <300000>;
turbo-mode;
};
opp-1800000000 {
opp-hz = /bits/ 64 <1800000000>;

2
arch/arm64/boot/dts/renesas/r8a77961.dtsi
View File

@@ -70,13 +70,11 @@ opp-1600000000 {
opp-hz = /bits/ 64 <1600000000>;
opp-microvolt = <900000>;
clock-latency-ns = <300000>;
turbo-mode;
};
opp-1700000000 {
opp-hz = /bits/ 64 <1700000000>;
opp-microvolt = <900000>;
clock-latency-ns = <300000>;
turbo-mode;
};
opp-1800000000 {
opp-hz = /bits/ 64 <1800000000>;

2
arch/arm64/boot/dts/renesas/r8a77965.dtsi
View File

@@ -75,13 +75,11 @@ opp-1600000000 {
opp-hz = /bits/ 64 <1600000000>;
opp-microvolt = <900000>;
clock-latency-ns = <300000>;
turbo-mode;
};
opp-1700000000 {
opp-hz = /bits/ 64 <1700000000>;
opp-microvolt = <900000>;
clock-latency-ns = <300000>;
turbo-mode;
};
opp-1800000000 {
opp-hz = /bits/ 64 <1800000000>;

8
arch/arm64/boot/dts/renesas/r8a77980-condor.dts
View File

@@ -14,3 +14,11 @@ / {
model = "Renesas Condor board based on r8a77980";
compatible = "renesas,condor", "renesas,r8a77980";
};
&i2c0 {
eeprom@50 {
compatible = "rohm,br24t01", "atmel,24c01";
reg = <0x50>;
pagesize = <8>;
};
};

1
arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts
View File

@@ -122,6 +122,7 @@ &gether {
phy0: ethernet-phy@0 {
compatible = "ethernet-phy-id0022.1622",
"ethernet-phy-ieee802.3-c22";
rxc-skew-ps = <1500>;
reg = <0>;
interrupt-parent = <&gpio4>;
interrupts = <23 IRQ_TYPE_LEVEL_LOW>;

3
arch/arm64/boot/dts/renesas/r8a77990.dtsi
View File

@@ -49,17 +49,14 @@ cluster1_opp: opp-table-1 {
opp-shared;
opp-800000000 {
opp-hz = /bits/ 64 <800000000>;
opp-microvolt = <820000>;
clock-latency-ns = <300000>;
};
opp-1000000000 {
opp-hz = /bits/ 64 <1000000000>;
opp-microvolt = <820000>;
clock-latency-ns = <300000>;
};
opp-1200000000 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <820000>;
clock-latency-ns = <300000>;
opp-suspend;
};

11
arch/arm64/boot/dts/renesas/r8a779a0-falcon.dts
View File

@@ -37,8 +37,12 @@ phy0: ethernet-phy@0 {
};
};
&can_clk {
clock-frequency = <40000000>;
};
&canfd {
pinctrl-0 = <&canfd0_pins>, <&canfd1_pins>;
pinctrl-0 = <&canfd0_pins>, <&canfd1_pins>, <&can_clk_pins>;
pinctrl-names = "default";
status = "okay";
@@ -80,6 +84,11 @@ pins_mii {
};
can_clk_pins: can-clk {
groups = "can_clk";
function = "can_clk";
};
canfd0_pins: canfd0 {
groups = "canfd0_data";
function = "canfd0";

14
arch/arm64/boot/dts/renesas/r8a779a0.dtsi
View File

@@ -606,7 +606,8 @@ hscif3: serial@e66a0000 {
};
canfd: can@e6660000 {
compatible = "renesas,r8a779a0-canfd";
compatible = "renesas,r8a779a0-canfd",
"renesas,rcar-gen4-canfd";
reg = <0 0xe6660000 0 0x8000>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
@@ -2209,8 +2210,7 @@ gic: interrupt-controller@f1000000 {
interrupt-controller;
reg = <0x0 0xf1000000 0 0x20000>,
<0x0 0xf1060000 0 0x110000>;
interrupts = <GIC_PPI 9
(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
fcpvd0: fcp@fea10000 {
@@ -2857,9 +2857,9 @@ sensor5_crit: sensor5-crit {
timer {
compatible = "arm,armv8-timer";
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
};
};

17
arch/arm64/boot/dts/renesas/r8a779f0.dtsi
View File

@@ -1108,8 +1108,7 @@ gic: interrupt-controller@f1000000 {
interrupt-controller;
reg = <0x0 0xf1000000 0 0x20000>,
<0x0 0xf1060000 0 0x110000>;
interrupts = <GIC_PPI 9
(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
prr: chipid@fff00044 {
@@ -1119,7 +1118,7 @@ prr: chipid@fff00044 {
};
thermal-zones {
sensor_thermal1: sensor1-thermal {
sensor_thermal_rtcore: sensor1-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsc 0>;
@@ -1133,7 +1132,7 @@ sensor1_crit: sensor1-crit {
};
};
sensor_thermal2: sensor2-thermal {
sensor_thermal_apcore0: sensor2-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsc 1>;
@@ -1147,7 +1146,7 @@ sensor2_crit: sensor2-crit {
};
};
sensor_thermal3: sensor3-thermal {
sensor_thermal_apcore4: sensor3-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsc 2>;
@@ -1164,10 +1163,10 @@ sensor3_crit: sensor3-crit {
timer {
compatible = "arm,armv8-timer";
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
};
ufs30_clk: ufs30-clk {

187
arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-ard-audio-da7212.dtso Normal file
View File

@@ -0,0 +1,187 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the White Hawk board with ARD-AUDIO-DA7212 Board
*
* You can find and buy "ARD-AUDIO-DA7212" at Digi-Key
*
* https://www.digikey.jp/en/products/detail/ARD-AUDIO-DA7212/1564-1021-ND/5456357
*
* Copyright (C) 2022 Renesas Electronics Corp.
*
*
* [Connection]
*
* White Hawk ARD-AUDIO-DA7212
* +----------------------------+
* |CPU board |
* | |
* |CN40 (IO PIN HEADER) |
* | AUDIO_CLKIN_V pin1 |<--\ +---------------+
* |(*) GP1_25/SL_SW2_V pin2 |<--/ |J2 |
* | AUDIO_CLKOUT_V pin5 |<----->| pin7 MCLK |
* | SSI_SCK_V pin9 |<----->| pin1 BCLK |
* | SSI_WS_V pin13 |<----->| pin3 WCLK |
* | SSI_SD_V pin15 |<----->| pin5 DATIN | (@)
* | | \-->| pin15 DATOUT | [CAPTURE]
* +----------------------------+ +---------------+
* +----------------------------+
* |Breakout board |
* | | +---------------+
* |CN34 (I2C CN) | |J1 |
* | I2C0_SCL pin3 |<----->| pin20 SCL |
* | I2C0_SDA pin5 |<----->| pin18 SDA |
* | | +---------------+
* | | +-----------------------+
* |CN4 (Power) | |J7 |
* | 3v3 (v) pin9 |<----->| pin4 / pin8 3.3v |
* | GND (v) pin3 / pin4 |<----->| pin12 / pin14 GND |
* +----------------------------+ +-----------------------+
* (*) GP1_25/SL_SW2_V is used as TPU
* (@) Connect to pin5 (DATIN = playback) or pin15 (DATOUT = capture)
* (v) These are just sample pins. You can find many 3v3 / GND pins on
* White Hawk board, not only CN4. You can use other pins for it.
*
* [How to enable]
*
* You need these configs
*
* CONFIG_PWM
* CONFIG_PWM_RENESAS_TPU
* CONFIG_COMMON_CLK_PWM
* CONFIG_SND_SOC_DA7213
*
* [How to use]
*
* 44.1kHz groups sound is available by default.
* You need to update audio_clkin settings to switch to 48kHz groups sound.
* see
* [(C) clock]
*
* You can use capture if you change the settings
* see
* [CAPTURE]
*
* You need to setup Headphone
*
* > amixer set "Headphone" 40%
* > amixer set "Headphone" on
* > amixer set "Mixout Left DAC Left" on
* > amixer set "Mixout Right DAC Right" on
*/
/dts-v1/;
/plugin/;
#include <dt-bindings/clock/r8a779g0-cpg-mssr.h>
&{/} {
sound_card: sound {
compatible = "audio-graph-card";
label = "rcar-sound";
dais = <&rsnd_port>; /* DA7212 Audio Codec */
};
tpu_clk: tpu-clk {
compatible = "pwm-clock";
#clock-cells = <0>;
/* 44.1kHz groups [(C) clock] */
clock-frequency = <11289600>;
pwms = <&tpu 0 88 0>; /* 1000000000 / 88 =~ 11289600 */
/* 48 kHz groups [(C) clock] */
// clock-frequency = <12288000>;
// pwms = <&tpu 0 81 0>; /* 1000000000 / 81 =~ 12288000 */
};
};
&pfc {
sound_pins: sound {
groups = "ssi_ctrl", "ssi_data";
function = "ssi";
};
sound_clk_pins: sound-clk {
groups = "audio_clkin", "audio_clkout";
function = "audio_clk";
};
tpu0_pins: tpu0 {
groups = "tpu_to0_a";
function = "tpu";
};
};
&tpu {
pinctrl-0 = <&tpu0_pins>;
pinctrl-names = "default";
status = "okay";
};
&i2c0 {
#address-cells = <1>;
#size-cells = <0>;
codec@1a {
compatible = "dlg,da7212";
#sound-dai-cells = <0>;
reg = <0x1a>;
clocks = <&rcar_sound>;
clock-names = "mclk";
dlg,micbias1-lvl = <2500>;
dlg,micbias2-lvl = <2500>;
dlg,dmic-data-sel = "lrise_rfall";
dlg,dmic-samplephase = "between_clkedge";
dlg,dmic-clkrate = <3000000>;
VDDA-supply = <&reg_1p8v>;
VDDMIC-supply = <&reg_3p3v>;
VDDIO-supply = <&reg_3p3v>;
port {
da7212_endpoint: endpoint {
remote-endpoint = <&rsnd_endpoint>;
};
};
};
};
&rcar_sound {
pinctrl-0 = <&sound_clk_pins>, <&sound_pins>;
pinctrl-names = "default";
/* Single DAI */
#sound-dai-cells = <0>;
/* audio_clkout */
#clock-cells = <0>;
clock-frequency = <5644800>; /* 44.1kHz groups [(C) clock] */
// clock-frequency = <6144000>; /* 48 kHz groups [(C) clock] */
status = "okay";
/* Update <clkin> to <tpu_clk> */
clocks = <&cpg CPG_MOD 2926>, <&cpg CPG_MOD 2927>, <&tpu_clk>;
ports {
rsnd_port: port {
rsnd_endpoint: endpoint {
remote-endpoint = <&da7212_endpoint>;
dai-format = "i2s";
bitclock-master = <&rsnd_endpoint>;
frame-master = <&rsnd_endpoint>;
/* Mutually exclusive with 'capture' */
playback = <&ssi0>;
/* [CAPTURE] */
/* capture = <&ssi0>; */
};
};
};
};

172
arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-csi-dsi.dtsi
View File

@@ -5,7 +5,63 @@
* Copyright (C) 2022 Glider bv
*/
#include <dt-bindings/media/video-interfaces.h>
&csi40 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
csi40_in: endpoint {
bus-type = <MEDIA_BUS_TYPE_CSI2_CPHY>;
clock-lanes = <0>;
data-lanes = <1 2 3>;
remote-endpoint = <&max96712_out0>;
};
};
};
};
&csi41 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
csi41_in: endpoint {
bus-type = <MEDIA_BUS_TYPE_CSI2_CPHY>;
clock-lanes = <0>;
data-lanes = <1 2 3>;
remote-endpoint = <&max96712_out1>;
};
};
};
};
&i2c0 {
pca9654_a: gpio@21 {
compatible = "onnn,pca9654";
reg = <0x21>;
gpio-controller;
#gpio-cells = <2>;
};
pca9654_b: gpio@22 {
compatible = "onnn,pca9654";
reg = <0x22>;
gpio-controller;
#gpio-cells = <2>;
};
eeprom@52 {
compatible = "rohm,br24g01", "atmel,24c01";
label = "csi-dsi-sub-board-id";
@@ -13,3 +69,119 @@ eeprom@52 {
pagesize = <8>;
};
};
&i2c1 {
gmsl0: gmsl-deserializer@49 {
compatible = "maxim,max96712";
reg = <0x49>;
enable-gpios = <&pca9654_a 0 GPIO_ACTIVE_HIGH>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@4 {
reg = <4>;
max96712_out0: endpoint {
bus-type = <MEDIA_BUS_TYPE_CSI2_CPHY>;
clock-lanes = <0>;
data-lanes = <1 2 3>;
remote-endpoint = <&csi40_in>;
};
};
};
};
gmsl1: gmsl-deserializer@4b {
compatible = "maxim,max96712";
reg = <0x4b>;
enable-gpios = <&pca9654_b 0 GPIO_ACTIVE_HIGH>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@4 {
reg = <4>;
max96712_out1: endpoint {
bus-type = <MEDIA_BUS_TYPE_CSI2_CPHY>;
clock-lanes = <0>;
data-lanes = <1 2 3>;
remote-endpoint = <&csi41_in>;
};
};
};
};
};
&isp0 {
status = "okay";
};
&isp1 {
status = "okay";
};
&vin00 {
status = "okay";
};
&vin01 {
status = "okay";
};
&vin02 {
status = "okay";
};
&vin03 {
status = "okay";
};
&vin04 {
status = "okay";
};
&vin05 {
status = "okay";
};
&vin06 {
status = "okay";
};
&vin07 {
status = "okay";
};
&vin08 {
status = "okay";
};
&vin09 {
status = "okay";
};
&vin10 {
status = "okay";
};
&vin11 {
status = "okay";
};
&vin12 {
status = "okay";
};
&vin13 {
status = "okay";
};
&vin14 {
status = "okay";
};
&vin15 {
status = "okay";
};

44
arch/arm64/boot/dts/renesas/r8a779g0-white-hawk.dts
View File

@@ -13,6 +13,33 @@
/ {
model = "Renesas White Hawk CPU and Breakout boards based on r8a779g0";
compatible = "renesas,white-hawk-breakout", "renesas,white-hawk-cpu", "renesas,r8a779g0";
can_transceiver0: can-phy0 {
compatible = "nxp,tjr1443";
#phy-cells = <0>;
enable-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
max-bitrate = <5000000>;
};
};
&can_clk {
clock-frequency = <40000000>;
};
&canfd {
pinctrl-0 = <&canfd0_pins>, <&canfd1_pins>, <&can_clk_pins>;
pinctrl-names = "default";
status = "okay";
channel0 {
status = "okay";
phys = <&can_transceiver0>;
};
channel1 {
status = "okay";
};
};
&i2c0 {
@@ -23,3 +50,20 @@ eeprom@51 {
pagesize = <8>;
};
};
&pfc {
can_clk_pins: can-clk {
groups = "can_clk";
function = "can_clk";
};
canfd0_pins: canfd0 {
groups = "canfd0_data";
function = "canfd0";
};
canfd1_pins: canfd1 {
groups = "canfd1_data";
function = "canfd1";
};
};

880
arch/arm64/boot/dts/renesas/r8a779g0.dtsi
View File

@@ -14,6 +14,20 @@ / {
#address-cells = <2>;
#size-cells = <2>;
/* External Audio clock - to be overridden by boards that provide it */
audio_clkin: audio_clkin {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
/* External CAN clock - to be overridden by boards that provide it */
can_clk: can {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
cluster0_opp: opp-table-0 {
compatible = "operating-points-v2";
opp-shared;
@@ -431,6 +445,18 @@ sysc: system-controller@e6180000 {
#power-domain-cells = <1>;
};
tsc: thermal@e6198000 {
compatible = "renesas,r8a779g0-thermal";
reg = <0 0xe6198000 0 0x200>,
<0 0xe61a0000 0 0x200>,
<0 0xe61a8000 0 0x200>,
<0 0xe61b0000 0 0x200>;
clocks = <&cpg CPG_MOD 919>;
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
resets = <&cpg 919>;
#thermal-sensor-cells = <1>;
};
intc_ex: interrupt-controller@e61c0000 {
compatible = "renesas,intc-ex-r8a779g0", "renesas,irqc";
#interrupt-cells = <2>;
@@ -682,6 +708,56 @@ hscif3: serial@e66a0000 {
status = "disabled";
};
canfd: can@e6660000 {
compatible = "renesas,r8a779g0-canfd",
"renesas,rcar-gen4-canfd";
reg = <0 0xe6660000 0 0x8500>;
interrupts = <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch_int", "g_int";
clocks = <&cpg CPG_MOD 328>,
<&cpg CPG_CORE R8A779G0_CLK_CANFD>,
<&can_clk>;
clock-names = "fck", "canfd", "can_clk";
assigned-clocks = <&cpg CPG_CORE R8A779G0_CLK_CANFD>;
assigned-clock-rates = <80000000>;
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
resets = <&cpg 328>;
status = "disabled";
channel0 {
status = "disabled";
};
channel1 {
status = "disabled";
};
channel2 {
status = "disabled";
};
channel3 {
status = "disabled";
};
channel4 {
status = "disabled";
};
channel5 {
status = "disabled";
};
channel6 {
status = "disabled";
};
channel7 {
status = "disabled";
};
};
avb0: ethernet@e6800000 {
compatible = "renesas,etheravb-r8a779g0",
"renesas,etheravb-rcar-gen4";
@@ -1098,6 +1174,454 @@ msiof5: spi@e6c28000 {
status = "disabled";
};
vin00: video@e6ef0000 {
compatible = "renesas,vin-r8a779g0";
reg = <0 0xe6ef0000 0 0x1000>;
interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 730>;
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
resets = <&cpg 730>;
renesas,id = <0>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
vin00isp0: endpoint@0 {
reg = <0>;
remote-endpoint = <&isp0vin00>;
};
};
};
};
vin01: video@e6ef1000 {
compatible = "renesas,vin-r8a779g0";
reg = <0 0xe6ef1000 0 0x1000>;
interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 731>;
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
resets = <&cpg 731>;
renesas,id = <1>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
vin01isp0: endpoint@0 {
reg = <0>;
remote-endpoint = <&isp0vin01>;
};
};
};
};
vin02: video@e6ef2000 {
compatible = "renesas,vin-r8a779g0";
reg = <0 0xe6ef2000 0 0x1000>;
interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 800>;
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
resets = <&cpg 800>;
renesas,id = <2>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
vin02isp0: endpoint@0 {
reg = <0>;
remote-endpoint = <&isp0vin02>;
};
};
};
};
vin03: video@e6ef3000 {
compatible = "renesas,vin-r8a779g0";
reg = <0 0xe6ef3000 0 0x1000>;
interrupts = <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 801>;
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
resets = <&cpg 801>;
renesas,id = <3>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
vin03isp0: endpoint@0 {
reg = <0>;
remote-endpoint = <&isp0vin03>;
};
};
};
};
vin04: video@e6ef4000 {
compatible = "renesas,vin-r8a779g0";
reg = <0 0xe6ef4000 0 0x1000>;
interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 802>;
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
resets = <&cpg 802>;
renesas,id = <4>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
vin04isp0: endpoint@0 {
reg = <0>;
remote-endpoint = <&isp0vin04>;
};
};
};
};
vin05: video@e6ef5000 {
compatible = "renesas,vin-r8a779g0";
reg = <0 0xe6ef5000 0 0x1000>;
interrupts = <GIC_SPI 534 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 803>;
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
resets = <&cpg 803>;
renesas,id = <5>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
vin05isp0: endpoint@0 {
reg = <0>;
remote-endpoint = <&isp0vin05>;
};
};
};
};
vin06: video@e6ef6000 {
compatible = "renesas,vin-r8a779g0";
reg = <0 0xe6ef6000 0 0x1000>;
interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 804>;
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
resets = <&cpg 804>;
renesas,id = <6>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
vin06isp0: endpoint@0 {
reg = <0>;
remote-endpoint = <&isp0vin06>;
};
};
};
};
vin07: video@e6ef7000 {
compatible = "renesas,vin-r8a779g0";
reg = <0 0xe6ef7000 0 0x1000>;
interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 805>;
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
resets = <&cpg 805>;
renesas,id = <7>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
vin07isp0: endpoint@0 {
reg = <0>;
remote-endpoint = <&isp0vin07>;
};
};
};
};
vin08: video@e6ef8000 {
compatible = "renesas,vin-r8a779g0";
reg = <0 0xe6ef8000 0 0x1000>;
interrupts = <GIC_SPI 537 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 806>;
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
resets = <&cpg 806>;
renesas,id = <8>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
vin08isp1: endpoint@1 {
reg = <1>;
remote-endpoint = <&isp1vin08>;
};
};
};
};
vin09: video@e6ef9000 {
compatible = "renesas,vin-r8a779g0";
reg = <0 0xe6ef9000 0 0x1000>;
interrupts = <GIC_SPI 538 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 807>;
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
resets = <&cpg 807>;
renesas,id = <9>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
vin09isp1: endpoint@1 {
reg = <1>;
remote-endpoint = <&isp1vin09>;
};
};
};
};
vin10: video@e6efa000 {
compatible = "renesas,vin-r8a779g0";
reg = <0 0xe6efa000 0 0x1000>;
interrupts = <GIC_SPI 539 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 808>;
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
resets = <&cpg 808>;
renesas,id = <10>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
vin10isp1: endpoint@1 {
reg = <1>;
remote-endpoint = <&isp1vin10>;
};
};
};
};
vin11: video@e6efb000 {
compatible = "renesas,vin-r8a779g0";
reg = <0 0xe6efb000 0 0x1000>;
interrupts = <GIC_SPI 540 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 809>;
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
resets = <&cpg 809>;
renesas,id = <11>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
vin11isp1: endpoint@1 {
reg = <1>;
remote-endpoint = <&isp1vin11>;
};
};
};
};
vin12: video@e6efc000 {
compatible = "renesas,vin-r8a779g0";
reg = <0 0xe6efc000 0 0x1000>;
interrupts = <GIC_SPI 541 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 810>;
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
resets = <&cpg 810>;
renesas,id = <12>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
vin12isp1: endpoint@1 {
reg = <1>;
remote-endpoint = <&isp1vin12>;
};
};
};
};
vin13: video@e6efd000 {
compatible = "renesas,vin-r8a779g0";
reg = <0 0xe6efd000 0 0x1000>;
interrupts = <GIC_SPI 542 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 811>;
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
resets = <&cpg 811>;
renesas,id = <13>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
vin13isp1: endpoint@1 {
reg = <1>;
remote-endpoint = <&isp1vin13>;
};
};
};
};
vin14: video@e6efe000 {
compatible = "renesas,vin-r8a779g0";
reg = <0 0xe6efe000 0 0x1000>;
interrupts = <GIC_SPI 543 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 812>;
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
resets = <&cpg 812>;
renesas,id = <14>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
vin14isp1: endpoint@1 {
reg = <1>;
remote-endpoint = <&isp1vin14>;
};
};
};
};
vin15: video@e6eff000 {
compatible = "renesas,vin-r8a779g0";
reg = <0 0xe6eff000 0 0x1000>;
interrupts = <GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 813>;
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
resets = <&cpg 813>;
renesas,id = <15>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
vin15isp1: endpoint@1 {
reg = <1>;
remote-endpoint = <&isp1vin15>;
};
};
};
};
dmac0: dma-controller@e7350000 {
compatible = "renesas,dmac-r8a779g0",
"renesas,rcar-gen4-dmac";
@@ -1168,6 +1692,75 @@ dmac1: dma-controller@e7351000 {
dma-channels = <16>;
};
rcar_sound: sound@ec5a0000 {
/*
* #sound-dai-cells is required
*
* Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
* Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
*/
/*
* #clock-cells is required
*
* clkout : #clock-cells = <0>; <&rcar_sound>;
* audio_clkout0/1/2/3 : #clock-cells = <1>; <&rcar_sound N>;
*/
compatible = "renesas,rcar_sound-r8a779g0", "renesas,rcar_sound-gen4";
reg = <0 0xec5a0000 0 0x020>,
<0 0xec540000 0 0x1000>,
<0 0xec541000 0 0x050>,
<0 0xec400000 0 0x40000>;
reg-names = "adg", "ssiu", "ssi", "sdmc";
clocks = <&cpg CPG_MOD 2926>, <&cpg CPG_MOD 2927>, <&audio_clkin>;
clock-names = "ssiu.0", "ssi.0", "clkin";
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
resets = <&cpg 2926>, <&cpg 2927>;
reset-names = "ssiu.0", "ssi.0";
status = "disabled";
rcar_sound,ssiu {
ssiu00: ssiu-0 {
dmas = <&dmac0 0x6e>, <&dmac0 0x6f>;
dma-names = "tx", "rx";
};
ssiu01: ssiu-1 {
dmas = <&dmac0 0x6c>, <&dmac0 0x6d>;
dma-names = "tx", "rx";
};
ssiu02: ssiu-2 {
dmas = <&dmac0 0x6a>, <&dmac0 0x6b>;
dma-names = "tx", "rx";
};
ssiu03: ssiu-3 {
dmas = <&dmac0 0x68>, <&dmac0 0x69>;
dma-names = "tx", "rx";
};
ssiu04: ssiu-4 {
dmas = <&dmac0 0x66>, <&dmac0 0x67>;
dma-names = "tx", "rx";
};
ssiu05: ssiu-5 {
dmas = <&dmac0 0x64>, <&dmac0 0x65>;
dma-names = "tx", "rx";
};
ssiu06: ssiu-6 {
dmas = <&dmac0 0x62>, <&dmac0 0x63>;
dma-names = "tx", "rx";
};
ssiu07: ssiu-7 {
dmas = <&dmac0 0x60>, <&dmac0 0x61>;
dma-names = "tx", "rx";
};
};
rcar_sound,ssi {
ssi0: ssi-0 {
interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>;
};
};
};
mmc0: mmc@ee140000 {
compatible = "renesas,sdhi-r8a779g0",
"renesas,rcar-gen4-sdhi";
@@ -1205,8 +1798,59 @@ gic: interrupt-controller@f1000000 {
interrupt-controller;
reg = <0x0 0xf1000000 0 0x20000>,
<0x0 0xf1060000 0 0x110000>;
interrupts = <GIC_PPI 9
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
csi40: csi2@fe500000 {
compatible = "renesas,r8a779g0-csi2";
reg = <0 0xfe500000 0 0x40000>;
interrupts = <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 331>;
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
resets = <&cpg 331>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
};
port@1 {
reg = <1>;
csi40isp0: endpoint {
remote-endpoint = <&isp0csi40>;
};
};
};
};
csi41: csi2@fe540000 {
compatible = "renesas,r8a779g0-csi2";
reg = <0 0xfe540000 0 0x40000>;
interrupts = <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 400>;
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
resets = <&cpg 400>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
};
port@1 {
reg = <1>;
csi41isp1: endpoint {
remote-endpoint = <&isp1csi41>;
};
};
};
};
fcpvd0: fcp@fea10000 {
@@ -1281,6 +1925,172 @@ du_out_dsi1: endpoint {
};
};
isp0: isp@fed00000 {
compatible = "renesas,r8a779g0-isp";
reg = <0 0xfed00000 0 0x10000>;
interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_LOW>;
clocks = <&cpg CPG_MOD 612>;
power-domains = <&sysc R8A779G0_PD_A3ISP0>;
resets = <&cpg 612>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
isp0csi40: endpoint@0 {
reg = <0>;
remote-endpoint = <&csi40isp0>;
};
};
port@1 {
reg = <1>;
isp0vin00: endpoint {
remote-endpoint = <&vin00isp0>;
};
};
port@2 {
reg = <2>;
isp0vin01: endpoint {
remote-endpoint = <&vin01isp0>;
};
};
port@3 {
reg = <3>;
isp0vin02: endpoint {
remote-endpoint = <&vin02isp0>;
};
};
port@4 {
reg = <4>;
isp0vin03: endpoint {
remote-endpoint = <&vin03isp0>;
};
};
port@5 {
reg = <5>;
isp0vin04: endpoint {
remote-endpoint = <&vin04isp0>;
};
};
port@6 {
reg = <6>;
isp0vin05: endpoint {
remote-endpoint = <&vin05isp0>;
};
};
port@7 {
reg = <7>;
isp0vin06: endpoint {
remote-endpoint = <&vin06isp0>;
};
};
port@8 {
reg = <8>;
isp0vin07: endpoint {
remote-endpoint = <&vin07isp0>;
};
};
};
};
isp1: isp@fed20000 {
compatible = "renesas,r8a779g0-isp";
reg = <0 0xfed20000 0 0x10000>;
interrupts = <GIC_SPI 474 IRQ_TYPE_LEVEL_LOW>;
clocks = <&cpg CPG_MOD 613>;
power-domains = <&sysc R8A779G0_PD_A3ISP1>;
resets = <&cpg 613>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
isp1csi41: endpoint@1 {
reg = <1>;
remote-endpoint = <&csi41isp1>;
};
};
port@1 {
reg = <1>;
isp1vin08: endpoint {
remote-endpoint = <&vin08isp1>;
};
};
port@2 {
reg = <2>;
isp1vin09: endpoint {
remote-endpoint = <&vin09isp1>;
};
};
port@3 {
reg = <3>;
isp1vin10: endpoint {
remote-endpoint = <&vin10isp1>;
};
};
port@4 {
reg = <4>;
isp1vin11: endpoint {
remote-endpoint = <&vin11isp1>;
};
};
port@5 {
reg = <5>;
isp1vin12: endpoint {
remote-endpoint = <&vin12isp1>;
};
};
port@6 {
reg = <6>;
isp1vin13: endpoint {
remote-endpoint = <&vin13isp1>;
};
};
port@7 {
reg = <7>;
isp1vin14: endpoint {
remote-endpoint = <&vin14isp1>;
};
};
port@8 {
reg = <8>;
isp1vin15: endpoint {
remote-endpoint = <&vin15isp1>;
};
};
};
};
dsi0: dsi-encoder@fed80000 {
compatible = "renesas,r8a779g0-dsi-csi2-tx";
reg = <0 0xfed80000 0 0x10000>;
@@ -1345,11 +2155,69 @@ prr: chipid@fff00044 {
};
};
thermal-zones {
sensor_thermal_cr52: sensor1-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsc 0>;
trips {
sensor1_crit: sensor1-crit {
temperature = <120000>;
hysteresis = <1000>;
type = "critical";
};
};
};
sensor_thermal_cnn: sensor2-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsc 1>;
trips {
sensor2_crit: sensor2-crit {
temperature = <120000>;
hysteresis = <1000>;
type = "critical";
};
};
};
sensor_thermal_ca76: sensor3-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsc 2>;
trips {
sensor3_crit: sensor3-crit {
temperature = <120000>;
hysteresis = <1000>;
type = "critical";
};
};
};
sensor_thermal_ddr1: sensor4-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsc 3>;
trips {
sensor4_crit: sensor4-crit {
temperature = <120000>;
hysteresis = <1000>;
type = "critical";
};
};
};
};
timer {
compatible = "arm,armv8-timer";
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
};
};

3
arch/arm64/boot/dts/renesas/r8a779m1.dtsi
View File

@@ -12,6 +12,9 @@ / {
};
&cluster0_opp {
opp-1700000000 {
/delete-property/ turbo-mode;
};
opp-2000000000 {
opp-hz = /bits/ 64 <2000000000>;
opp-microvolt = <960000>;

3
arch/arm64/boot/dts/renesas/r8a779m3.dtsi
View File

@@ -12,6 +12,9 @@ / {
};
&cluster0_opp {
opp-1800000000 {
/delete-property/ turbo-mode;
};
opp-2000000000 {
opp-hz = /bits/ 64 <2000000000>;
opp-microvolt = <960000>;

3
arch/arm64/boot/dts/renesas/r8a779m5.dtsi
View File

@@ -12,6 +12,9 @@ / {
};
&cluster0_opp {
opp-1800000000 {
/delete-property/ turbo-mode;
};
opp-2000000000 {
opp-hz = /bits/ 64 <2000000000>;
opp-microvolt = <960000>;

19
arch/arm64/boot/dts/renesas/r9a07g043.dtsi
View File

@@ -80,9 +80,8 @@ ssi0: ssi@10049c00 {
reg = <0 0x10049c00 0 0x400>;
interrupts = <SOC_PERIPHERAL_IRQ(326) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(327) IRQ_TYPE_EDGE_RISING>,
<SOC_PERIPHERAL_IRQ(328) IRQ_TYPE_EDGE_RISING>,
<SOC_PERIPHERAL_IRQ(329) IRQ_TYPE_EDGE_RISING>;
interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
<SOC_PERIPHERAL_IRQ(328) IRQ_TYPE_EDGE_RISING>;
interrupt-names = "int_req", "dma_rx", "dma_tx";
clocks = <&cpg CPG_MOD R9A07G043_SSI0_PCLK2>,
<&cpg CPG_MOD R9A07G043_SSI0_PCLK_SFR>,
<&audio_clk1>, <&audio_clk2>;
@@ -101,9 +100,8 @@ ssi1: ssi@1004a000 {
reg = <0 0x1004a000 0 0x400>;
interrupts = <SOC_PERIPHERAL_IRQ(330) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(331) IRQ_TYPE_EDGE_RISING>,
<SOC_PERIPHERAL_IRQ(332) IRQ_TYPE_EDGE_RISING>,
<SOC_PERIPHERAL_IRQ(333) IRQ_TYPE_EDGE_RISING>;
interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
<SOC_PERIPHERAL_IRQ(332) IRQ_TYPE_EDGE_RISING>;
interrupt-names = "int_req", "dma_rx", "dma_tx";
clocks = <&cpg CPG_MOD R9A07G043_SSI1_PCLK2>,
<&cpg CPG_MOD R9A07G043_SSI1_PCLK_SFR>,
<&audio_clk1>, <&audio_clk2>;
@@ -121,10 +119,8 @@ ssi2: ssi@1004a400 {
"renesas,rz-ssi";
reg = <0 0x1004a400 0 0x400>;
interrupts = <SOC_PERIPHERAL_IRQ(334) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(335) IRQ_TYPE_EDGE_RISING>,
<SOC_PERIPHERAL_IRQ(336) IRQ_TYPE_EDGE_RISING>,
<SOC_PERIPHERAL_IRQ(337) IRQ_TYPE_EDGE_RISING>;
interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
interrupt-names = "int_req", "dma_rt";
clocks = <&cpg CPG_MOD R9A07G043_SSI2_PCLK2>,
<&cpg CPG_MOD R9A07G043_SSI2_PCLK_SFR>,
<&audio_clk1>, <&audio_clk2>;
@@ -143,9 +139,8 @@ ssi3: ssi@1004a800 {
reg = <0 0x1004a800 0 0x400>;
interrupts = <SOC_PERIPHERAL_IRQ(338) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(339) IRQ_TYPE_EDGE_RISING>,
<SOC_PERIPHERAL_IRQ(340) IRQ_TYPE_EDGE_RISING>,
<SOC_PERIPHERAL_IRQ(341) IRQ_TYPE_EDGE_RISING>;
interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
<SOC_PERIPHERAL_IRQ(340) IRQ_TYPE_EDGE_RISING>;
interrupt-names = "int_req", "dma_rx", "dma_tx";
clocks = <&cpg CPG_MOD R9A07G043_SSI3_PCLK2>,
<&cpg CPG_MOD R9A07G043_SSI3_PCLK_SFR>,
<&audio_clk1>, <&audio_clk2>;

13
arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
View File

@@ -35,6 +35,11 @@ L3_CA55: cache-controller-0 {
};
};
pmu {
compatible = "arm,cortex-a55-pmu";
interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
};
psci {
compatible = "arm,psci-1.0", "arm,psci-0.2";
method = "smc";
@@ -42,10 +47,10 @@ psci {
timer {
compatible = "arm,armv8-timer";
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
};
};

32
arch/arm64/boot/dts/renesas/r9a07g044.dtsi
View File

@@ -157,6 +157,11 @@ opp-50000000 {
};
};
pmu {
compatible = "arm,cortex-a55-pmu";
interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
};
psci {
compatible = "arm,psci-1.0", "arm,psci-0.2";
method = "smc";
@@ -175,9 +180,8 @@ ssi0: ssi@10049c00 {
reg = <0 0x10049c00 0 0x400>;
interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 327 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 328 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 329 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
<GIC_SPI 328 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "int_req", "dma_rx", "dma_tx";
clocks = <&cpg CPG_MOD R9A07G044_SSI0_PCLK2>,
<&cpg CPG_MOD R9A07G044_SSI0_PCLK_SFR>,
<&audio_clk1>, <&audio_clk2>;
@@ -196,9 +200,8 @@ ssi1: ssi@1004a000 {
reg = <0 0x1004a000 0 0x400>;
interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 331 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 332 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 333 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
<GIC_SPI 332 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "int_req", "dma_rx", "dma_tx";
clocks = <&cpg CPG_MOD R9A07G044_SSI1_PCLK2>,
<&cpg CPG_MOD R9A07G044_SSI1_PCLK_SFR>,
<&audio_clk1>, <&audio_clk2>;
@@ -216,10 +219,8 @@ ssi2: ssi@1004a400 {
"renesas,rz-ssi";
reg = <0 0x1004a400 0 0x400>;
interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 335 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 336 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 337 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
interrupt-names = "int_req", "dma_rt";
clocks = <&cpg CPG_MOD R9A07G044_SSI2_PCLK2>,
<&cpg CPG_MOD R9A07G044_SSI2_PCLK_SFR>,
<&audio_clk1>, <&audio_clk2>;
@@ -238,9 +239,8 @@ ssi3: ssi@1004a800 {
reg = <0 0x1004a800 0 0x400>;
interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 339 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 340 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 341 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
<GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "int_req", "dma_rx", "dma_tx";
clocks = <&cpg CPG_MOD R9A07G044_SSI3_PCLK2>,
<&cpg CPG_MOD R9A07G044_SSI3_PCLK_SFR>,
<&audio_clk1>, <&audio_clk2>;
@@ -1061,9 +1061,9 @@ target: trip-point {
timer {
compatible = "arm,armv8-timer";
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
};
};

7
arch/arm64/boot/dts/renesas/r9a07g044c1.dtsi
View File

@@ -15,13 +15,6 @@ cpus {
/delete-node/ cpu-map;
/delete-node/ cpu@100;
};
timer {
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
};
};
&soc {

7
arch/arm64/boot/dts/renesas/r9a07g044l1.dtsi
View File

@@ -15,11 +15,4 @@ cpus {
/delete-node/ cpu-map;
/delete-node/ cpu@100;
};
timer {
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
};
};

32
arch/arm64/boot/dts/renesas/r9a07g054.dtsi
View File

@@ -157,6 +157,11 @@ opp-50000000 {
};
};
pmu {
compatible = "arm,cortex-a55-pmu";
interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
};
psci {
compatible = "arm,psci-1.0", "arm,psci-0.2";
method = "smc";
@@ -175,9 +180,8 @@ ssi0: ssi@10049c00 {
reg = <0 0x10049c00 0 0x400>;
interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 327 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 328 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 329 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
<GIC_SPI 328 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "int_req", "dma_rx", "dma_tx";
clocks = <&cpg CPG_MOD R9A07G054_SSI0_PCLK2>,
<&cpg CPG_MOD R9A07G054_SSI0_PCLK_SFR>,
<&audio_clk1>, <&audio_clk2>;
@@ -196,9 +200,8 @@ ssi1: ssi@1004a000 {
reg = <0 0x1004a000 0 0x400>;
interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 331 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 332 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 333 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
<GIC_SPI 332 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "int_req", "dma_rx", "dma_tx";
clocks = <&cpg CPG_MOD R9A07G054_SSI1_PCLK2>,
<&cpg CPG_MOD R9A07G054_SSI1_PCLK_SFR>,
<&audio_clk1>, <&audio_clk2>;
@@ -216,10 +219,8 @@ ssi2: ssi@1004a400 {
"renesas,rz-ssi";
reg = <0 0x1004a400 0 0x400>;
interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 335 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 336 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 337 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
interrupt-names = "int_req", "dma_rt";
clocks = <&cpg CPG_MOD R9A07G054_SSI2_PCLK2>,
<&cpg CPG_MOD R9A07G054_SSI2_PCLK_SFR>,
<&audio_clk1>, <&audio_clk2>;
@@ -238,9 +239,8 @@ ssi3: ssi@1004a800 {
reg = <0 0x1004a800 0 0x400>;
interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 339 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 340 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 341 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
<GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "int_req", "dma_rx", "dma_tx";
clocks = <&cpg CPG_MOD R9A07G054_SSI3_PCLK2>,
<&cpg CPG_MOD R9A07G054_SSI3_PCLK_SFR>,
<&audio_clk1>, <&audio_clk2>;
@@ -1067,9 +1067,9 @@ target: trip-point {
timer {
compatible = "arm,armv8-timer";
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
};
};

7
arch/arm64/boot/dts/renesas/r9a07g054l1.dtsi
View File

@@ -15,11 +15,4 @@ cpus {
/delete-node/ cpu-map;
/delete-node/ cpu@100;
};
timer {
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
};
};

218
arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts
View File

@@ -7,6 +7,7 @@
/dts-v1/;
#include "r9a09g011.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/rzv2m-pinctrl.h>
/ {
@@ -22,6 +23,31 @@ chosen {
stdout-path = "serial0:115200n8";
};
connector {
compatible = "usb-c-connector";
label = "USB-C";
data-role = "dual";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
hs_ep: endpoint {
remote-endpoint = <&usb3_hs_ep>;
};
};
port@1 {
reg = <1>;
ss_ep: endpoint {
remote-endpoint = <&hd3ss3220_in_ep>;
};
};
};
};
memory@58000000 {
device_type = "memory";
/*
@@ -35,6 +61,36 @@ memory@180000000 {
device_type = "memory";
reg = <0x1 0x80000000 0x0 0x80000000>;
};
reg_1v8: regulator-1v8 {
compatible = "regulator-fixed";
regulator-name = "fixed-1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
reg_3v3: regulator-3v3 {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
vccq_sdhi0: regulator-vccq-sdhi0 {
compatible = "regulator-gpio";
regulator-name = "SDHI0 VccQ";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
gpios = <&pwc 0 GPIO_ACTIVE_HIGH>;
gpios-states = <1>;
states = <3300000 0>, <1800000 1>;
};
};
&avb {
@@ -50,6 +106,23 @@ phy0: ethernet-phy@0 {
};
};
&emmc {
pinctrl-0 = <&emmc_pins>;
pinctrl-1 = <&emmc_pins>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&reg_3v3>;
vqmmc-supply = <&reg_1v8>;
bus-width = <8>;
mmc-hs200-1_8v;
no-sd;
no-sdio;
non-removable;
fixed-emmc-driver-type = <1>;
max-frequency = <200000000>;
status = "okay";
};
&extal_clk {
clock-frequency = <48000000>;
};
@@ -59,6 +132,30 @@ &i2c0 {
pinctrl-names = "default";
clock-frequency = <400000>;
status = "okay";
hd3ss3220@47 {
compatible = "ti,hd3ss3220";
reg = <0x47>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
hd3ss3220_in_ep: endpoint {
remote-endpoint = <&ss_ep>;
};
};
port@1 {
reg = <1>;
hd3ss3220_out_ep: endpoint {
remote-endpoint = <&usb3_role_switch>;
};
};
};
};
};
&i2c2 {
@@ -69,6 +166,26 @@ &i2c2 {
};
&pinctrl {
emmc_pins: emmc {
data {
pinmux = <RZV2M_PORT_PINMUX(0, 0, 2)>, /* MMDAT0 */
<RZV2M_PORT_PINMUX(0, 1, 2)>, /* MMDAT1 */
<RZV2M_PORT_PINMUX(0, 2, 2)>, /* MMDAT2 */
<RZV2M_PORT_PINMUX(0, 3, 2)>, /* MMDAT3 */
<RZV2M_PORT_PINMUX(0, 4, 2)>, /* MMDAT4 */
<RZV2M_PORT_PINMUX(0, 5, 2)>, /* MMDAT5 */
<RZV2M_PORT_PINMUX(0, 6, 2)>, /* MMDAT6 */
<RZV2M_PORT_PINMUX(0, 7, 2)>; /* MMDAT7 */
power-source = <1800>;
};
ctrl {
pinmux = <RZV2M_PORT_PINMUX(0, 10, 2)>, /* MMCMD */
<RZV2M_PORT_PINMUX(0, 11, 2)>; /* MMCLK */
power-source = <1800>;
};
};
i2c0_pins: i2c0 {
pinmux = <RZV2M_PORT_PINMUX(5, 0, 2)>, /* SDA */
<RZV2M_PORT_PINMUX(5, 1, 2)>; /* SCL */
@@ -78,6 +195,55 @@ i2c2_pins: i2c2 {
pinmux = <RZV2M_PORT_PINMUX(3, 8, 2)>, /* SDA */
<RZV2M_PORT_PINMUX(3, 9, 2)>; /* SCL */
};
sdhi0_pins: sd0 {
data {
pinmux = <RZV2M_PORT_PINMUX(8, 2, 1)>, /* SD0DAT0 */
<RZV2M_PORT_PINMUX(8, 3, 1)>, /* SD0DAT1 */
<RZV2M_PORT_PINMUX(8, 4, 1)>, /* SD0DAT2 */
<RZV2M_PORT_PINMUX(8, 5, 1)>; /* SD0DAT3 */
power-source = <3300>;
};
ctrl {
pinmux = <RZV2M_PORT_PINMUX(8, 0, 1)>, /* SD0CMD */
<RZV2M_PORT_PINMUX(8, 1, 1)>; /* SD0CLK */
power-source = <3300>;
};
cd {
pinmux = <RZV2M_PORT_PINMUX(8, 7, 1)>; /* SD0CD */
power-source = <3300>;
};
};
sdhi0_pins_uhs: sd0-uhs {
data {
pinmux = <RZV2M_PORT_PINMUX(8, 2, 1)>, /* SD0DAT0 */
<RZV2M_PORT_PINMUX(8, 3, 1)>, /* SD0DAT1 */
<RZV2M_PORT_PINMUX(8, 4, 1)>, /* SD0DAT2 */
<RZV2M_PORT_PINMUX(8, 5, 1)>; /* SD0DAT3 */
power-source = <1800>;
};
ctrl {
pinmux = <RZV2M_PORT_PINMUX(8, 0, 1)>, /* SD0CMD */
<RZV2M_PORT_PINMUX(8, 1, 1)>; /* SD0CLK */
power-source = <1800>;
};
cd {
pinmux = <RZV2M_PORT_PINMUX(8, 7, 1)>; /* SD0CD */
power-source = <1800>;
};
};
uart0_pins: uart0 {
pinmux = <RZV2M_PORT_PINMUX(3, 0, 2)>, /* UATX0 */
<RZV2M_PORT_PINMUX(3, 1, 2)>, /* UARX0 */
<RZV2M_PORT_PINMUX(3, 2, 2)>, /* UACTS0N */
<RZV2M_PORT_PINMUX(3, 3, 2)>; /* UARTS0N */
};
};
&pwc {
@@ -85,10 +251,60 @@ &pwc {
status = "okay";
};
&uart0 {
&sdhi0 {
pinctrl-0 = <&sdhi0_pins>;
pinctrl-1 = <&sdhi0_pins_uhs>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&reg_3v3>;
vqmmc-supply = <&vccq_sdhi0>;
bus-width = <4>;
sd-uhs-sdr50;
sd-uhs-sdr104;
status = "okay";
};
&uart0 {
pinctrl-0 = <&uart0_pins>;
pinctrl-names = "default";
uart-has-rtscts;
status = "okay";
};
&usb3drd {
status = "okay";
};
&usb3host {
status = "okay";
};
&usb3peri {
companion = <&usb3host>;
status = "okay";
usb-role-switch;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
usb3_hs_ep: endpoint {
remote-endpoint = <&hs_ep>;
};
};
port@1 {
reg = <1>;
usb3_role_switch: endpoint {
remote-endpoint = <&hd3ss3220_out_ep>;
};
};
};
};
&wdt0 {
status = "okay";
};

45
arch/arm64/boot/dts/renesas/r9a09g011.dtsi
View File

@@ -117,6 +117,51 @@ emmc: mmc@85020000 {
status = "disabled";
};
usb3drd: usb3drd@85070400 {
compatible = "renesas,r9a09g011-usb3drd",
"renesas,rzv2m-usb3drd";
reg = <0x0 0x85070400 0x0 0x100>;
interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "drd", "bc", "gpi";
clocks = <&cpg CPG_MOD R9A09G011_USB_ACLK_P>,
<&cpg CPG_MOD R9A09G011_USB_PCLK>;
clock-names = "axi", "reg";
resets = <&cpg R9A09G011_USB_DRD_RESET>;
power-domains = <&cpg>;
ranges;
#address-cells = <2>;
#size-cells = <2>;
status = "disabled";
usb3host: usb@85060000 {
compatible = "renesas,r9a09g011-xhci",
"renesas,rzv2m-xhci";
reg = <0 0x85060000 0 0x2000>;
interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD R9A09G011_USB_ACLK_H>,
<&cpg CPG_MOD R9A09G011_USB_PCLK>;
clock-names = "axi", "reg";
resets = <&cpg R9A09G011_USB_ARESETN_H>;
power-domains = <&cpg>;
status = "disabled";
};
usb3peri: usb3peri@85070000 {
compatible = "renesas,r9a09g011-usb3-peri",
"renesas,rzv2m-usb3-peri";
reg = <0x0 0x85070000 0x0 0x400>;
interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD R9A09G011_USB_ACLK_P>,
<&cpg CPG_MOD R9A09G011_USB_PCLK>;
clock-names = "axi", "reg";
resets = <&cpg R9A09G011_USB_ARESETN_P>;
power-domains = <&cpg>;
status = "disabled";
};
};
avb: ethernet@a3300000 {
compatible = "renesas,etheravb-r9a09g011","renesas,etheravb-rzv2m";
reg = <0 0xa3300000 0 0x800>;

6
arch/arm64/boot/dts/renesas/ulcb.dtsi
View File

@@ -267,6 +267,12 @@ dvfs: dvfs {
};
};
};
eeprom@50 {
compatible = "rohm,br24t01", "atmel,24c01";
reg = <0x50>;
pagesize = <8>;
};
};
&ohci1 {