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drm/amdgpu/gfx11: add CU mask support for compute MQD initialization

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Extend the GFX11 compute MQD initialization to support
Compute Unit (CU) masking for fine-grained resource allocation.
This allows compute queues to be limited to specific CUs for
performance isolation and debugging purposes.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Jesse Zhang <jesse.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Jesse.Zhang
2026-01-23 13:00:13 +08:00
committed by Alex Deucher
parent 0ea556047d
commit d68c4e48e4
1 changed files with 33 additions and 0 deletions
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33
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
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@@ -4238,6 +4238,37 @@ static int gfx_v11_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev)
return gfx_v11_0_cp_gfx_start(adev);
}
static void gfx_v11_0_compute_mqd_set_cu_mask(struct amdgpu_device *adev,
struct v11_compute_mqd *mqd,
struct amdgpu_mqd_prop *prop)
{
uint32_t se_mask[8] = {0};
uint32_t wa_mask;
bool has_wa_flag = prop->cu_flags & (AMDGPU_UPDATE_FLAG_DBG_WA_ENABLE |
AMDGPU_UPDATE_FLAG_DBG_WA_DISABLE);
if (!has_wa_flag && (!prop->cu_mask || !prop->cu_mask_count))
return;
if (has_wa_flag) {
wa_mask = (prop->cu_flags & AMDGPU_UPDATE_FLAG_DBG_WA_ENABLE) ?
0xffff : 0xffffffff;
mqd->compute_static_thread_mgmt_se0 = wa_mask;
mqd->compute_static_thread_mgmt_se1 = wa_mask;
mqd->compute_static_thread_mgmt_se2 = wa_mask;
mqd->compute_static_thread_mgmt_se3 = wa_mask;
return;
}
amdgpu_gfx_mqd_symmetrically_map_cu_mask(adev, prop->cu_mask,
prop->cu_mask_count, se_mask);
mqd->compute_static_thread_mgmt_se0 = se_mask[0];
mqd->compute_static_thread_mgmt_se1 = se_mask[1];
mqd->compute_static_thread_mgmt_se2 = se_mask[2];
mqd->compute_static_thread_mgmt_se3 = se_mask[3];
}
static int gfx_v11_0_compute_mqd_init(struct amdgpu_device *adev, void *m,
struct amdgpu_mqd_prop *prop)
{
@@ -4372,6 +4403,8 @@ static int gfx_v11_0_compute_mqd_init(struct amdgpu_device *adev, void *m,
/* set UQ fenceaddress */
mqd->fence_address_lo = lower_32_bits(prop->fence_address);
mqd->fence_address_hi = upper_32_bits(prop->fence_address);
/* set CU mask */
gfx_v11_0_compute_mqd_set_cu_mask(adev, mqd, prop);
return 0;
}