mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2026-05-05 14:40:12 -04:00
Merge tag 'tegra-for-6.6-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/dt
arm64: tegra: Device tree changes for v6.6-rc1
The majority of this is fixes all over the place for DT schema
validation warnings. However, there are also cleanups for some things in
DT and audio support is added on IGX Orin. Jetson Orin NX and Nano also
gain a new thermal trip point to help keep the device cool at moderate
loads.
* tag 'tegra-for-6.6-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: (22 commits)
arm64: tegra: Add blank lines for better readability
arm64: tegra: Remove {clock,reset}-names from VIC powergate
arm64: tegra: Drop incorrect maxim,disable-etr on Smaug
arm64: tegra: Add SPI device tree nodes for Tegra234
arm64: tegra: Enable UARTA and UARTE for Orin Nano
arm64: tegra: Add UARTE device tree node on Tegra234
arm64: tegra: Adapt to LP855X bindings changes
arm64: tegra: Add PCIe and DP 3.3V supplies
arm64: tegra: Add missing reset-names for Tegra HS UART
arm64: tegra: Remove current-speed for SBSA UART
arm64: tegra: smaug: Remove reg-shift for high-speed UART
arm64: tegra: Remove dmas and dma-names for debug UART
arm64: tegra: Add 35°C trip point for Jetson Orin NX/Nano
arm64: tegra: Remove duplicate PCI nodes
arm64: tegra: Sort PCI nodes correctly on Orin
arm64: tegra: Add audio support for IGX Orin
arm64: tegra: Update CPU OPP tables
arm64: tegra: Fix HSUART for Smaug
arm64: tegra: Fix HSUART for Jetson AGX Orin
arm64: tegra: Add missing alias for NVIDIA IGX Orin
...
Link: https://lore.kernel.org/r/20230728094129.3587109-4-thierry.reding@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
@@ -531,6 +531,8 @@ soc_warm_reset_l {
|
||||
};
|
||||
|
||||
serial@70006000 {
|
||||
/delete-property/ dmas;
|
||||
/delete-property/ dma-names;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
||||
@@ -135,7 +135,8 @@ tegra_ahub: ahub@2900800 {
|
||||
clocks = <&bpmp TEGRA186_CLK_AHUB>;
|
||||
clock-names = "ahub";
|
||||
assigned-clocks = <&bpmp TEGRA186_CLK_AHUB>;
|
||||
assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
|
||||
assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>;
|
||||
assigned-clock-rates = <81600000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x02900800 0x02900800 0x11800>;
|
||||
|
||||
@@ -231,7 +231,8 @@ tegra_ahub: ahub@2900800 {
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||||
clocks = <&bpmp TEGRA194_CLK_AHUB>;
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clock-names = "ahub";
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assigned-clocks = <&bpmp TEGRA194_CLK_AHUB>;
|
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assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
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assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLP_OUT0>;
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assigned-clock-rates = <81600000>;
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status = "disabled";
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||||
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||||
#address-cells = <2>;
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||||
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||||
@@ -28,6 +28,8 @@ gpu@57000000 {
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||||
|
||||
/* debug port */
|
||||
serial@70006000 {
|
||||
/delete-property/ dmas;
|
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/delete-property/ dma-names;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
||||
@@ -58,19 +58,17 @@ backlight: backlight@2c {
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||||
dev-ctrl = /bits/ 8 <0x80>;
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init-brt = /bits/ 8 <0xff>;
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||||
|
||||
pwm-period = <29334>;
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||||
|
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pwms = <&pwm 0 29334>;
|
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pwm-names = "lp8557";
|
||||
|
||||
/* boost frequency 1 MHz */
|
||||
rom_13h {
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rom-13h {
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rom-addr = /bits/ 8 <0x13>;
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rom-val = /bits/ 8 <0x01>;
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};
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||||
|
||||
/* 3 LED string */
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rom_14h {
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rom-14h {
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rom-addr = /bits/ 8 <0x14>;
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rom-val = /bits/ 8 <0x87>;
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};
|
||||
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@@ -21,6 +21,8 @@ memory@80000000 {
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||||
|
||||
/* debug port */
|
||||
serial@70006000 {
|
||||
/delete-property/ dmas;
|
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/delete-property/ dma-names;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
||||
@@ -1321,6 +1321,8 @@ shutdown {
|
||||
};
|
||||
|
||||
serial@70006000 {
|
||||
/delete-property/ dmas;
|
||||
/delete-property/ dma-names;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
||||
@@ -126,6 +126,8 @@ dvfs_pwm_pbb1 {
|
||||
|
||||
/* debug port */
|
||||
serial@70006000 {
|
||||
/delete-property/ dmas;
|
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/delete-property/ dma-names;
|
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status = "okay";
|
||||
};
|
||||
|
||||
|
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@@ -1312,11 +1312,15 @@ shutdown {
|
||||
};
|
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|
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serial@70006000 {
|
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/delete-property/ dmas;
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/delete-property/ dma-names;
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status = "okay";
|
||||
};
|
||||
|
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uartd: serial@70006300 {
|
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compatible = "nvidia,tegra30-hsuart";
|
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reset-names = "serial";
|
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/delete-property/ reg-shift;
|
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status = "okay";
|
||||
|
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bluetooth {
|
||||
@@ -1391,7 +1395,6 @@ max77621_gpu: regulator@1c {
|
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maxim,dvs-default-state = <1>;
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maxim,enable-active-discharge;
|
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maxim,enable-bias-control;
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maxim,disable-etr;
|
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maxim,enable-gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
|
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maxim,externally-enable;
|
||||
};
|
||||
|
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@@ -916,9 +916,7 @@ pd_venc: venc {
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|
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pd_vic: vic {
|
||||
clocks = <&tegra_car TEGRA210_CLK_VIC03>;
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clock-names = "vic";
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resets = <&tegra_car 178>;
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reset-names = "vic";
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#power-domain-cells = <0>;
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};
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@@ -1386,7 +1384,8 @@ tegra_ahub: ahub@702d0800 {
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clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>;
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clock-names = "ahub";
|
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assigned-clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>;
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assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
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assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>;
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assigned-clock-rates = <81600000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x702d0000 0x702d0000 0x0000e400>;
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@@ -1,6 +1,7 @@
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||||
// SPDX-License-Identifier: GPL-2.0
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|
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#include "tegra234.dtsi"
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#include "tegra234-p3701.dtsi"
|
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|
||||
/ {
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model = "NVIDIA Jetson AGX Orin";
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|
||||
@@ -1,6 +1,7 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
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#include "tegra234.dtsi"
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#include "tegra234-p3701.dtsi"
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/ {
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compatible = "nvidia,p3701-0008", "nvidia,tegra234";
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1991
arch/arm64/boot/dts/nvidia/tegra234-p3701.dtsi
Normal file
1991
arch/arm64/boot/dts/nvidia/tegra234-p3701.dtsi
Normal file
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,9 +1,26 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
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||||
|
||||
#include <dt-bindings/sound/rt5640.h>
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|
||||
/ {
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compatible = "nvidia,p3737-0000";
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bus@0 {
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aconnect@2900000 {
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ahub@2900800 {
|
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i2s@2901000 {
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ports {
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port@1 {
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endpoint {
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dai-format = "i2s";
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remote-endpoint = <&rt5640_ep>;
|
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};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
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i2c@3160000 {
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status = "okay";
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@@ -20,6 +37,30 @@ eeprom@56 {
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||||
};
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};
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i2c@31e0000 {
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status = "okay";
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audio-codec@1c {
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compatible = "realtek,rt5640";
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reg = <0x1c>;
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interrupt-parent = <&gpio>;
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interrupts = <TEGRA234_MAIN_GPIO(AC, 5) GPIO_ACTIVE_HIGH>;
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clocks = <&bpmp TEGRA234_CLK_AUD_MCLK>;
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clock-names = "mclk";
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realtek,dmic1-data-pin = <RT5640_DMIC1_DATA_PIN_NONE>;
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realtek,dmic2-data-pin = <RT5640_DMIC2_DATA_PIN_NONE>;
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realtek,jack-detect-source = <RT5640_JD_SRC_HDA_HEADER>;
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sound-name-prefix = "CVB-RT";
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port {
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rt5640_ep: endpoint {
|
||||
remote-endpoint = <&i2s1_dap>;
|
||||
mclk-fs = <256>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pwm@3280000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
@@ -12,6 +12,7 @@ / {
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||||
|
||||
aliases {
|
||||
serial0 = &tcu;
|
||||
serial1 = &uarta;
|
||||
};
|
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||||
chosen {
|
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@@ -19,57 +20,9 @@ chosen {
|
||||
};
|
||||
|
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bus@0 {
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||||
host1x@13e00000 {
|
||||
nvdec@15480000 {
|
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status = "okay";
|
||||
};
|
||||
};
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pcie@140e0000 {
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status = "okay";
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vddio-pex-ctl-supply = <&vdd_1v8_ls>;
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phys = <&p2u_gbe_4>, <&p2u_gbe_5>;
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phy-names = "p2u-0", "p2u-1";
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};
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pcie@14100000 {
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status = "okay";
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vddio-pex-ctl-supply = <&vdd_1v8_ao>;
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phys = <&p2u_hsio_3>;
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phy-names = "p2u-0";
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};
|
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pcie@14160000 {
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status = "okay";
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vddio-pex-ctl-supply = <&vdd_1v8_ao>;
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phys = <&p2u_hsio_7>, <&p2u_hsio_6>, <&p2u_hsio_5>,
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<&p2u_hsio_4>;
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phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3";
|
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};
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pcie@141a0000 {
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status = "okay";
|
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vddio-pex-ctl-supply = <&vdd_1v8_ls>;
|
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phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>,
|
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<&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>,
|
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<&p2u_nvhs_6>, <&p2u_nvhs_7>;
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phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4",
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"p2u-5", "p2u-6", "p2u-7";
|
||||
};
|
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|
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pcie@141e0000 {
|
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status = "okay";
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vddio-pex-ctl-supply = <&vdd_1v8_ls>;
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phys = <&p2u_gbe_0>, <&p2u_gbe_1>;
|
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phy-names = "p2u-0", "p2u-1";
|
||||
};
|
||||
|
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aconnect@2900000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
serial@3100000 {
|
||||
compatible = "nvidia,tegra194-hsuart";
|
||||
reset-names = "serial";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
@@ -103,7 +56,7 @@ spi@3270000 {
|
||||
};
|
||||
|
||||
hda@3510000 {
|
||||
nvidia,model = "NVIDIA IGX HDA";
|
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nvidia,model = "NVIDIA IGX Orin HDA";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
@@ -118,6 +71,52 @@ i2c@c240000 {
|
||||
i2c@c250000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
host1x@13e00000 {
|
||||
nvdec@15480000 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
pcie@140e0000 {
|
||||
status = "okay";
|
||||
vddio-pex-ctl-supply = <&vdd_1v8_ls>;
|
||||
phys = <&p2u_gbe_4>, <&p2u_gbe_5>;
|
||||
phy-names = "p2u-0", "p2u-1";
|
||||
};
|
||||
|
||||
pcie@14100000 {
|
||||
status = "okay";
|
||||
vddio-pex-ctl-supply = <&vdd_1v8_ao>;
|
||||
vpcie3v3-supply = <&vdd_3v3_wifi>;
|
||||
phys = <&p2u_hsio_3>;
|
||||
phy-names = "p2u-0";
|
||||
};
|
||||
|
||||
pcie@14160000 {
|
||||
status = "okay";
|
||||
vddio-pex-ctl-supply = <&vdd_1v8_ao>;
|
||||
phys = <&p2u_hsio_7>, <&p2u_hsio_6>, <&p2u_hsio_5>,
|
||||
<&p2u_hsio_4>;
|
||||
phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3";
|
||||
};
|
||||
|
||||
pcie@141a0000 {
|
||||
status = "okay";
|
||||
vddio-pex-ctl-supply = <&vdd_1v8_ls>;
|
||||
phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>,
|
||||
<&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>,
|
||||
<&p2u_nvhs_6>, <&p2u_nvhs_7>;
|
||||
phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4",
|
||||
"p2u-5", "p2u-6", "p2u-7";
|
||||
};
|
||||
|
||||
pcie@141e0000 {
|
||||
status = "okay";
|
||||
vddio-pex-ctl-supply = <&vdd_1v8_ls>;
|
||||
phys = <&p2u_gbe_0>, <&p2u_gbe_1>;
|
||||
phy-names = "p2u-0", "p2u-1";
|
||||
};
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
@@ -151,4 +150,89 @@ key-suspend {
|
||||
serial {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
sound {
|
||||
status = "okay";
|
||||
|
||||
compatible = "nvidia,tegra186-audio-graph-card";
|
||||
|
||||
dais = /* ADMAIF (FE) Ports */
|
||||
<&admaif0_port>, <&admaif1_port>, <&admaif2_port>, <&admaif3_port>,
|
||||
<&admaif4_port>, <&admaif5_port>, <&admaif6_port>, <&admaif7_port>,
|
||||
<&admaif8_port>, <&admaif9_port>, <&admaif10_port>, <&admaif11_port>,
|
||||
<&admaif12_port>, <&admaif13_port>, <&admaif14_port>, <&admaif15_port>,
|
||||
<&admaif16_port>, <&admaif17_port>, <&admaif18_port>, <&admaif19_port>,
|
||||
/* XBAR Ports */
|
||||
<&xbar_i2s1_port>, <&xbar_i2s2_port>, <&xbar_i2s4_port>,
|
||||
<&xbar_i2s6_port>, <&xbar_dmic3_port>,
|
||||
<&xbar_sfc1_in_port>, <&xbar_sfc2_in_port>,
|
||||
<&xbar_sfc3_in_port>, <&xbar_sfc4_in_port>,
|
||||
<&xbar_mvc1_in_port>, <&xbar_mvc2_in_port>,
|
||||
<&xbar_amx1_in1_port>, <&xbar_amx1_in2_port>,
|
||||
<&xbar_amx1_in3_port>, <&xbar_amx1_in4_port>,
|
||||
<&xbar_amx2_in1_port>, <&xbar_amx2_in2_port>,
|
||||
<&xbar_amx2_in3_port>, <&xbar_amx2_in4_port>,
|
||||
<&xbar_amx3_in1_port>, <&xbar_amx3_in2_port>,
|
||||
<&xbar_amx3_in3_port>, <&xbar_amx3_in4_port>,
|
||||
<&xbar_amx4_in1_port>, <&xbar_amx4_in2_port>,
|
||||
<&xbar_amx4_in3_port>, <&xbar_amx4_in4_port>,
|
||||
<&xbar_adx1_in_port>, <&xbar_adx2_in_port>,
|
||||
<&xbar_adx3_in_port>, <&xbar_adx4_in_port>,
|
||||
<&xbar_mix_in1_port>, <&xbar_mix_in2_port>,
|
||||
<&xbar_mix_in3_port>, <&xbar_mix_in4_port>,
|
||||
<&xbar_mix_in5_port>, <&xbar_mix_in6_port>,
|
||||
<&xbar_mix_in7_port>, <&xbar_mix_in8_port>,
|
||||
<&xbar_mix_in9_port>, <&xbar_mix_in10_port>,
|
||||
<&xbar_asrc_in1_port>, <&xbar_asrc_in2_port>,
|
||||
<&xbar_asrc_in3_port>, <&xbar_asrc_in4_port>,
|
||||
<&xbar_asrc_in5_port>, <&xbar_asrc_in6_port>,
|
||||
<&xbar_asrc_in7_port>,
|
||||
<&xbar_ope1_in_port>,
|
||||
/* HW accelerators */
|
||||
<&sfc1_out_port>, <&sfc2_out_port>,
|
||||
<&sfc3_out_port>, <&sfc4_out_port>,
|
||||
<&mvc1_out_port>, <&mvc2_out_port>,
|
||||
<&amx1_out_port>, <&amx2_out_port>,
|
||||
<&amx3_out_port>, <&amx4_out_port>,
|
||||
<&adx1_out1_port>, <&adx1_out2_port>,
|
||||
<&adx1_out3_port>, <&adx1_out4_port>,
|
||||
<&adx2_out1_port>, <&adx2_out2_port>,
|
||||
<&adx2_out3_port>, <&adx2_out4_port>,
|
||||
<&adx3_out1_port>, <&adx3_out2_port>,
|
||||
<&adx3_out3_port>, <&adx3_out4_port>,
|
||||
<&adx4_out1_port>, <&adx4_out2_port>,
|
||||
<&adx4_out3_port>, <&adx4_out4_port>,
|
||||
<&mix_out1_port>, <&mix_out2_port>, <&mix_out3_port>,
|
||||
<&mix_out4_port>, <&mix_out5_port>,
|
||||
<&asrc_out1_port>, <&asrc_out2_port>, <&asrc_out3_port>,
|
||||
<&asrc_out4_port>, <&asrc_out5_port>, <&asrc_out6_port>,
|
||||
<&ope1_out_port>,
|
||||
/* BE I/O Ports */
|
||||
<&i2s1_port>, <&i2s2_port>, <&i2s4_port>, <&i2s6_port>,
|
||||
<&dmic3_port>;
|
||||
|
||||
label = "NVIDIA IGX Orin APE";
|
||||
|
||||
widgets = "Microphone", "CVB-RT MIC Jack",
|
||||
"Microphone", "CVB-RT MIC",
|
||||
"Headphone", "CVB-RT HP Jack",
|
||||
"Speaker", "CVB-RT SPK";
|
||||
|
||||
routing = /* I2S4 <-> RT5640 */
|
||||
"CVB-RT AIF1 Playback", "I2S4 DAP-Playback",
|
||||
"I2S4 DAP-Capture", "CVB-RT AIF1 Capture",
|
||||
/* RT5640 codec controls */
|
||||
"CVB-RT HP Jack", "CVB-RT HPOL",
|
||||
"CVB-RT HP Jack", "CVB-RT HPOR",
|
||||
"CVB-RT IN1P", "CVB-RT MIC Jack",
|
||||
"CVB-RT IN2P", "CVB-RT MIC Jack",
|
||||
"CVB-RT IN2N", "CVB-RT MIC Jack",
|
||||
"CVB-RT IN3P", "CVB-RT MIC Jack",
|
||||
"CVB-RT SPK", "CVB-RT SPOLP",
|
||||
"CVB-RT SPK", "CVB-RT SPORP",
|
||||
"CVB-RT SPK", "CVB-RT LOUTL",
|
||||
"CVB-RT SPK", "CVB-RT LOUTR",
|
||||
"CVB-RT DMIC1", "CVB-RT MIC",
|
||||
"CVB-RT DMIC2", "CVB-RT MIC";
|
||||
};
|
||||
};
|
||||
|
||||
@@ -1,10 +1,60 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
|
||||
#include <dt-bindings/sound/rt5640.h>
|
||||
|
||||
/ {
|
||||
compatible = "nvidia,p3740-0002";
|
||||
|
||||
bus@0 {
|
||||
aconnect@2900000 {
|
||||
ahub@2900800 {
|
||||
i2s@2901300 {
|
||||
ports {
|
||||
port@1 {
|
||||
endpoint {
|
||||
dai-format = "i2s";
|
||||
remote-endpoint = <&rt5640_ep>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
i2s@2901500 {
|
||||
ports {
|
||||
port@1 {
|
||||
endpoint {
|
||||
bitclock-master;
|
||||
frame-master;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
i2c@31c0000 {
|
||||
rt5640: audio-codec@1c {
|
||||
compatible = "realtek,rt5640";
|
||||
reg = <0x1c>;
|
||||
interrupt-parent = <&gpio>;
|
||||
interrupts = <TEGRA234_MAIN_GPIO(F, 3) GPIO_ACTIVE_HIGH>;
|
||||
clocks = <&bpmp TEGRA234_CLK_AUD_MCLK>;
|
||||
clock-names = "mclk";
|
||||
|
||||
realtek,dmic1-data-pin = <RT5640_DMIC1_DATA_PIN_NONE>;
|
||||
realtek,dmic2-data-pin = <RT5640_DMIC2_DATA_PIN_NONE>;
|
||||
realtek,jack-detect-source = <RT5640_JD_SRC_HDA_HEADER>;
|
||||
|
||||
sound-name-prefix = "CVB-RT";
|
||||
|
||||
port {
|
||||
rt5640_ep: endpoint {
|
||||
remote-endpoint = <&i2s4_dap>;
|
||||
mclk-fs = <256>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* carrier board ID EEPROM */
|
||||
eeprom@55 {
|
||||
compatible = "atmel,24c02";
|
||||
@@ -134,4 +184,32 @@ usb@3610000 {
|
||||
"usb3-0", "usb3-1", "usb3-2";
|
||||
};
|
||||
};
|
||||
|
||||
vdd_3v3_dp: regulator-vdd-3v3-dp {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "VDD_3V3_DP";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&vdd_3v3_sys>;
|
||||
gpio = <&gpio TEGRA234_MAIN_GPIO(H, 6) 0>;
|
||||
enable-active-high;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vdd_3v3_sys: regulator-vdd-3v3-sys {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "VDD_3V3_SYS";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
vdd_3v3_wifi: regulator-vdd-3v3-wifi {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "VDD_3V3_WIFI";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
gpio = <&gpio TEGRA234_MAIN_GPIO(G, 3) GPIO_ACTIVE_HIGH>;
|
||||
regulator-boot-on;
|
||||
enable-active-high;
|
||||
};
|
||||
};
|
||||
|
||||
@@ -106,12 +106,18 @@ tj-thermal {
|
||||
|
||||
trips {
|
||||
tj_trip_active0: active-0 {
|
||||
temperature = <74000>;
|
||||
temperature = <35000>;
|
||||
hysteresis = <4000>;
|
||||
type = "active";
|
||||
};
|
||||
|
||||
tj_trip_active1: active-1 {
|
||||
temperature = <74000>;
|
||||
hysteresis = <4000>;
|
||||
type = "active";
|
||||
};
|
||||
|
||||
tj_trip_active2: active-2 {
|
||||
temperature = <95000>;
|
||||
hysteresis = <4000>;
|
||||
type = "active";
|
||||
|
||||
@@ -13,6 +13,8 @@ / {
|
||||
|
||||
aliases {
|
||||
serial0 = &tcu;
|
||||
serial1 = &uarta;
|
||||
serial2 = &uarte;
|
||||
};
|
||||
|
||||
chosen {
|
||||
@@ -20,8 +22,19 @@ chosen {
|
||||
};
|
||||
|
||||
bus@0 {
|
||||
serial@3100000 {
|
||||
compatible = "nvidia,tegra194-hsuart";
|
||||
reset-names = "serial";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
serial@3140000 {
|
||||
compatible = "nvidia,tegra194-hsuart";
|
||||
reset-names = "serial";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
serial@31d0000 {
|
||||
current-speed = <115200>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
@@ -39,50 +52,6 @@ hda@3510000 {
|
||||
padctl@3520000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* C1 - M.2 Key-E */
|
||||
pcie@14100000 {
|
||||
status = "okay";
|
||||
|
||||
vddio-pex-ctl-supply = <&vdd_1v8_ao>;
|
||||
|
||||
phys = <&p2u_hsio_3>;
|
||||
phy-names = "p2u-0";
|
||||
};
|
||||
|
||||
/* C4 - M.2 Key-M */
|
||||
pcie@14160000 {
|
||||
status = "okay";
|
||||
|
||||
vddio-pex-ctl-supply = <&vdd_1v8_ao>;
|
||||
|
||||
phys = <&p2u_hsio_4>, <&p2u_hsio_5>, <&p2u_hsio_6>,
|
||||
<&p2u_hsio_7>;
|
||||
phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3";
|
||||
};
|
||||
|
||||
/* C8 - Ethernet */
|
||||
pcie@140a0000 {
|
||||
status = "okay";
|
||||
|
||||
num-lanes = <2>;
|
||||
|
||||
phys = <&p2u_gbe_2>, <&p2u_gbe_3>;
|
||||
phy-names = "p2u-0", "p2u-1";
|
||||
|
||||
vddio-pex-ctl-supply = <&vdd_1v8_ao>;
|
||||
vpcie3v3-supply = <&vdd_3v3_pcie>;
|
||||
};
|
||||
|
||||
/* C7 - M.2 Key-M */
|
||||
pcie@141e0000 {
|
||||
status = "okay";
|
||||
|
||||
vddio-pex-ctl-supply = <&vdd_1v8_ao>;
|
||||
|
||||
phys = <&p2u_gbe_0>, <&p2u_gbe_1>;
|
||||
phy-names = "p2u-0", "p2u-1";
|
||||
};
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
@@ -113,7 +82,7 @@ key-suspend {
|
||||
};
|
||||
|
||||
pwm-fan {
|
||||
cooling-levels = <0 187 255>;
|
||||
cooling-levels = <0 88 187 255>;
|
||||
};
|
||||
|
||||
vdd_3v3_pcie: regulator-vdd-3v3-pcie {
|
||||
@@ -141,6 +110,11 @@ map-active-1 {
|
||||
cooling-device = <&fan 1 2>;
|
||||
trip = <&tj_trip_active1>;
|
||||
};
|
||||
|
||||
map-active-2 {
|
||||
cooling-device = <&fan 2 3>;
|
||||
trip = <&tj_trip_active2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@@ -12,7 +12,7 @@ / {
|
||||
model = "NVIDIA Jetson Orin Nano Developer Kit";
|
||||
|
||||
pwm-fan {
|
||||
cooling-levels = <0 187 255>;
|
||||
cooling-levels = <0 88 187 255>;
|
||||
};
|
||||
|
||||
thermal-zones {
|
||||
@@ -27,6 +27,11 @@ map-active-1 {
|
||||
cooling-device = <&fan 1 2>;
|
||||
trip = <&tj_trip_active1>;
|
||||
};
|
||||
|
||||
map-active-2 {
|
||||
cooling-device = <&fan 2 3>;
|
||||
trip = <&tj_trip_active2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@@ -29,7 +29,6 @@ eeprom@57 {
|
||||
};
|
||||
|
||||
serial@31d0000 {
|
||||
current-speed = <115200>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
@@ -134,6 +133,19 @@ usb@3610000 {
|
||||
"usb3-1";
|
||||
};
|
||||
|
||||
/* C8 - Ethernet */
|
||||
pcie@140a0000 {
|
||||
status = "okay";
|
||||
|
||||
num-lanes = <2>;
|
||||
|
||||
phys = <&p2u_gbe_2>, <&p2u_gbe_3>;
|
||||
phy-names = "p2u-0", "p2u-1";
|
||||
|
||||
vddio-pex-ctl-supply = <&vdd_1v8_ao>;
|
||||
vpcie3v3-supply = <&vdd_3v3_pcie>;
|
||||
};
|
||||
|
||||
/* C1 - M.2 Key-E */
|
||||
pcie@14100000 {
|
||||
status = "okay";
|
||||
@@ -155,19 +167,6 @@ pcie@14160000 {
|
||||
phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3";
|
||||
};
|
||||
|
||||
/* C8 - Ethernet */
|
||||
pcie@140a0000 {
|
||||
status = "okay";
|
||||
|
||||
num-lanes = <2>;
|
||||
|
||||
phys = <&p2u_gbe_2>, <&p2u_gbe_3>;
|
||||
phy-names = "p2u-0", "p2u-1";
|
||||
|
||||
vddio-pex-ctl-supply = <&vdd_1v8_ao>;
|
||||
vpcie3v3-supply = <&vdd_3v3_pcie>;
|
||||
};
|
||||
|
||||
/* C7 - M.2 Key-M */
|
||||
pcie@141e0000 {
|
||||
status = "okay";
|
||||
|
||||
@@ -19,6 +19,8 @@ chosen {
|
||||
|
||||
bus@0 {
|
||||
serial@3100000 {
|
||||
/delete-property/ dmas;
|
||||
/delete-property/ dma-names;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
||||
@@ -180,7 +180,8 @@ tegra_ahub: ahub@2900800 {
|
||||
clocks = <&bpmp TEGRA234_CLK_AHUB>;
|
||||
clock-names = "ahub";
|
||||
assigned-clocks = <&bpmp TEGRA234_CLK_AHUB>;
|
||||
assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
|
||||
assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
|
||||
assigned-clock-rates = <81600000>;
|
||||
status = "disabled";
|
||||
|
||||
#address-cells = <2>;
|
||||
@@ -687,6 +688,15 @@ uarta: serial@3100000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uarte: serial@3140000 {
|
||||
compatible = "nvidia,tegra234-uart", "nvidia,tegra20-uart";
|
||||
reg = <0x0 0x03140000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&bpmp TEGRA234_CLK_UARTE>;
|
||||
resets = <&bpmp TEGRA234_RESET_UARTE>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gen1_i2c: i2c@3160000 {
|
||||
compatible = "nvidia,tegra194-i2c";
|
||||
reg = <0x0 0x3160000 0x0 0x100>;
|
||||
@@ -808,6 +818,44 @@ dp_aux_ch3_i2c: i2c@31e0000 {
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
|
||||
spi@3210000 {
|
||||
compatible = "nvidia,tegra210-spi";
|
||||
reg = <0x0 0x03210000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&bpmp TEGRA234_CLK_SPI1>;
|
||||
assigned-clocks = <&bpmp TEGRA234_CLK_SPI1>;
|
||||
assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
|
||||
clock-names = "spi";
|
||||
iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>;
|
||||
resets = <&bpmp TEGRA234_RESET_SPI1>;
|
||||
reset-names = "spi";
|
||||
dmas = <&gpcdma 15>, <&gpcdma 15>;
|
||||
dma-names = "rx", "tx";
|
||||
dma-coherent;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi@3230000 {
|
||||
compatible = "nvidia,tegra210-spi";
|
||||
reg = <0x0 0x03230000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&bpmp TEGRA234_CLK_SPI3>;
|
||||
clock-names = "spi";
|
||||
iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>;
|
||||
assigned-clocks = <&bpmp TEGRA234_CLK_SPI3>;
|
||||
assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
|
||||
resets = <&bpmp TEGRA234_RESET_SPI3>;
|
||||
reset-names = "spi";
|
||||
dmas = <&gpcdma 17>, <&gpcdma 17>;
|
||||
dma-names = "rx", "tx";
|
||||
dma-coherent;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi@3270000 {
|
||||
compatible = "nvidia,tegra234-qspi";
|
||||
reg = <0x0 0x3270000 0x0 0x1000>;
|
||||
@@ -1733,6 +1781,25 @@ gen8_i2c: i2c@c250000 {
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
|
||||
spi@c260000 {
|
||||
compatible = "nvidia,tegra210-spi";
|
||||
reg = <0x0 0x0c260000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&bpmp TEGRA234_CLK_SPI2>;
|
||||
clock-names = "spi";
|
||||
iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>;
|
||||
assigned-clocks = <&bpmp TEGRA234_CLK_SPI2>;
|
||||
assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
|
||||
resets = <&bpmp TEGRA234_RESET_SPI2>;
|
||||
reset-names = "spi";
|
||||
dmas = <&gpcdma 19>, <&gpcdma 19>;
|
||||
dma-names = "rx", "tx";
|
||||
dma-coherent;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
rtc@c2a0000 {
|
||||
compatible = "nvidia,tegra234-rtc", "nvidia,tegra20-rtc";
|
||||
reg = <0x0 0x0c2a0000 0x0 0x10000>;
|
||||
@@ -3589,72 +3656,142 @@ cl0_ch1_opp1: opp-115200000 {
|
||||
opp-peak-kBps = <816000>;
|
||||
};
|
||||
|
||||
cl0_ch1_opp2: opp-268800000 {
|
||||
cl0_ch1_opp2: opp-192000000 {
|
||||
opp-hz = /bits/ 64 <192000000>;
|
||||
opp-peak-kBps = <816000>;
|
||||
};
|
||||
|
||||
cl0_ch1_opp3: opp-268800000 {
|
||||
opp-hz = /bits/ 64 <268800000>;
|
||||
opp-peak-kBps = <816000>;
|
||||
};
|
||||
|
||||
cl0_ch1_opp3: opp-422400000 {
|
||||
cl0_ch1_opp4: opp-345600000 {
|
||||
opp-hz = /bits/ 64 <345600000>;
|
||||
opp-peak-kBps = <816000>;
|
||||
};
|
||||
|
||||
cl0_ch1_opp5: opp-422400000 {
|
||||
opp-hz = /bits/ 64 <422400000>;
|
||||
opp-peak-kBps = <816000>;
|
||||
};
|
||||
|
||||
cl0_ch1_opp4: opp-576000000 {
|
||||
cl0_ch1_opp6: opp-499200000 {
|
||||
opp-hz = /bits/ 64 <499200000>;
|
||||
opp-peak-kBps = <816000>;
|
||||
};
|
||||
|
||||
cl0_ch1_opp7: opp-576000000 {
|
||||
opp-hz = /bits/ 64 <576000000>;
|
||||
opp-peak-kBps = <816000>;
|
||||
};
|
||||
|
||||
cl0_ch1_opp5: opp-729600000 {
|
||||
cl0_ch1_opp8: opp-652800000 {
|
||||
opp-hz = /bits/ 64 <652800000>;
|
||||
opp-peak-kBps = <816000>;
|
||||
};
|
||||
|
||||
cl0_ch1_opp9: opp-729600000 {
|
||||
opp-hz = /bits/ 64 <729600000>;
|
||||
opp-peak-kBps = <816000>;
|
||||
};
|
||||
|
||||
cl0_ch1_opp6: opp-883200000 {
|
||||
cl0_ch1_opp10: opp-806400000 {
|
||||
opp-hz = /bits/ 64 <806400000>;
|
||||
opp-peak-kBps = <816000>;
|
||||
};
|
||||
|
||||
cl0_ch1_opp11: opp-883200000 {
|
||||
opp-hz = /bits/ 64 <883200000>;
|
||||
opp-peak-kBps = <816000>;
|
||||
};
|
||||
|
||||
cl0_ch1_opp7: opp-1036800000 {
|
||||
cl0_ch1_opp12: opp-960000000 {
|
||||
opp-hz = /bits/ 64 <960000000>;
|
||||
opp-peak-kBps = <816000>;
|
||||
};
|
||||
|
||||
cl0_ch1_opp13: opp-1036800000 {
|
||||
opp-hz = /bits/ 64 <1036800000>;
|
||||
opp-peak-kBps = <816000>;
|
||||
};
|
||||
|
||||
cl0_ch1_opp8: opp-1190400000 {
|
||||
opp-hz = /bits/ 64 <1190400000>;
|
||||
opp-peak-kBps = <816000>;
|
||||
cl0_ch1_opp14: opp-1113600000 {
|
||||
opp-hz = /bits/ 64 <1113600000>;
|
||||
opp-peak-kBps = <1632000>;
|
||||
};
|
||||
|
||||
cl0_ch1_opp9: opp-1344000000 {
|
||||
cl0_ch1_opp15: opp-1190400000 {
|
||||
opp-hz = /bits/ 64 <1190400000>;
|
||||
opp-peak-kBps = <1632000>;
|
||||
};
|
||||
|
||||
cl0_ch1_opp16: opp-1267200000 {
|
||||
opp-hz = /bits/ 64 <1267200000>;
|
||||
opp-peak-kBps = <1632000>;
|
||||
};
|
||||
|
||||
cl0_ch1_opp17: opp-1344000000 {
|
||||
opp-hz = /bits/ 64 <1344000000>;
|
||||
opp-peak-kBps = <1632000>;
|
||||
};
|
||||
|
||||
cl0_ch1_opp10: opp-1497600000 {
|
||||
opp-hz = /bits/ 64 <1497600000>;
|
||||
cl0_ch1_opp18: opp-1420800000 {
|
||||
opp-hz = /bits/ 64 <1420800000>;
|
||||
opp-peak-kBps = <1632000>;
|
||||
};
|
||||
|
||||
cl0_ch1_opp11: opp-1651200000 {
|
||||
cl0_ch1_opp19: opp-1497600000 {
|
||||
opp-hz = /bits/ 64 <1497600000>;
|
||||
opp-peak-kBps = <3200000>;
|
||||
};
|
||||
|
||||
cl0_ch1_opp20: opp-1574400000 {
|
||||
opp-hz = /bits/ 64 <1574400000>;
|
||||
opp-peak-kBps = <3200000>;
|
||||
};
|
||||
|
||||
cl0_ch1_opp21: opp-1651200000 {
|
||||
opp-hz = /bits/ 64 <1651200000>;
|
||||
opp-peak-kBps = <2660000>;
|
||||
opp-peak-kBps = <3200000>;
|
||||
};
|
||||
|
||||
cl0_ch1_opp12: opp-1804800000 {
|
||||
cl0_ch1_opp22: opp-1728000000 {
|
||||
opp-hz = /bits/ 64 <1728000000>;
|
||||
opp-peak-kBps = <3200000>;
|
||||
};
|
||||
|
||||
cl0_ch1_opp23: opp-1804800000 {
|
||||
opp-hz = /bits/ 64 <1804800000>;
|
||||
opp-peak-kBps = <2660000>;
|
||||
opp-peak-kBps = <3200000>;
|
||||
};
|
||||
|
||||
cl0_ch1_opp13: opp-1958400000 {
|
||||
cl0_ch1_opp24: opp-1881600000 {
|
||||
opp-hz = /bits/ 64 <1881600000>;
|
||||
opp-peak-kBps = <3200000>;
|
||||
};
|
||||
|
||||
cl0_ch1_opp25: opp-1958400000 {
|
||||
opp-hz = /bits/ 64 <1958400000>;
|
||||
opp-peak-kBps = <3200000>;
|
||||
};
|
||||
|
||||
cl0_ch1_opp14: opp-2112000000 {
|
||||
cl0_ch1_opp26: opp-2035200000 {
|
||||
opp-hz = /bits/ 64 <2035200000>;
|
||||
opp-peak-kBps = <3200000>;
|
||||
};
|
||||
|
||||
cl0_ch1_opp27: opp-2112000000 {
|
||||
opp-hz = /bits/ 64 <2112000000>;
|
||||
opp-peak-kBps = <6400000>;
|
||||
};
|
||||
|
||||
cl0_ch1_opp15: opp-2201600000 {
|
||||
cl0_ch1_opp28: opp-2188800000 {
|
||||
opp-hz = /bits/ 64 <2188800000>;
|
||||
opp-peak-kBps = <6400000>;
|
||||
};
|
||||
|
||||
cl0_ch1_opp29: opp-2201600000 {
|
||||
opp-hz = /bits/ 64 <2201600000>;
|
||||
opp-peak-kBps = <6400000>;
|
||||
};
|
||||
@@ -3669,72 +3806,142 @@ cl1_ch1_opp1: opp-115200000 {
|
||||
opp-peak-kBps = <816000>;
|
||||
};
|
||||
|
||||
cl1_ch1_opp2: opp-268800000 {
|
||||
cl1_ch1_opp2: opp-192000000 {
|
||||
opp-hz = /bits/ 64 <192000000>;
|
||||
opp-peak-kBps = <816000>;
|
||||
};
|
||||
|
||||
cl1_ch1_opp3: opp-268800000 {
|
||||
opp-hz = /bits/ 64 <268800000>;
|
||||
opp-peak-kBps = <816000>;
|
||||
};
|
||||
|
||||
cl1_ch1_opp3: opp-422400000 {
|
||||
cl1_ch1_opp4: opp-345600000 {
|
||||
opp-hz = /bits/ 64 <345600000>;
|
||||
opp-peak-kBps = <816000>;
|
||||
};
|
||||
|
||||
cl1_ch1_opp5: opp-422400000 {
|
||||
opp-hz = /bits/ 64 <422400000>;
|
||||
opp-peak-kBps = <816000>;
|
||||
};
|
||||
|
||||
cl1_ch1_opp4: opp-576000000 {
|
||||
cl1_ch1_opp6: opp-499200000 {
|
||||
opp-hz = /bits/ 64 <499200000>;
|
||||
opp-peak-kBps = <816000>;
|
||||
};
|
||||
|
||||
cl1_ch1_opp7: opp-576000000 {
|
||||
opp-hz = /bits/ 64 <576000000>;
|
||||
opp-peak-kBps = <816000>;
|
||||
};
|
||||
|
||||
cl1_ch1_opp5: opp-729600000 {
|
||||
cl1_ch1_opp8: opp-652800000 {
|
||||
opp-hz = /bits/ 64 <652800000>;
|
||||
opp-peak-kBps = <816000>;
|
||||
};
|
||||
|
||||
cl1_ch1_opp9: opp-729600000 {
|
||||
opp-hz = /bits/ 64 <729600000>;
|
||||
opp-peak-kBps = <816000>;
|
||||
};
|
||||
|
||||
cl1_ch1_opp6: opp-883200000 {
|
||||
cl1_ch1_opp10: opp-806400000 {
|
||||
opp-hz = /bits/ 64 <806400000>;
|
||||
opp-peak-kBps = <816000>;
|
||||
};
|
||||
|
||||
cl1_ch1_opp11: opp-883200000 {
|
||||
opp-hz = /bits/ 64 <883200000>;
|
||||
opp-peak-kBps = <816000>;
|
||||
};
|
||||
|
||||
cl1_ch1_opp7: opp-1036800000 {
|
||||
cl1_ch1_opp12: opp-960000000 {
|
||||
opp-hz = /bits/ 64 <960000000>;
|
||||
opp-peak-kBps = <816000>;
|
||||
};
|
||||
|
||||
cl1_ch1_opp13: opp-1036800000 {
|
||||
opp-hz = /bits/ 64 <1036800000>;
|
||||
opp-peak-kBps = <816000>;
|
||||
};
|
||||
|
||||
cl1_ch1_opp8: opp-1190400000 {
|
||||
opp-hz = /bits/ 64 <1190400000>;
|
||||
opp-peak-kBps = <816000>;
|
||||
cl1_ch1_opp14: opp-1113600000 {
|
||||
opp-hz = /bits/ 64 <1113600000>;
|
||||
opp-peak-kBps = <1632000>;
|
||||
};
|
||||
|
||||
cl1_ch1_opp9: opp-1344000000 {
|
||||
cl1_ch1_opp15: opp-1190400000 {
|
||||
opp-hz = /bits/ 64 <1190400000>;
|
||||
opp-peak-kBps = <1632000>;
|
||||
};
|
||||
|
||||
cl1_ch1_opp16: opp-1267200000 {
|
||||
opp-hz = /bits/ 64 <1267200000>;
|
||||
opp-peak-kBps = <1632000>;
|
||||
};
|
||||
|
||||
cl1_ch1_opp17: opp-1344000000 {
|
||||
opp-hz = /bits/ 64 <1344000000>;
|
||||
opp-peak-kBps = <1632000>;
|
||||
};
|
||||
|
||||
cl1_ch1_opp10: opp-1497600000 {
|
||||
opp-hz = /bits/ 64 <1497600000>;
|
||||
cl1_ch1_opp18: opp-1420800000 {
|
||||
opp-hz = /bits/ 64 <1420800000>;
|
||||
opp-peak-kBps = <1632000>;
|
||||
};
|
||||
|
||||
cl1_ch1_opp11: opp-1651200000 {
|
||||
cl1_ch1_opp19: opp-1497600000 {
|
||||
opp-hz = /bits/ 64 <1497600000>;
|
||||
opp-peak-kBps = <3200000>;
|
||||
};
|
||||
|
||||
cl1_ch1_opp20: opp-1574400000 {
|
||||
opp-hz = /bits/ 64 <1574400000>;
|
||||
opp-peak-kBps = <3200000>;
|
||||
};
|
||||
|
||||
cl1_ch1_opp21: opp-1651200000 {
|
||||
opp-hz = /bits/ 64 <1651200000>;
|
||||
opp-peak-kBps = <2660000>;
|
||||
opp-peak-kBps = <3200000>;
|
||||
};
|
||||
|
||||
cl1_ch1_opp12: opp-1804800000 {
|
||||
cl1_ch1_opp22: opp-1728000000 {
|
||||
opp-hz = /bits/ 64 <1728000000>;
|
||||
opp-peak-kBps = <3200000>;
|
||||
};
|
||||
|
||||
cl1_ch1_opp23: opp-1804800000 {
|
||||
opp-hz = /bits/ 64 <1804800000>;
|
||||
opp-peak-kBps = <2660000>;
|
||||
opp-peak-kBps = <3200000>;
|
||||
};
|
||||
|
||||
cl1_ch1_opp13: opp-1958400000 {
|
||||
cl1_ch1_opp24: opp-1881600000 {
|
||||
opp-hz = /bits/ 64 <1881600000>;
|
||||
opp-peak-kBps = <3200000>;
|
||||
};
|
||||
|
||||
cl1_ch1_opp25: opp-1958400000 {
|
||||
opp-hz = /bits/ 64 <1958400000>;
|
||||
opp-peak-kBps = <3200000>;
|
||||
};
|
||||
|
||||
cl1_ch1_opp14: opp-2112000000 {
|
||||
cl1_ch1_opp26: opp-2035200000 {
|
||||
opp-hz = /bits/ 64 <2035200000>;
|
||||
opp-peak-kBps = <3200000>;
|
||||
};
|
||||
|
||||
cl1_ch1_opp27: opp-2112000000 {
|
||||
opp-hz = /bits/ 64 <2112000000>;
|
||||
opp-peak-kBps = <6400000>;
|
||||
};
|
||||
|
||||
cl1_ch1_opp15: opp-2201600000 {
|
||||
cl1_ch1_opp28: opp-2188800000 {
|
||||
opp-hz = /bits/ 64 <2188800000>;
|
||||
opp-peak-kBps = <6400000>;
|
||||
};
|
||||
|
||||
cl1_ch1_opp29: opp-2201600000 {
|
||||
opp-hz = /bits/ 64 <2201600000>;
|
||||
opp-peak-kBps = <6400000>;
|
||||
};
|
||||
@@ -3749,72 +3956,142 @@ cl2_ch1_opp1: opp-115200000 {
|
||||
opp-peak-kBps = <816000>;
|
||||
};
|
||||
|
||||
cl2_ch1_opp2: opp-268800000 {
|
||||
cl2_ch1_opp2: opp-192000000 {
|
||||
opp-hz = /bits/ 64 <192000000>;
|
||||
opp-peak-kBps = <816000>;
|
||||
};
|
||||
|
||||
cl2_ch1_opp3: opp-268800000 {
|
||||
opp-hz = /bits/ 64 <268800000>;
|
||||
opp-peak-kBps = <816000>;
|
||||
};
|
||||
|
||||
cl2_ch1_opp3: opp-422400000 {
|
||||
cl2_ch1_opp4: opp-345600000 {
|
||||
opp-hz = /bits/ 64 <345600000>;
|
||||
opp-peak-kBps = <816000>;
|
||||
};
|
||||
|
||||
cl2_ch1_opp5: opp-422400000 {
|
||||
opp-hz = /bits/ 64 <422400000>;
|
||||
opp-peak-kBps = <816000>;
|
||||
};
|
||||
|
||||
cl2_ch1_opp4: opp-576000000 {
|
||||
cl2_ch1_opp6: opp-499200000 {
|
||||
opp-hz = /bits/ 64 <499200000>;
|
||||
opp-peak-kBps = <816000>;
|
||||
};
|
||||
|
||||
cl2_ch1_opp7: opp-576000000 {
|
||||
opp-hz = /bits/ 64 <576000000>;
|
||||
opp-peak-kBps = <816000>;
|
||||
};
|
||||
|
||||
cl2_ch1_opp5: opp-729600000 {
|
||||
cl2_ch1_opp8: opp-652800000 {
|
||||
opp-hz = /bits/ 64 <652800000>;
|
||||
opp-peak-kBps = <816000>;
|
||||
};
|
||||
|
||||
cl2_ch1_opp9: opp-729600000 {
|
||||
opp-hz = /bits/ 64 <729600000>;
|
||||
opp-peak-kBps = <816000>;
|
||||
};
|
||||
|
||||
cl2_ch1_opp6: opp-883200000 {
|
||||
cl2_ch1_opp10: opp-806400000 {
|
||||
opp-hz = /bits/ 64 <806400000>;
|
||||
opp-peak-kBps = <816000>;
|
||||
};
|
||||
|
||||
cl2_ch1_opp11: opp-883200000 {
|
||||
opp-hz = /bits/ 64 <883200000>;
|
||||
opp-peak-kBps = <816000>;
|
||||
};
|
||||
|
||||
cl2_ch1_opp7: opp-1036800000 {
|
||||
cl2_ch1_opp12: opp-960000000 {
|
||||
opp-hz = /bits/ 64 <960000000>;
|
||||
opp-peak-kBps = <816000>;
|
||||
};
|
||||
|
||||
cl2_ch1_opp13: opp-1036800000 {
|
||||
opp-hz = /bits/ 64 <1036800000>;
|
||||
opp-peak-kBps = <816000>;
|
||||
};
|
||||
|
||||
cl2_ch1_opp8: opp-1190400000 {
|
||||
opp-hz = /bits/ 64 <1190400000>;
|
||||
opp-peak-kBps = <816000>;
|
||||
cl2_ch1_opp14: opp-1113600000 {
|
||||
opp-hz = /bits/ 64 <1113600000>;
|
||||
opp-peak-kBps = <1632000>;
|
||||
};
|
||||
|
||||
cl2_ch1_opp9: opp-1344000000 {
|
||||
cl2_ch1_opp15: opp-1190400000 {
|
||||
opp-hz = /bits/ 64 <1190400000>;
|
||||
opp-peak-kBps = <1632000>;
|
||||
};
|
||||
|
||||
cl2_ch1_opp16: opp-1267200000 {
|
||||
opp-hz = /bits/ 64 <1267200000>;
|
||||
opp-peak-kBps = <1632000>;
|
||||
};
|
||||
|
||||
cl2_ch1_opp17: opp-1344000000 {
|
||||
opp-hz = /bits/ 64 <1344000000>;
|
||||
opp-peak-kBps = <1632000>;
|
||||
};
|
||||
|
||||
cl2_ch1_opp10: opp-1497600000 {
|
||||
opp-hz = /bits/ 64 <1497600000>;
|
||||
cl2_ch1_opp18: opp-1420800000 {
|
||||
opp-hz = /bits/ 64 <1420800000>;
|
||||
opp-peak-kBps = <1632000>;
|
||||
};
|
||||
|
||||
cl2_ch1_opp11: opp-1651200000 {
|
||||
cl2_ch1_opp19: opp-1497600000 {
|
||||
opp-hz = /bits/ 64 <1497600000>;
|
||||
opp-peak-kBps = <3200000>;
|
||||
};
|
||||
|
||||
cl2_ch1_opp20: opp-1574400000 {
|
||||
opp-hz = /bits/ 64 <1574400000>;
|
||||
opp-peak-kBps = <3200000>;
|
||||
};
|
||||
|
||||
cl2_ch1_opp21: opp-1651200000 {
|
||||
opp-hz = /bits/ 64 <1651200000>;
|
||||
opp-peak-kBps = <2660000>;
|
||||
opp-peak-kBps = <3200000>;
|
||||
};
|
||||
|
||||
cl2_ch1_opp12: opp-1804800000 {
|
||||
cl2_ch1_opp22: opp-1728000000 {
|
||||
opp-hz = /bits/ 64 <1728000000>;
|
||||
opp-peak-kBps = <3200000>;
|
||||
};
|
||||
|
||||
cl2_ch1_opp23: opp-1804800000 {
|
||||
opp-hz = /bits/ 64 <1804800000>;
|
||||
opp-peak-kBps = <2660000>;
|
||||
opp-peak-kBps = <3200000>;
|
||||
};
|
||||
|
||||
cl2_ch1_opp13: opp-1958400000 {
|
||||
cl2_ch1_opp24: opp-1881600000 {
|
||||
opp-hz = /bits/ 64 <1881600000>;
|
||||
opp-peak-kBps = <3200000>;
|
||||
};
|
||||
|
||||
cl2_ch1_opp25: opp-1958400000 {
|
||||
opp-hz = /bits/ 64 <1958400000>;
|
||||
opp-peak-kBps = <3200000>;
|
||||
};
|
||||
|
||||
cl2_ch1_opp14: opp-2112000000 {
|
||||
cl2_ch1_opp26: opp-2035200000 {
|
||||
opp-hz = /bits/ 64 <2035200000>;
|
||||
opp-peak-kBps = <3200000>;
|
||||
};
|
||||
|
||||
cl2_ch1_opp27: opp-2112000000 {
|
||||
opp-hz = /bits/ 64 <2112000000>;
|
||||
opp-peak-kBps = <6400000>;
|
||||
};
|
||||
|
||||
cl2_ch1_opp15: opp-2201600000 {
|
||||
cl2_ch1_opp28: opp-2188800000 {
|
||||
opp-hz = /bits/ 64 <2188800000>;
|
||||
opp-peak-kBps = <6400000>;
|
||||
};
|
||||
|
||||
cl2_ch1_opp29: opp-2201600000 {
|
||||
opp-hz = /bits/ 64 <2201600000>;
|
||||
opp-peak-kBps = <6400000>;
|
||||
};
|
||||
|
||||
Reference in New Issue
Block a user