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dt-bindings: riscv: Add xsfvfwmaccqqq ISA extension description

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Add "xsfvfwmaccqqq" ISA extension which is provided by SiFive for
matrix multiply accumulate instructions support.

Signed-off-by: Cyan Yang <cyan.yang@sifive.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20250418053239.4351-10-cyan.yang@sifive.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
This commit is contained in:
Cyan Yang
2025-04-18 13:32:36 +08:00
committed by Palmer Dabbelt
parent 1d91224394
commit d5ca02b25f
1 changed files with 6 additions and 0 deletions
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6
Documentation/devicetree/bindings/riscv/extensions.yaml
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@@ -681,6 +681,12 @@ properties:
See more details in
https://www.sifive.com/document-file/fp32-to-int8-ranged-clip-instructions
- const: xsfvfwmaccqqq
description:
SiFive Matrix Multiply Accumulate Instruction Extensions Specification.
See more details in
https://www.sifive.com/document-file/matrix-multiply-accumulate-instruction
# T-HEAD
- const: xtheadvector
description: