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Merge branch 'for-7.1/core-v2' into for-linus

Browse Source 
- fixed handling of 0-sized reports (Dmitry Torokhov)
- convert core code to __free() (Dmitry Torokhov)
- support for multiple batteries per HID device (Lucas Zampieri)
This commit is contained in:
Jiri Kosina
2026-04-16 21:01:18 +02:00
parent 8b9a097eb2 69c02ffde6
commit d4eb7b2da6
10831 changed files with 138506 additions and 65533 deletions
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16
.mailmap
View File

@@ -210,10 +210,16 @@ Daniel Borkmann <daniel@iogearbox.net> <daniel.borkmann@tik.ee.ethz.ch>
Daniel Borkmann <daniel@iogearbox.net> <dborkmann@redhat.com>
Daniel Borkmann <daniel@iogearbox.net> <dborkman@redhat.com>
Daniel Borkmann <daniel@iogearbox.net> <dxchgb@gmail.com>
Daniel Lezcano <daniel.lezcano@kernel.org> <daniel.lezcano@linaro.org>
Daniel Lezcano <daniel.lezcano@kernel.org> <daniel.lezcano@free.fr>
Daniel Lezcano <daniel.lezcano@kernel.org> <daniel.lezcano@linexp.org>
Daniel Lezcano <daniel.lezcano@kernel.org> <dlezcano@fr.ibm.com>
Daniel Thompson <danielt@kernel.org> <daniel.thompson@linaro.org>
Daniele Alessandrelli <daniele.alessandrelli@gmail.com> <daniele.alessandrelli@intel.com>
Danilo Krummrich <dakr@kernel.org> <dakr@redhat.com>
David Brownell <david-b@pacbell.net>
David Collins <quic_collinsd@quicinc.com> <collinsd@codeaurora.org>
David Gow <david@davidgow.net> <davidgow@google.com>
David Heidelberg <david@ixit.cz> <d.okias@gmail.com>
David Hildenbrand <david@kernel.org> <david@redhat.com>
David Rheinsberg <david@readahead.eu> <dh.herrmann@gmail.com>
@@ -321,6 +327,7 @@ Henrik Rydberg <rydberg@bitmath.org>
Herbert Xu <herbert@gondor.apana.org.au>
Huacai Chen <chenhuacai@kernel.org> <chenhc@lemote.com>
Huacai Chen <chenhuacai@kernel.org> <chenhuacai@loongson.cn>
Ignat Korchagin <ignat@linux.win> <ignat@cloudflare.com>
Ike Panhc <ikepanhc@gmail.com> <ike.pan@canonical.com>
J. Bruce Fields <bfields@fieldses.org> <bfields@redhat.com>
J. Bruce Fields <bfields@fieldses.org> <bfields@citi.umich.edu>
@@ -348,6 +355,7 @@ Jarkko Sakkinen <jarkko@kernel.org> <jarkko.sakkinen@opinsys.com>
Jason Gunthorpe <jgg@ziepe.ca> <jgg@mellanox.com>
Jason Gunthorpe <jgg@ziepe.ca> <jgg@nvidia.com>
Jason Gunthorpe <jgg@ziepe.ca> <jgunthorpe@obsidianresearch.com>
Jason Xing <kerneljasonxing@gmail.com> <kernelxing@tencent.com>
<javier@osg.samsung.com> <javier.martinez@collabora.co.uk>
Javi Merino <javi.merino@kernel.org> <javi.merino@arm.com>
Jayachandran C <c.jayachandran@gmail.com> <jayachandranc@netlogicmicro.com>
@@ -396,6 +404,7 @@ Jiri Slaby <jirislaby@kernel.org> <xslaby@fi.muni.cz>
Jisheng Zhang <jszhang@kernel.org> <jszhang@marvell.com>
Jisheng Zhang <jszhang@kernel.org> <Jisheng.Zhang@synaptics.com>
Jishnu Prakash <quic_jprakash@quicinc.com> <jprakash@codeaurora.org>
Joe Damato <joe@dama.to> <jdamato@fastly.com>
Joel Granados <joel.granados@kernel.org> <j.granados@samsung.com>
Johan Hovold <johan@kernel.org> <jhovold@gmail.com>
Johan Hovold <johan@kernel.org> <johan@hovoldconsulting.com>
@@ -490,7 +499,8 @@ Lior David <quic_liord@quicinc.com> <liord@codeaurora.org>
Loic Poulain <loic.poulain@oss.qualcomm.com> <loic.poulain@linaro.org>
Loic Poulain <loic.poulain@oss.qualcomm.com> <loic.poulain@intel.com>
Lorenzo Pieralisi <lpieralisi@kernel.org> <lorenzo.pieralisi@arm.com>
Lorenzo Stoakes <lorenzo.stoakes@oracle.com> <lstoakes@gmail.com>
Lorenzo Stoakes <ljs@kernel.org> <lstoakes@gmail.com>
Lorenzo Stoakes <ljs@kernel.org> <lorenzo.stoakes@oracle.com>
Luca Ceresoli <luca.ceresoli@bootlin.com> <luca@lucaceresoli.net>
Luca Weiss <luca@lucaweiss.eu> <luca@z3ntu.xyz>
Lucas De Marchi <demarchi@kernel.org> <lucas.demarchi@intel.com>
@@ -876,6 +886,7 @@ Vivien Didelot <vivien.didelot@gmail.com> <vivien.didelot@savoirfairelinux.com>
Vlad Dogaru <ddvlad@gmail.com> <vlad.dogaru@intel.com>
Vladimir Davydov <vdavydov.dev@gmail.com> <vdavydov@parallels.com>
Vladimir Davydov <vdavydov.dev@gmail.com> <vdavydov@virtuozzo.com>
Vlastimil Babka <vbabka@kernel.org> <vbabka@suse.cz>
WangYuli <wangyuli@aosc.io> <wangyl5933@chinaunicom.cn>
WangYuli <wangyuli@aosc.io> <wangyuli@deepin.org>
Weiwen Hu <huweiwen@linux.alibaba.com> <sehuww@mail.scut.edu.cn>
@@ -890,7 +901,8 @@ Yanteng Si <si.yanteng@linux.dev> <siyanteng@loongson.cn>
Ying Huang <huang.ying.caritas@gmail.com> <ying.huang@intel.com>
Yixun Lan <dlan@kernel.org> <dlan@gentoo.org>
Yixun Lan <dlan@kernel.org> <yixun.lan@amlogic.com>
Yosry Ahmed <yosry.ahmed@linux.dev> <yosryahmed@google.com>
Yosry Ahmed <yosry@kernel.org> <yosryahmed@google.com>
Yosry Ahmed <yosry@kernel.org> <yosry.ahmed@linux.dev>
Yu-Chun Lin <eleanor.lin@realtek.com> <eleanor15x@gmail.com>
Yusuke Goda <goda.yusuke@renesas.com>
Zack Rusin <zack.rusin@broadcom.com> <zackr@vmware.com>

11
CREDITS
View File

@@ -1242,6 +1242,10 @@ N: Veaceslav Falico
E: vfalico@gmail.com
D: Co-maintainer and co-author of the network bonding driver.
N: Thomas Falcon
E: tlfalcon@linux.ibm.com
D: Initial author of the IBM ibmvnic network driver
N: János Farkas
E: chexum@shadow.banki.hu
D: romfs, various (mostly networking) fixes
@@ -2415,6 +2419,10 @@ S: Am Muehlenweg 38
S: D53424 Remagen
S: Germany
N: Jonathan Lemon
E: jonathan.lemon@gmail.com
D: OpenCompute PTP clock driver (ptp_ocp)
N: Colin Leroy
E: colin@colino.net
W: http://www.geekounet.org/
@@ -3492,7 +3500,8 @@ S: Brazil
N: Stephen Rothwell
E: sfr@canb.auug.org.au
W: http://www.canb.auug.org.au/~sfr
P: 1024/BD8C7805 CD A4 9D 01 10 6E 7E 3B 91 88 FA D9 C8 40 AA 02
P: 4096R/5AD24211C060D1C8 D41C A3ED 5B30 275C F5A0 1B05 5AD2 4211 C060 D1C8
D: Created linux-next and maintained it 2008-2026
D: Boot/setup/build work for setup > 2K
D: Author, APM driver
D: Directory notification

15
Documentation/ABI/stable/sysfs-driver-dma-idxd
View File

@@ -136,6 +136,21 @@ Description: The last executed device administrative command's status/error.
Also last configuration error overloaded.
Writing to it will clear the status.
What: /sys/bus/dsa/devices/dsa<m>/dsacaps
Date: April 5, 2026
KernelVersion: 6.20.0
Contact: dmaengine@vger.kernel.org
Description: The DSA3 specification introduces three new capability
registers: dsacap[0-2]. User components (e.g., configuration
libraries and workload applications) require this information
to properly utilize the DSA3 features.
This includes SGL capability support, Enabling hardware-specific
optimizations, Configuring memory, etc.
The output format is '<dsacap2>,<dsacap1>,<dsacap0>' where each
DSA cap value is a 64 bit hex value.
This attribute should only be visible on DSA devices of version
3 or later.
What: /sys/bus/dsa/devices/dsa<m>/iaa_cap
Date: Sept 14, 2022
KernelVersion: 6.0.0

3
Documentation/ABI/stable/sysfs-driver-speakup
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@@ -23,8 +23,7 @@ What: /sys/accessibility/speakup/bleep_time
KernelVersion: 2.6
Contact: speakup@linux-speakup.org
Description: This controls the duration of the PC speaker beeps speakup
produces.
TODO: What are the units? Jiffies?
produces, in milliseconds.
What: /sys/accessibility/speakup/cursor_time
KernelVersion: 2.6

16
Documentation/ABI/testing/configfs-tsm-report
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@@ -17,6 +17,12 @@ Description:
where the implementation is conveyed via the @provider
attribute.
This interface fails reads and sets errno to EFBIG when the
report generated by @provider exceeds the configfs-tsm-report
internal maximums. Contact the platform provider for the
compatible security module, driver, and attestation library
combination.
What: /sys/kernel/config/tsm/report/$name/auxblob
Date: October, 2023
KernelVersion: v6.7
@@ -31,6 +37,9 @@ Description:
Standardization v2.03 Section 4.1.8.1 MSG_REPORT_REQ.
https://www.amd.com/content/dam/amd/en/documents/epyc-technical-docs/specifications/56421.pdf
See "EFBIG" comment in the @outblob description for potential
error conditions.
What: /sys/kernel/config/tsm/report/$name/manifestblob
Date: January, 2024
KernelVersion: v6.10
@@ -43,6 +52,9 @@ Description:
See 'service_provider' for information on the format of the
manifest blob.
See "EFBIG" comment in the @outblob description for potential
error conditions.
What: /sys/kernel/config/tsm/report/$name/provider
Date: September, 2023
KernelVersion: v6.7
@@ -61,6 +73,10 @@ Description:
Library Revision 0.8 Appendix 4,5
https://download.01.org/intel-sgx/latest/dcap-latest/linux/docs/Intel_TDX_DCAP_Quoting_Library_API.pdf
Intel TDX platforms with DICE-based attestation use CBOR Web Token
(CWT) format for the Quote payload. This is indicated by the Quote
size exceeding 8KB.
What: /sys/kernel/config/tsm/report/$name/generation
Date: September, 2023
KernelVersion: v6.7

17
Documentation/ABI/testing/configfs-usb-gadget-midi
View File

@@ -4,11 +4,12 @@ KernelVersion: 3.19
Description:
The attributes:
========== ====================================
index index value for the USB MIDI adapter
id ID string for the USB MIDI adapter
buflen MIDI buffer length
qlen USB read request queue length
in_ports number of MIDI input ports
out_ports number of MIDI output ports
========== ====================================
================ ====================================
index index value for the USB MIDI adapter
id ID string for the USB MIDI adapter
buflen MIDI buffer length
qlen USB read request queue length
in_ports number of MIDI input ports
out_ports number of MIDI output ports
interface_string USB AudioControl interface string
================ ====================================

4
Documentation/ABI/testing/sysfs-block-zram
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@@ -151,11 +151,11 @@ Description:
The algorithm_params file is write-only and is used to setup
compression algorithm parameters.
What: /sys/block/zram<id>/writeback_compressed
What: /sys/block/zram<id>/compressed_writeback
Date: Decemeber 2025
Contact: Richard Chang <richardycc@google.com>
Description:
The writeback_compressed device atrribute toggles compressed
The compressed_writeback device atrribute toggles compressed
writeback feature.
What: /sys/block/zram<id>/writeback_batch_size

4
Documentation/ABI/testing/sysfs-bus-coresight-devices-dummy-source
View File

@@ -1,7 +1,7 @@
What: /sys/bus/coresight/devices/dummy_source<N>/enable_source
Date: Dec 2024
KernelVersion: 6.14
Contact: Mao Jinlong <quic_jinlmao@quicinc.com>
Contact: Mao Jinlong <jinlong.mao@oss.qualcomm.com>
Description: (RW) Enable/disable tracing of dummy source. A sink should be activated
before enabling the source. The path of coresight components linking
the source to the sink is configured and managed automatically by the
@@ -10,7 +10,7 @@ Description: (RW) Enable/disable tracing of dummy source. A sink should be activ
What: /sys/bus/coresight/devices/dummy_source<N>/traceid
Date: Dec 2024
KernelVersion: 6.14
Contact: Mao Jinlong <quic_jinlmao@quicinc.com>
Contact: Mao Jinlong <jinlong.mao@oss.qualcomm.com>
Description: (R) Show the trace ID that will appear in the trace stream
coming from this trace entity.

69
Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda Normal file
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@@ -0,0 +1,69 @@
What: /sys/bus/coresight/devices/<tpda-name>/trig_async_enable
Date: December 2025
KernelVersion: 6.20
Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>, Jie Gan <jie.gan@oss.qualcomm.com>
Description:
(RW) Enable/disable cross trigger synchronization sequence interface.
What: /sys/bus/coresight/devices/<tpda-name>/trig_flag_ts_enable
Date: December 2025
KernelVersion: 6.20
Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>, Jie Gan <jie.gan@oss.qualcomm.com>
Description:
(RW) Enable/disable cross trigger FLAG packet request interface.
What: /sys/bus/coresight/devices/<tpda-name>/trig_freq_enable
Date: December 2025
KernelVersion: 6.20
Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>, Jie Gan <jie.gan@oss.qualcomm.com>
Description:
(RW) Enable/disable cross trigger FREQ packet request interface.
What: /sys/bus/coresight/devices/<tpda-name>/freq_ts_enable
Date: December 2025
KernelVersion: 6.20
Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>, Jie Gan <jie.gan@oss.qualcomm.com>
Description:
(RW) Enable/disable the timestamp for all FREQ packets.
What: /sys/bus/coresight/devices/<tpda-name>/cmbchan_mode
Date: December 2025
KernelVersion: 6.20
Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>, Jie Gan <jie.gan@oss.qualcomm.com>
Description:
(RW) Configure the CMB/MCMB channel mode for all enabled ports.
Value 0 means raw channel mapping mode. Value 1 means channel pair marking mode.
What: /sys/bus/coresight/devices/<tpda-name>/global_flush_req
Date: December 2025
KernelVersion: 6.20
Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>, Jie Gan <jie.gan@oss.qualcomm.com>
Description:
(RW) Set global (all ports) flush request bit. The bit remains set until a
global flush request sequence completes.
What: /sys/bus/coresight/devices/<tpda-name>/syncr_mode
Date: December 2025
KernelVersion: 6.20
Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>, Jie Gan <jie.gan@oss.qualcomm.com>
Description:
(RW) Set mode the of the syncr counter.
mode 0 - COUNT[11:0] value represents the approximate number of bytes moved between two ASYNC packet requests
mode 1 - the bits COUNT[11:7] are used as a power of 2. for example, we could insert an async packet every 8K
data by writing a value 13 to the COUNT[11:7] field.
What: /sys/bus/coresight/devices/<tpda-name>/syncr_count
Date: December 2025
KernelVersion: 6.20
Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>, Jie Gan <jie.gan@oss.qualcomm.com>
Description:
(RW) Set value the of the syncr counter.
Range: 0-4095
What: /sys/bus/coresight/devices/<tpda-name>/port_flush_req
Date: December 2025
KernelVersion: 6.20
Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>, Jie Gan <jie.gan@oss.qualcomm.com>
Description:
(RW) Configure the bit i to requests a flush operation of port i on the TPDA.
The requested bit(s) remain set until the flush request completes.

56
Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm
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@@ -1,7 +1,7 @@
What: /sys/bus/coresight/devices/<tpdm-name>/integration_test
Date: January 2023
KernelVersion: 6.2
Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>
Description:
(Write) Run integration test for tpdm. Integration test
will generate test data for tpdm. It can help to make
@@ -15,7 +15,7 @@ Description:
What: /sys/bus/coresight/devices/<tpdm-name>/reset_dataset
Date: March 2023
KernelVersion: 6.7
Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>
Description:
(Write) Reset the dataset of the tpdm.
@@ -25,7 +25,7 @@ Description:
What: /sys/bus/coresight/devices/<tpdm-name>/dsb_trig_type
Date: March 2023
KernelVersion: 6.7
Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>
Description:
(RW) Set/Get the trigger type of the DSB for tpdm.
@@ -36,7 +36,7 @@ Description:
What: /sys/bus/coresight/devices/<tpdm-name>/dsb_trig_ts
Date: March 2023
KernelVersion: 6.7
Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>
Description:
(RW) Set/Get the trigger timestamp of the DSB for tpdm.
@@ -47,7 +47,7 @@ Description:
What: /sys/bus/coresight/devices/<tpdm-name>/dsb_mode
Date: March 2023
KernelVersion: 6.7
Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>
Description:
(RW) Set/Get the programming mode of the DSB for tpdm.
@@ -61,7 +61,7 @@ Description:
What: /sys/bus/coresight/devices/<tpdm-name>/dsb_edge/ctrl_idx
Date: March 2023
KernelVersion: 6.7
Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>
Description:
(RW) Set/Get the index number of the edge detection for the DSB
subunit TPDM. Since there are at most 256 edge detections, this
@@ -70,7 +70,7 @@ Description:
What: /sys/bus/coresight/devices/<tpdm-name>/dsb_edge/ctrl_val
Date: March 2023
KernelVersion: 6.7
Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>
Description:
Write a data to control the edge detection corresponding to
the index number. Before writing data to this sysfs file,
@@ -86,7 +86,7 @@ Description:
What: /sys/bus/coresight/devices/<tpdm-name>/dsb_edge/ctrl_mask
Date: March 2023
KernelVersion: 6.7
Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>
Description:
Write a data to mask the edge detection corresponding to the index
number. Before writing data to this sysfs file, "ctrl_idx" should
@@ -98,21 +98,21 @@ Description:
What: /sys/bus/coresight/devices/<tpdm-name>/dsb_edge/edcr[0:15]
Date: March 2023
KernelVersion: 6.7
Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>
Description:
Read a set of the edge control value of the DSB in TPDM.
What: /sys/bus/coresight/devices/<tpdm-name>/dsb_edge/edcmr[0:7]
Date: March 2023
KernelVersion: 6.7
Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>
Description:
Read a set of the edge control mask of the DSB in TPDM.
What: /sys/bus/coresight/devices/<tpdm-name>/dsb_trig_patt/xpr[0:7]
Date: March 2023
KernelVersion: 6.7
Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>
Description:
(RW) Set/Get the value of the trigger pattern for the DSB
subunit TPDM.
@@ -120,7 +120,7 @@ Description:
What: /sys/bus/coresight/devices/<tpdm-name>/dsb_trig_patt/xpmr[0:7]
Date: March 2023
KernelVersion: 6.7
Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>
Description:
(RW) Set/Get the mask of the trigger pattern for the DSB
subunit TPDM.
@@ -128,21 +128,21 @@ Description:
What: /sys/bus/coresight/devices/<tpdm-name>/dsb_patt/tpr[0:7]
Date: March 2023
KernelVersion: 6.7
Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>
Description:
(RW) Set/Get the value of the pattern for the DSB subunit TPDM.
What: /sys/bus/coresight/devices/<tpdm-name>/dsb_patt/tpmr[0:7]
Date: March 2023
KernelVersion: 6.7
Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>
Description:
(RW) Set/Get the mask of the pattern for the DSB subunit TPDM.
What: /sys/bus/coresight/devices/<tpdm-name>/dsb_patt/enable_ts
Date: March 2023
KernelVersion: 6.7
Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>
Description:
(Write) Set the pattern timestamp of DSB tpdm. Read
the pattern timestamp of DSB tpdm.
@@ -154,7 +154,7 @@ Description:
What: /sys/bus/coresight/devices/<tpdm-name>/dsb_patt/set_type
Date: March 2023
KernelVersion: 6.7
Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>
Description:
(Write) Set the pattern type of DSB tpdm. Read
the pattern type of DSB tpdm.
@@ -166,7 +166,7 @@ Description:
What: /sys/bus/coresight/devices/<tpdm-name>/dsb_msr/msr[0:31]
Date: March 2023
KernelVersion: 6.7
Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>
Description:
(RW) Set/Get the MSR(mux select register) for the DSB subunit
TPDM.
@@ -174,7 +174,7 @@ Description:
What: /sys/bus/coresight/devices/<tpdm-name>/cmb_mode
Date: January 2024
KernelVersion: 6.9
Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>
Description: (Write) Set the data collection mode of CMB tpdm. Continuous
change creates CMB data set elements on every CMBCLK edge.
Trace-on-change creates CMB data set elements only when a new
@@ -188,7 +188,7 @@ Description: (Write) Set the data collection mode of CMB tpdm. Continuous
What: /sys/bus/coresight/devices/<tpdm-name>/cmb_trig_patt/xpr[0:1]
Date: January 2024
KernelVersion: 6.9
Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>
Description:
(RW) Set/Get the value of the trigger pattern for the CMB
subunit TPDM.
@@ -196,7 +196,7 @@ Description:
What: /sys/bus/coresight/devices/<tpdm-name>/cmb_trig_patt/xpmr[0:1]
Date: January 2024
KernelVersion: 6.9
Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>
Description:
(RW) Set/Get the mask of the trigger pattern for the CMB
subunit TPDM.
@@ -204,21 +204,21 @@ Description:
What: /sys/bus/coresight/devices/<tpdm-name>/dsb_patt/tpr[0:1]
Date: January 2024
KernelVersion: 6.9
Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>
Description:
(RW) Set/Get the value of the pattern for the CMB subunit TPDM.
What: /sys/bus/coresight/devices/<tpdm-name>/dsb_patt/tpmr[0:1]
Date: January 2024
KernelVersion: 6.9
Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>
Description:
(RW) Set/Get the mask of the pattern for the CMB subunit TPDM.
What: /sys/bus/coresight/devices/<tpdm-name>/cmb_patt/enable_ts
Date: January 2024
KernelVersion: 6.9
Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>
Description:
(Write) Set the pattern timestamp of CMB tpdm. Read
the pattern timestamp of CMB tpdm.
@@ -230,7 +230,7 @@ Description:
What: /sys/bus/coresight/devices/<tpdm-name>/cmb_trig_ts
Date: January 2024
KernelVersion: 6.9
Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>
Description:
(RW) Set/Get the trigger timestamp of the CMB for tpdm.
@@ -241,7 +241,7 @@ Description:
What: /sys/bus/coresight/devices/<tpdm-name>/cmb_ts_all
Date: January 2024
KernelVersion: 6.9
Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>
Description:
(RW) Read or write the status of timestamp upon all interface.
Only value 0 and 1 can be written to this node. Set this node to 1 to request
@@ -253,7 +253,7 @@ Description:
What: /sys/bus/coresight/devices/<tpdm-name>/cmb_msr/msr[0:31]
Date: January 2024
KernelVersion: 6.9
Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>
Description:
(RW) Set/Get the MSR(mux select register) for the CMB subunit
TPDM.
@@ -261,7 +261,7 @@ Description:
What: /sys/bus/coresight/devices/<tpdm-name>/mcmb_trig_lane
Date: Feb 2025
KernelVersion 6.15
Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>
Description:
(RW) Set/Get which lane participates in the output pattern
match cross trigger mechanism for the MCMB subunit TPDM.
@@ -269,7 +269,7 @@ Description:
What: /sys/bus/coresight/devices/<tpdm-name>/mcmb_lanes_select
Date: Feb 2025
KernelVersion 6.15
Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>
Description:
(RW) Set/Get the enablement of the individual lane.

9
Documentation/ABI/testing/sysfs-bus-iio-cros-ec
View File

@@ -3,9 +3,12 @@ Date: July 2015
KernelVersion: 4.7
Contact: linux-iio@vger.kernel.org
Description:
Writing '1' will perform a FOC (Fast Online Calibration). The
corresponding calibration offsets can be read from `*_calibbias`
entries.
Writing '1' either perform a FOC (Fast Online Calibration) or
enter calibration mode.
Writing '0` exits calibration mode. It is a NOP for FOC enabled
sensors.
The corresponding calibration offsets can be read from `*_calibbias`
entries.
What: /sys/bus/iio/devices/iio:deviceX/id
Date: September 2017

42
Documentation/ABI/testing/sysfs-bus-pci-drivers-xhci_hcd
View File

@@ -85,3 +85,45 @@ Description:
up to 5000. The default value is 64 ms.
This polling interval is used while DbC is enabled but has no
active data transfers.
What: /sys/bus/pci/drivers/xhci_hcd/.../dbc_serial
Date: January 2026
Contact: Łukasz Bartosik <ukaszb@chromium.org>
Description:
The dbc_serial attribute allows to change the serial number
string descriptor presented by the debug device when a host
requests a string descriptor with iSerialNumber index.
Index is found in the iSerialNumber field in the device
descriptor.
Value can only be changed while debug capability (DbC) is in
disabled state to prevent USB device descriptor change while
connected to a USB host.
The default value is "0001".
The field length can be from 1 to 126 characters.
What: /sys/bus/pci/drivers/xhci_hcd/.../dbc_product
Date: January 2026
Contact: Łukasz Bartosik <ukaszb@chromium.org>
Description:
The dbc_product attribute allows to change the product string
descriptor presented by the debug device when a host requests
a string descriptor with iProduct index.
Index is found in the iProduct field in the device descriptor.
Value can only be changed while debug capability (DbC) is in
disabled state to prevent USB device descriptor change while
connected to a USB host.
The default value is "Linux USB Debug Target".
The field length can be from 1 to 126 characters.
What: /sys/bus/pci/drivers/xhci_hcd/.../dbc_manufacturer
Date: January 2026
Contact: Łukasz Bartosik <ukaszb@chromium.org>
Description:
The dbc_manufacturer attribute allows to change the manufacturer
string descriptor presented by the debug device when a host
requests a string descriptor with iManufacturer index.
Value can only be changed while debug capability (DbC) is in
disabled state to prevent USB device descriptor change while
connected to a USB host.
The default value is "Linux Foundation".
The field length can be from 1 to 126 characters.

11
Documentation/ABI/testing/sysfs-class-spi-eeprom
View File

@@ -17,3 +17,14 @@ Description:
from the device.
This is a read-only attribute.
What: /sys/class/spi_master/spi<bus>/spi<bus>.<dev>/jedec_id
Date: January 2026
KernelVersion: 6.19
Contact: Patrick Wicki <patrick.wicki@siemens.com>
Description:
Contains the raw JEDEC ID bytes returned by the RDID (0x9f) command. The
bytes are exposed as a hex string in big-endian order as read from the
device.
This is a read-only attribute.

11
Documentation/ABI/testing/sysfs-class-typec
View File

@@ -162,6 +162,17 @@ Description: Lists the supported USB Modes. The default USB mode that is used
- usb3 (USB 3.2)
- usb4 (USB4)
What: /sys/class/typec/<port>/<alt-mode>/priority
Date: July 2025
Contact: Andrei Kuchynski <akuchynski@chromium.org>
Description:
Displays and allows setting the priority for a specific alternate mode.
The priority is an integer in the range 0-255. A lower numerical value
indicates a higher priority (0 is the highest).
If the new value is already in use by another mode, the priority of the
conflicting mode and any subsequent modes will be incremented until they
are all unique.
USB Type-C partner devices (eg. /sys/class/typec/port0-partner/)
What: /sys/class/typec/<port>-partner/accessory_mode

10
Documentation/ABI/testing/sysfs-driver-uniwill-laptop
View File

@@ -1,4 +1,4 @@
What: /sys/bus/platform/devices/INOU0000:XX/fn_lock_toggle_enable
What: /sys/bus/platform/devices/INOU0000:XX/fn_lock
Date: November 2025
KernelVersion: 6.19
Contact: Armin Wolf <W_Armin@gmx.de>
@@ -8,15 +8,15 @@ Description:
Reading this file returns the current enable status of the FN lock functionality.
What: /sys/bus/platform/devices/INOU0000:XX/super_key_toggle_enable
What: /sys/bus/platform/devices/INOU0000:XX/super_key_enable
Date: November 2025
KernelVersion: 6.19
Contact: Armin Wolf <W_Armin@gmx.de>
Description:
Allows userspace applications to enable/disable the super key functionality
of the integrated keyboard by writing "1"/"0" into this file.
Allows userspace applications to enable/disable the super key of the integrated
keyboard by writing "1"/"0" into this file.
Reading this file returns the current enable status of the super key functionality.
Reading this file returns the current enable status of the super key.
What: /sys/bus/platform/devices/INOU0000:XX/touchpad_toggle_enable
Date: November 2025

62
Documentation/ABI/testing/sysfs-fs-f2fs
View File

@@ -520,7 +520,7 @@ What: /sys/fs/f2fs/<disk>/ckpt_thread_ioprio
Date: January 2021
Contact: "Daeho Jeong" <daehojeong@google.com>
Description: Give a way to change checkpoint merge daemon's io priority.
Its default value is "be,3", which means "BE" I/O class and
Its default value is "rt,3", which means "RT" I/O class and
I/O priority "3". We can select the class between "rt" and "be",
and set the I/O priority within valid range of it. "," delimiter
is necessary in between I/O class and priority number.
@@ -732,7 +732,7 @@ Description: Support configuring fault injection type, should be
FAULT_TRUNCATE 0x00000400
FAULT_READ_IO 0x00000800
FAULT_CHECKPOINT 0x00001000
FAULT_DISCARD 0x00002000
FAULT_DISCARD 0x00002000 (obsolete)
FAULT_WRITE_IO 0x00004000
FAULT_SLAB_ALLOC 0x00008000
FAULT_DQUOT_INIT 0x00010000
@@ -741,8 +741,10 @@ Description: Support configuring fault injection type, should be
FAULT_BLKADDR_CONSISTENCE 0x00080000
FAULT_NO_SEGMENT 0x00100000
FAULT_INCONSISTENT_FOOTER 0x00200000
FAULT_TIMEOUT 0x00400000 (1000ms)
FAULT_ATOMIC_TIMEOUT 0x00400000 (1000ms)
FAULT_VMALLOC 0x00800000
FAULT_LOCK_TIMEOUT 0x01000000 (1000ms)
FAULT_SKIP_WRITE 0x02000000
=========================== ==========
What: /sys/fs/f2fs/<disk>/discard_io_aware_gran
@@ -939,3 +941,57 @@ Description: Controls write priority in multi-devices setups. A value of 0 means
allocate_section_policy = 1 Prioritize writing to section before allocate_section_hint
allocate_section_policy = 2 Prioritize writing to section after allocate_section_hint
=========================== ==========================================================
What: /sys/fs/f2fs/<disk>/max_lock_elapsed_time
Date: December 2025
Contact: "Chao Yu" <chao@kernel.org>
Description: This is a threshold, once a thread enters critical region that lock covers, total
elapsed time exceeds this threshold, f2fs will print tracepoint to dump information
of related context. This sysfs entry can be used to control the value of threshold,
by default, the value is 500 ms.
What: /sys/fs/f2fs/<disk>/inject_timeout_type
Date: December 2025
Contact: "Chao Yu" <chao@kernel.org>
Description: This sysfs entry can be used to change type of injected timeout:
========== ===============================
Flag_Value Flag_Description
========== ===============================
0x00000000 No timeout (default)
0x00000001 Simulate running time
0x00000002 Simulate IO type sleep time
0x00000003 Simulate Non-IO type sleep time
0x00000004 Simulate runnable time
========== ===============================
What: /sys/fs/f2fs/<disk>/adjust_lock_priority
Date: January 2026
Contact: "Chao Yu" <chao@kernel.org>
Description: This sysfs entry can be used to enable/disable to adjust priority for task
which is in critical region covered by lock.
========== ==================
Flag_Value Flag_Description
========== ==================
0x00000000 Disabled (default)
0x00000001 cp_rwsem
0x00000002 node_change
0x00000004 node_write
0x00000008 gc_lock
0x00000010 cp_global
0x00000020 io_rwsem
========== ==================
What: /sys/fs/f2fs/<disk>/lock_duration_priority
Date: January 2026
Contact: "Chao Yu" <chao@kernel.org>
Description: f2fs can tune priority of thread which has entered into critical region covered by
f2fs rwsemphore lock. This sysfs entry can be used to control priority value, the
range is [100,139], by default the value is 120.
What: /sys/fs/f2fs/<disk>/critical_task_priority
Date: February 2026
Contact: "Chao Yu" <chao@kernel.org>
Description: It can be used to tune priority of f2fs critical task, e.g. f2fs_ckpt, f2fs_gc
threads, limitation as below:
- it requires user has CAP_SYS_NICE capability.
- the range is [100, 139], by default the value is 100.

6
Documentation/admin-guide/blockdev/zram.rst
View File

@@ -216,7 +216,7 @@ writeback_limit WO specifies the maximum amount of write IO zram
writeback_limit_enable RW show and set writeback_limit feature
writeback_batch_size RW show and set maximum number of in-flight
writeback operations
writeback_compressed RW show and set compressed writeback feature
compressed_writeback RW show and set compressed writeback feature
comp_algorithm RW show and change the compression algorithm
algorithm_params WO setup compression algorithm parameters
compact WO trigger memory compaction
@@ -439,11 +439,11 @@ budget in next setting is user's job.
By default zram stores written back pages in decompressed (raw) form, which
means that writeback operation involves decompression of the page before
writing it to the backing device. This behavior can be changed by enabling
`writeback_compressed` feature, which causes zram to write compressed pages
`compressed_writeback` feature, which causes zram to write compressed pages
to the backing device, thus avoiding decompression overhead. To enable
this feature, execute::
$ echo yes > /sys/block/zramX/writeback_compressed
$ echo yes > /sys/block/zramX/compressed_writeback
Note that this feature should be configured before the `zramX` device is
initialized.

24
Documentation/admin-guide/bootconfig.rst
View File

@@ -20,18 +20,26 @@ Config File Syntax
The boot config syntax is a simple structured key-value. Each key consists
of dot-connected-words, and key and value are connected by ``=``. The value
has to be terminated by semi-colon (``;``) or newline (``\n``).
For array value, array entries are separated by comma (``,``). ::
KEY[.WORD[...]] = VALUE[, VALUE2[...]][;]
Unlike the kernel command line syntax, spaces are OK around the comma and ``=``.
string has to be terminated by the following delimiters described below.
Each key word must contain only alphabets, numbers, dash (``-``) or underscore
(``_``). And each value only contains printable characters or spaces except
for delimiters such as semi-colon (``;``), new-line (``\n``), comma (``,``),
hash (``#``) and closing brace (``}``).
If the ``=`` is followed by whitespace up to one of these delimiters, the
key is assigned an empty value.
For arrays, the array values are comma (``,``) separated, and comments and
line breaks with newline (``\n``) are allowed between array values for
readability. Thus the first entry of the array must be on the same line as
the key.::
KEY[.WORD[...]] = VALUE[, VALUE2[...]][;]
Unlike the kernel command line syntax, white spaces (including tabs) are
ignored around the comma and ``=``.
If you want to use those delimiters in a value, you can use either double-
quotes (``"VALUE"``) or single-quotes (``'VALUE'``) to quote it. Note that
you can not escape these quotes.
@@ -138,8 +146,8 @@ This is parsed as below::
foo = value
bar = 1, 2, 3
Note that you can not put a comment between value and delimiter(``,`` or
``;``). This means following config has a syntax error ::
Note that you can NOT put a comment or a newline between value and delimiter
(``,`` or ``;``). This means following config has a syntax error ::
key = 1 # comment
,2

2
Documentation/admin-guide/devices.txt
View File

@@ -352,7 +352,7 @@
216 = /dev/fujitsu/apanel Fujitsu/Siemens application panel
217 = /dev/ni/natmotn National Instruments Motion
218 = /dev/kchuid Inter-process chuid control
219 = /dev/modems/mwave MWave modem firmware upload
219 =
220 = /dev/mptctl Message passing technology (MPT) control
221 = /dev/mvista/hssdsi Montavista PICMG hot swap system driver
222 = /dev/mvista/hasi Montavista PICMG high availability

18
Documentation/admin-guide/kernel-parameters.txt
View File

@@ -74,6 +74,7 @@
TPM TPM drivers are enabled.
UMS USB Mass Storage support is enabled.
USB USB support is enabled.
NVME NVMe support is enabled
USBHID USB Human Interface Device support is enabled.
V4L Video For Linux support is enabled.
VGA The VGA console has been enabled.
@@ -4661,7 +4662,7 @@ Kernel parameters
nosmt [KNL,MIPS,PPC,EARLY] Disable symmetric multithreading (SMT).
Equivalent to smt=1.
[KNL,X86,PPC,S390] Disable symmetric multithreading (SMT).
[KNL,LOONGARCH,X86,PPC,S390] Disable symmetric multithreading (SMT).
nosmt=force: Force disable SMT, cannot be undone
via the sysfs control file.
@@ -4787,6 +4788,18 @@ Kernel parameters
This can be set from sysctl after boot.
See Documentation/admin-guide/sysctl/vm.rst for details.
nvme.quirks= [NVME] A list of quirk entries to augment the built-in
nvme quirk list. List entries are separated by a
'-' character.
Each entry has the form VendorID:ProductID:quirk_names.
The IDs are 4-digits hex numbers and quirk_names is a
list of quirk names separated by commas. A quirk name
can be prefixed by '^', meaning that the specified
quirk must be disabled.
Example:
nvme.quirks=7710:2267:bogus_nid,^identify_cns-9900:7711:broken_msi
ohci1394_dma=early [HW,EARLY] enable debugging via the ohci1394 driver.
See Documentation/core-api/debugging-via-ohci1394.rst for more
info.
@@ -8183,6 +8196,9 @@ Kernel parameters
p = USB_QUIRK_SHORT_SET_ADDRESS_REQ_TIMEOUT
(Reduce timeout of the SET_ADDRESS
request from 5000 ms to 500 ms);
q = USB_QUIRK_FORCE_ONE_CONFIG (Device
claims zero configurations,
forcing to 1);
Example: quirks=0781:5580:bk,0a5c:5834:gij
usbhid.mousepoll=

2
Documentation/admin-guide/laptops/toshiba_haps.rst
View File

@@ -43,7 +43,7 @@ RSSS Shuts down the HDD protection interface for a few seconds,
==== =====================================================================
Note:
The presence of Solid State Drives (SSD) can make this driver to fail loading,
The presence of Solid State Drives (SSD) can cause this driver to fail loading,
given the fact that such drives have no movable parts, and thus, not requiring
any "protection" as well as failing during the evaluation of the _STA method
found under this device.

2
Documentation/admin-guide/laptops/uniwill-laptop.rst
View File

@@ -24,7 +24,7 @@ Keyboard settings
The ``uniwill-laptop`` driver allows the user to enable/disable:
- the FN and super key lock functionality of the integrated keyboard
- the FN lock and super key of the integrated keyboard
- the touchpad toggle functionality of the integrated touchpad
See Documentation/ABI/testing/sysfs-driver-uniwill-laptop for details.

11
Documentation/admin-guide/pm/intel_idle.rst
View File

@@ -260,6 +260,17 @@ mode to off when the CPU is in any one of the available idle states. This may
help performance of a sibling CPU at the expense of a slightly higher wakeup
latency for the idle CPU.
The ``table`` argument allows customization of idle state latency and target
residency. The syntax is a comma-separated list of ``name:latency:residency``
entries, where ``name`` is the idle state name, ``latency`` is the exit latency
in microseconds, and ``residency`` is the target residency in microseconds. It
is not necessary to specify all idle states; only those to be customized. For
example, ``C1:1:3,C6:50:100`` sets the exit latency and target residency for
C1 and C6 to 1/3 and 50/100 microseconds, respectively. Remaining idle states
keep their default values. The driver verifies that deeper idle states have
higher latency and target residency than shallower ones. Also, target
residency cannot be smaller than exit latency. If any of these conditions is
not met, the driver ignores the entire ``table`` parameter.
.. _intel-idle-core-and-package-idle-states:

55
Documentation/admin-guide/sysctl/net.rst
View File

@@ -40,8 +40,8 @@ Table : Subdirectories in /proc/sys/net
bridge Bridging rose X.25 PLP layer
core General parameter tipc TIPC
ethernet Ethernet protocol unix Unix domain sockets
ipv4 IP version 4 x25 X.25 protocol
ipv6 IP version 6
ipv4 IP version 4 vsock VSOCK sockets
ipv6 IP version 6 x25 X.25 protocol
========= =================== = ========== ===================
1. /proc/sys/net/core - Network core options
@@ -551,3 +551,54 @@ originally may have been issued in the correct sequential order.
If named_timeout is nonzero, failed topology updates will be placed on a defer
queue until another event arrives that clears the error, or until the timeout
expires. Value is in milliseconds.
6. /proc/sys/net/vsock - VSOCK sockets
--------------------------------------
VSOCK sockets (AF_VSOCK) provide communication between virtual machines and
their hosts. The behavior of VSOCK sockets in a network namespace is determined
by the namespace's mode (``global`` or ``local``), which controls how CIDs
(Context IDs) are allocated and how sockets interact across namespaces.
ns_mode
-------
Read-only. Reports the current namespace's mode, set at namespace creation
and immutable thereafter.
Values:
- ``global`` - the namespace shares system-wide CID allocation and
its sockets can reach any VM or socket in any global namespace.
Sockets in this namespace cannot reach sockets in local
namespaces.
- ``local`` - the namespace has private CID allocation and its
sockets can only connect to VMs or sockets within the same
namespace.
The init_net mode is always ``global``.
child_ns_mode
-------------
Controls what mode newly created child namespaces will inherit. At namespace
creation, ``ns_mode`` is inherited from the parent's ``child_ns_mode``. The
initial value matches the namespace's own ``ns_mode``.
Values:
- ``global`` - child namespaces will share system-wide CID allocation
and their sockets will be able to reach any VM or socket in any
global namespace.
- ``local`` - child namespaces will have private CID allocation and
their sockets will only be able to connect within their own
namespace.
The first write to ``child_ns_mode`` locks its value. Subsequent writes of the
same value succeed, but writing a different value returns ``-EBUSY``.
Changing ``child_ns_mode`` only affects namespaces created after the change;
it does not modify the current namespace or any existing children.
A namespace with ``ns_mode`` set to ``local`` cannot change
``child_ns_mode`` to ``global`` (returns ``-EPERM``).

2
Documentation/admin-guide/thunderbolt.rst
View File

@@ -370,7 +370,7 @@ is built-in to the kernel image, there is no need to do anything.
The driver will create one virtual ethernet interface per Thunderbolt
port which are named like ``thunderbolt0`` and so on. From this point
you can either use standard userspace tools like ``ifconfig`` to
you can either use standard userspace tools like ``ip`` to
configure the interface or let your GUI handle it automatically.
Forcing power

6
Documentation/core-api/rbtree.rst
View File

@@ -197,7 +197,7 @@ Cached rbtrees
--------------
Computing the leftmost (smallest) node is quite a common task for binary
search trees, such as for traversals or users relying on a the particular
search trees, such as for traversals or users relying on the particular
order for their own logic. To this end, users can use 'struct rb_root_cached'
to optimize O(logN) rb_first() calls to a simple pointer fetch avoiding
potentially expensive tree iterations. This is done at negligible runtime
@@ -255,7 +255,7 @@ affected subtrees.
When erasing a node, the user must call rb_erase_augmented() instead of
rb_erase(). rb_erase_augmented() calls back into user provided functions
to updated the augmented information on affected subtrees.
to update the augmented information on affected subtrees.
In both cases, the callbacks are provided through struct rb_augment_callbacks.
3 callbacks must be defined:
@@ -293,7 +293,7 @@ way making it possible to do efficient lookup and exact match.
This "extra information" stored in each node is the maximum hi
(max_hi) value among all the nodes that are its descendants. This
information can be maintained at each node just be looking at the node
information can be maintained at each node just by looking at the node
and its immediate children. And this will be used in O(log n) lookup
for lowest match (lowest start address among all possible matches)
with something like::

21
Documentation/dev-tools/coccinelle.rst
View File

@@ -127,6 +127,18 @@ To enable verbose messages set the V= variable, for example::
make coccicheck MODE=report V=1
By default, coccicheck will print debug logs to stdout and redirect stderr to
/dev/null. This can make coccicheck output difficult to read and understand.
Debug and error messages can instead be written to a debug file instead by
setting the ``DEBUG_FILE`` variable::
make coccicheck MODE=report DEBUG_FILE="cocci.log"
Coccinelle cannot overwrite a debug file. Instead of repeatedly deleting a log
file, you could include the datetime in the debug file name::
make coccicheck MODE=report DEBUG_FILE="cocci-$(date -Iseconds).log"
Coccinelle parallelization
--------------------------
@@ -208,11 +220,10 @@ include options matching the options used when we compile the kernel.
You can learn what these options are by using V=1; you could then
manually run Coccinelle with debug options added.
Alternatively you can debug running Coccinelle against SmPL patches
by asking for stderr to be redirected to stderr. By default stderr
is redirected to /dev/null; if you'd like to capture stderr you
can specify the ``DEBUG_FILE="file.txt"`` option to coccicheck. For
instance::
An easier approach to debug running Coccinelle against SmPL patches is to ask
coccicheck to redirect stderr to a debug file. As mentioned in the examples, by
default stderr is redirected to /dev/null; if you'd like to capture stderr you
can specify the ``DEBUG_FILE="file.txt"`` option to coccicheck. For instance::
rm -f cocci.err
make coccicheck COCCI=scripts/coccinelle/free/kfree.cocci MODE=report DEBUG_FILE=cocci.err

2
Documentation/devicetree/bindings/arm/arm,coresight-dummy-sink.yaml
View File

@@ -31,7 +31,7 @@ maintainers:
- Mike Leach <mike.leach@linaro.org>
- Suzuki K Poulose <suzuki.poulose@arm.com>
- James Clark <james.clark@linaro.org>
- Mao Jinlong <quic_jinlmao@quicinc.com>
- Mao Jinlong <jinlong.mao@oss.qualcomm.com>
- Hao Zhang <quic_hazha@quicinc.com>
properties:

2
Documentation/devicetree/bindings/arm/arm,coresight-dummy-source.yaml
View File

@@ -30,7 +30,7 @@ maintainers:
- Mike Leach <mike.leach@linaro.org>
- Suzuki K Poulose <suzuki.poulose@arm.com>
- James Clark <james.clark@linaro.org>
- Mao Jinlong <quic_jinlmao@quicinc.com>
- Mao Jinlong <jinlong.mao@oss.qualcomm.com>
- Hao Zhang <quic_hazha@quicinc.com>
properties:

15
Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml
View File

@@ -7,9 +7,9 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: CoreSight TMC Control Unit
maintainers:
- Yuanfang Zhang <quic_yuanfang@quicinc.com>
- Mao Jinlong <quic_jinlmao@quicinc.com>
- Jie Gan <quic_jiegan@quicinc.com>
- Yuanfang Zhang <yuanfang.zhang@oss.qualcomm.com>
- Mao Jinlong <jinlong.mao@oss.qualcomm.com>
- Jie Gan <jie.gan@oss.qualcomm.com>
description: |
The Trace Memory Controller(TMC) is used for Embedded Trace Buffer(ETB),
@@ -26,8 +26,13 @@ description: |
properties:
compatible:
enum:
- qcom,sa8775p-ctcu
oneOf:
- items:
- enum:
- qcom,qcs8300-ctcu
- const: qcom,sa8775p-ctcu
- enum:
- qcom,sa8775p-ctcu
reg:
maxItems: 1

90
Documentation/devicetree/bindings/arm/qcom,coresight-itnoc.yaml Normal file
View File

@@ -0,0 +1,90 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/qcom,coresight-itnoc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Interconnect Trace Network On Chip - ITNOC
maintainers:
- Yuanfang Zhang <yuanfang.zhang@oss.qualcomm.com>
description:
The Interconnect TNOC is a CoreSight graph link that forwards trace data
from a subsystem to the Aggregator TNOC. Compared to Aggregator TNOC, it
does not have aggregation and ATID functionality.
properties:
$nodename:
pattern: "^itnoc(@[0-9a-f]+)?$"
compatible:
const: qcom,coresight-itnoc
reg:
maxItems: 1
clocks:
maxItems: 1
clock-names:
items:
- const: apb
in-ports:
$ref: /schemas/graph.yaml#/properties/ports
patternProperties:
'^port(@[0-9a-f]{1,2})?$':
description: Input connections from CoreSight Trace Bus
$ref: /schemas/graph.yaml#/properties/port
out-ports:
$ref: /schemas/graph.yaml#/properties/ports
additionalProperties: false
properties:
port:
description: out connections to aggregator TNOC
$ref: /schemas/graph.yaml#/properties/port
required:
- compatible
- reg
- clocks
- clock-names
- in-ports
- out-ports
additionalProperties: false
examples:
- |
itnoc@109ac000 {
compatible = "qcom,coresight-itnoc";
reg = <0x109ac000 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb";
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
tn_ic_in_tpdm_dcc: endpoint {
remote-endpoint = <&tpdm_dcc_out_tn_ic>;
};
};
};
out-ports {
port {
tn_ic_out_tnoc_aggr: endpoint {
/* to Aggregator TNOC input */
remote-endpoint = <&tn_ag_in_tn_ic>;
};
};
};
};
...

4
Documentation/devicetree/bindings/arm/qcom,coresight-remote-etm.yaml
View File

@@ -7,8 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Coresight Remote ETM(Embedded Trace Macrocell)
maintainers:
- Jinlong Mao <quic_jinlmao@quicinc.com>
- Tao Zhang <quic_taozha@quicinc.com>
- Jinlong Mao <jinlong.mao@oss.qualcomm.com>
- Tao Zhang <tao.zhang@oss.qualcomm.com>
description:
Support for ETM trace collection on remote processor using coresight

2
Documentation/devicetree/bindings/arm/qcom,coresight-tnoc.yaml
View File

@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Trace Network On Chip - TNOC
maintainers:
- Yuanfang Zhang <quic_yuanfang@quicinc.com>
- Yuanfang Zhang <yuanfang.zhang@oss.qualcomm.com>
description: >
The Trace Network On Chip (TNOC) is an integration hierarchy hardware

4
Documentation/devicetree/bindings/arm/qcom,coresight-tpda.yaml
View File

@@ -33,8 +33,8 @@ description: |
to sink.
maintainers:
- Mao Jinlong <quic_jinlmao@quicinc.com>
- Tao Zhang <quic_taozha@quicinc.com>
- Mao Jinlong <jinlong.mao@oss.qualcomm.com>
- Tao Zhang <tao.zhang@oss.qualcomm.com>
# Need a custom select here or 'arm,primecell' will match on lots of nodes
select:

4
Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml
View File

@@ -19,8 +19,8 @@ description: |
sources and send it to a TPDA for packetization, timestamping, and funneling.
maintainers:
- Mao Jinlong <quic_jinlmao@quicinc.com>
- Tao Zhang <quic_taozha@quicinc.com>
- Mao Jinlong <jinlong.mao@oss.qualcomm.com>
- Tao Zhang <tao.zhang@oss.qualcomm.com>
# Need a custom select here or 'arm,primecell' will match on lots of nodes
select:

116
Documentation/devicetree/bindings/clock/amlogic,t7-peripherals-clkc.yaml Normal file
View File

@@ -0,0 +1,116 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (C) 2024-2025 Amlogic, Inc. All rights reserved
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/amlogic,t7-peripherals-clkc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Amlogic T7 Peripherals Clock Controller
maintainers:
- Neil Armstrong <neil.armstrong@linaro.org>
- Jerome Brunet <jbrunet@baylibre.com>
- Xianwei Zhao <xianwei.zhao@amlogic.com>
- Jian Hu <jian.hu@amlogic.com>
properties:
compatible:
const: amlogic,t7-peripherals-clkc
reg:
maxItems: 1
'#clock-cells':
const: 1
clocks:
minItems: 14
items:
- description: input oscillator
- description: input sys clk
- description: input fixed pll
- description: input fclk div 2
- description: input fclk div 2p5
- description: input fclk div 3
- description: input fclk div 4
- description: input fclk div 5
- description: input fclk div 7
- description: input hifi pll
- description: input gp0 pll
- description: input gp1 pll
- description: input mpll1
- description: input mpll2
- description: external input rmii oscillator (optional)
- description: input video pll0 (optional)
- description: external pad input for rtc (optional)
clock-names:
minItems: 14
items:
- const: xtal
- const: sys
- const: fix
- const: fdiv2
- const: fdiv2p5
- const: fdiv3
- const: fdiv4
- const: fdiv5
- const: fdiv7
- const: hifi
- const: gp0
- const: gp1
- const: mpll1
- const: mpll2
- const: ext_rmii
- const: vid_pll0
- const: ext_rtc
required:
- compatible
- '#clock-cells'
- reg
- clocks
- clock-names
additionalProperties: false
examples:
- |
apb {
#address-cells = <2>;
#size-cells = <2>;
clkc_periphs:clock-controller@0 {
compatible = "amlogic,t7-peripherals-clkc";
reg = <0 0x0 0 0x1c8>;
#clock-cells = <1>;
clocks = <&xtal>,
<&scmi_clk 13>,
<&scmi_clk 16>,
<&scmi_clk 18>,
<&scmi_clk 20>,
<&scmi_clk 22>,
<&scmi_clk 24>,
<&scmi_clk 26>,
<&scmi_clk 28>,
<&hifi 1>,
<&gp0 1>,
<&gp1 1>,
<&mpll 4>,
<&mpll 6>;
clock-names = "xtal",
"sys",
"fix",
"fdiv2",
"fdiv2p5",
"fdiv3",
"fdiv4",
"fdiv5",
"fdiv7",
"hifi",
"gp0",
"gp1",
"mpll1",
"mpll2";
};
};

114
Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml Normal file
View File

@@ -0,0 +1,114 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (C) 2024-2025 Amlogic, Inc. All rights reserved
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/amlogic,t7-pll-clkc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Amlogic T7 PLL Clock Control Controller
maintainers:
- Neil Armstrong <neil.armstrong@linaro.org>
- Jerome Brunet <jbrunet@baylibre.com>
- Jian Hu <jian.hu@amlogic.com>
- Xianwei Zhao <xianwei.zhao@amlogic.com>
properties:
compatible:
enum:
- amlogic,t7-gp0-pll
- amlogic,t7-gp1-pll
- amlogic,t7-hifi-pll
- amlogic,t7-pcie-pll
- amlogic,t7-mpll
- amlogic,t7-hdmi-pll
- amlogic,t7-mclk-pll
reg:
maxItems: 1
'#clock-cells':
const: 1
clocks:
items:
- description: mclk pll input oscillator gate
- description: oscillator input clock source for mclk_sel_0
- description: fixed input clock source for mclk_sel_0
minItems: 1
clock-names:
items:
- const: in0
- const: in1
- const: in2
minItems: 1
required:
- compatible
- '#clock-cells'
- reg
- clocks
- clock-names
allOf:
- if:
properties:
compatible:
contains:
const: amlogic,t7-mclk-pll
then:
properties:
clocks:
minItems: 3
clock-names:
minItems: 3
- if:
properties:
compatible:
contains:
enum:
- amlogic,t7-gp0-pll
- amlogic,t7-gp1--pll
- amlogic,t7-hifi-pll
- amlogic,t7-pcie-pll
- amlogic,t7-mpll
- amlogic,t7-hdmi-pll
then:
properties:
clocks:
maxItems: 1
clock-names:
maxItems: 1
additionalProperties: false
examples:
- |
apb {
#address-cells = <2>;
#size-cells = <2>;
clock-controller@8080 {
compatible = "amlogic,t7-gp0-pll";
reg = <0 0x8080 0 0x20>;
clocks = <&scmi_clk 2>;
clock-names = "in0";
#clock-cells = <1>;
};
clock-controller@8300 {
compatible = "amlogic,t7-mclk-pll";
reg = <0 0x8300 0 0x18>;
clocks = <&scmi_clk 2>,
<&xtal>,
<&scmi_clk 31>;
clock-names = "in0", "in1", "in2";
#clock-cells = <1>;
};
};

19
Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
View File

@@ -53,6 +53,11 @@ properties:
reg:
maxItems: 1
samsung,sysreg:
$ref: /schemas/types.yaml#/definitions/phandle
description:
Phandle to system registers interface.
required:
- compatible
- "#clock-cells"
@@ -185,6 +190,18 @@ allOf:
- const: bus
- const: ip
- if:
properties:
compatible:
contains:
const: google,gs101-cmu-top
then:
properties:
samsung,sysreg: false
else:
required:
- samsung,sysreg
additionalProperties: false
examples:
@@ -194,7 +211,7 @@ examples:
cmu_top: clock-controller@1e080000 {
compatible = "google,gs101-cmu-top";
reg = <0x1e080000 0x8000>;
reg = <0x1e080000 0x10000>;
#clock-cells = <1>;
clocks = <&ext_24_5m>;
clock-names = "oscclk";

10
Documentation/devicetree/bindings/clock/mediatek,mt7622-pciesys.yaml
View File

@@ -14,11 +14,9 @@ maintainers:
properties:
compatible:
oneOf:
- items:
- const: mediatek,mt7622-pciesys
- const: syscon
- const: mediatek,mt7629-pciesys
enum:
- mediatek,mt7622-pciesys
- mediatek,mt7629-pciesys
reg:
maxItems: 1
@@ -40,7 +38,7 @@ additionalProperties: false
examples:
- |
clock-controller@1a100800 {
compatible = "mediatek,mt7622-pciesys", "syscon";
compatible = "mediatek,mt7622-pciesys";
reg = <0x1a100800 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;

6
Documentation/devicetree/bindings/clock/microchip,mpfs-ccc.yaml
View File

@@ -17,7 +17,11 @@ description: |
properties:
compatible:
const: microchip,mpfs-ccc
oneOf:
- items:
- const: microchip,pic64gx-ccc
- const: microchip,mpfs-ccc
- const: microchip,mpfs-ccc
reg:
items:

16
Documentation/devicetree/bindings/clock/microchip,mpfs-clkcfg.yaml
View File

@@ -19,7 +19,11 @@ description: |
properties:
compatible:
const: microchip,mpfs-clkcfg
oneOf:
- items:
- const: microchip,pic64gx-clkcfg
- const: microchip,mpfs-clkcfg
- const: microchip,mpfs-clkcfg
reg:
oneOf:
@@ -69,6 +73,16 @@ required:
- clocks
- '#clock-cells'
if:
properties:
compatible:
contains:
const: microchip,pic64gx-clkcfg
then:
properties:
reg:
maxItems: 1
additionalProperties: false
examples:

6
Documentation/devicetree/bindings/clock/qcom,gcc-msm8953.yaml
View File

@@ -4,7 +4,7 @@
$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8953.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller on MSM8953
title: Qualcomm Global Clock & Reset Controller on MSM8937, MSM8940, MSM8953 and SDM439
maintainers:
- Adam Skladowski <a_skl39@protonmail.com>
@@ -13,7 +13,7 @@ maintainers:
description: |
Qualcomm global clock control module provides the clocks, resets and power
domains on MSM8937 or MSM8953.
domains on MSM8937, MSM8940, MSM8953 or SDM439.
See also::
include/dt-bindings/clock/qcom,gcc-msm8917.h
@@ -23,7 +23,9 @@ properties:
compatible:
enum:
- qcom,gcc-msm8937
- qcom,gcc-msm8940
- qcom,gcc-msm8953
- qcom,gcc-sdm439
clocks:
items:

63
Documentation/devicetree/bindings/clock/qcom,kaanapali-gxclkctl.yaml Normal file
View File

@@ -0,0 +1,63 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,kaanapali-gxclkctl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Graphics power domain Controller on Kaanapali
maintainers:
- Taniya Das <taniya.das@oss.qualcomm.com>
description: |
Qualcomm GX(graphics) is a clock controller which has PLLs, clocks and
Power domains (GDSC). This module provides the power domains control
of gxclkctl on Qualcomm SoCs which helps the recovery of Graphics subsystem.
See also:
include/dt-bindings/clock/qcom,kaanapali-gxclkctl.h
properties:
compatible:
enum:
- qcom,kaanapali-gxclkctl
power-domains:
description:
Power domains required for the clock controller to operate
items:
- description: GFX power domain
- description: GMXC power domain
- description: GPUCC(CX) power domain
'#power-domain-cells':
const: 1
reg:
maxItems: 1
required:
- compatible
- reg
- power-domains
- '#power-domain-cells'
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/power/qcom,rpmhpd.h>
soc {
#address-cells = <2>;
#size-cells = <2>;
clock-controller@3d64000 {
compatible = "qcom,kaanapali-gxclkctl";
reg = <0x0 0x03d64000 0x0 0x6000>;
power-domains = <&rpmhpd RPMHPD_GFX>,
<&rpmhpd RPMHPD_GMXC>,
<&gpucc 0>;
#power-domain-cells = <1>;
};
};
...

11
Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml
View File

@@ -9,23 +9,32 @@ title: Qualcomm Camera Clock & Reset Controller on SM8450
maintainers:
- Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
- Jagadeesh Kona <quic_jkona@quicinc.com>
- Taniya Das <taniya.das@oss.qualcomm.com>
description: |
Qualcomm camera clock control module provides the clocks, resets and power
domains on SM8450.
See also:
include/dt-bindings/clock/qcom,kaanapali-camcc.h
include/dt-bindings/clock/qcom,kaanapali-cambistmclkcc.h
include/dt-bindings/clock/qcom,sm8450-camcc.h
include/dt-bindings/clock/qcom,sm8550-camcc.h
include/dt-bindings/clock/qcom,sm8650-camcc.h
include/dt-bindings/clock/qcom,sm8750-cambistmclkcc.h
include/dt-bindings/clock/qcom,sm8750-camcc.h
properties:
compatible:
enum:
- qcom,kaanapali-cambistmclkcc
- qcom,kaanapali-camcc
- qcom,sm8450-camcc
- qcom,sm8475-camcc
- qcom,sm8550-camcc
- qcom,sm8650-camcc
- qcom,sm8750-cambistmclkcc
- qcom,sm8750-camcc
clocks:
items:
@@ -63,6 +72,8 @@ allOf:
compatible:
contains:
enum:
- qcom,kaanapali-cambistmclkcc
- qcom,kaanapali-camcc
- qcom,sc8280xp-camcc
- qcom,sm8450-camcc
- qcom,sm8550-camcc

2
Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml
View File

@@ -14,6 +14,7 @@ description: |
domains on Qualcomm SoCs.
See also::
include/dt-bindings/clock/qcom,kaanapali-gpucc.h
include/dt-bindings/clock/qcom,milos-gpucc.h
include/dt-bindings/clock/qcom,sar2130p-gpucc.h
include/dt-bindings/clock/qcom,sm4450-gpucc.h
@@ -26,6 +27,7 @@ description: |
properties:
compatible:
enum:
- qcom,kaanapali-gpucc
- qcom,milos-gpucc
- qcom,sar2130p-gpucc
- qcom,sm4450-gpucc

3
Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml
View File

@@ -15,6 +15,7 @@ description: |
domains on SM8450.
See also:
include/dt-bindings/clock/qcom,kaanapali-videocc.h
include/dt-bindings/clock/qcom,sm8450-videocc.h
include/dt-bindings/clock/qcom,sm8650-videocc.h
include/dt-bindings/clock/qcom,sm8750-videocc.h
@@ -22,6 +23,7 @@ description: |
properties:
compatible:
enum:
- qcom,kaanapali-videocc
- qcom,sm8450-videocc
- qcom,sm8475-videocc
- qcom,sm8550-videocc
@@ -61,6 +63,7 @@ allOf:
compatible:
contains:
enum:
- qcom,kaanapali-videocc
- qcom,sm8450-videocc
- qcom,sm8550-videocc
- qcom,sm8750-videocc

2
Documentation/devicetree/bindings/clock/qcom,sm8550-dispcc.yaml
View File

@@ -15,6 +15,7 @@ description: |
domains on SM8550, SM8650, SM8750 and few other platforms.
See also:
- include/dt-bindings/clock/qcom,kaanapali-dispcc.h
- include/dt-bindings/clock/qcom,sm8550-dispcc.h
- include/dt-bindings/clock/qcom,sm8650-dispcc.h
- include/dt-bindings/clock/qcom,sm8750-dispcc.h
@@ -23,6 +24,7 @@ description: |
properties:
compatible:
enum:
- qcom,kaanapali-dispcc
- qcom,sar2130p-dispcc
- qcom,sm8550-dispcc
- qcom,sm8650-dispcc

11
Documentation/devicetree/bindings/clock/renesas,9series.yaml
View File

@@ -62,7 +62,7 @@ properties:
description: Output clock down spread in pcm (1/1000 of percent)
patternProperties:
"^DIF[0-19]$":
"^DIF1?[0-9]$":
type: object
description:
Description of one of the outputs (DIF0..DIF19).
@@ -107,6 +107,15 @@ examples:
DIF0 {
renesas,slew-rate = <3000000>;
};
/* Not present on 9FGV0241, used for DT validation only */
DIF2 {
renesas,slew-rate = <2000000>;
};
DIF19 {
renesas,slew-rate = <3000000>;
};
};
};

19
Documentation/devicetree/bindings/clock/samsung,exynosautov920-clock.yaml
View File

@@ -40,6 +40,7 @@ properties:
- samsung,exynosautov920-cmu-hsi2
- samsung,exynosautov920-cmu-m2m
- samsung,exynosautov920-cmu-mfc
- samsung,exynosautov920-cmu-mfd
- samsung,exynosautov920-cmu-misc
- samsung,exynosautov920-cmu-peric0
- samsung,exynosautov920-cmu-peric1
@@ -268,6 +269,24 @@ allOf:
- const: mfc
- const: wfd
- if:
properties:
compatible:
contains:
const: samsung,exynosautov920-cmu-mfd
then:
properties:
clocks:
items:
- description: External reference clock (38.4 MHz)
- description: CMU_MFD NOC clock (from CMU_TOP)
clock-names:
items:
- const: oscclk
- const: noc
required:
- compatible
- "#clock-cells"

9
Documentation/devicetree/bindings/clock/spacemit,k1-pll.yaml
View File

@@ -4,14 +4,16 @@
$id: http://devicetree.org/schemas/clock/spacemit,k1-pll.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: SpacemiT K1 PLL
title: SpacemiT K1/K3 PLL
maintainers:
- Haylen Chu <heylenay@4d2.org>
properties:
compatible:
const: spacemit,k1-pll
enum:
- spacemit,k1-pll
- spacemit,k3-pll
reg:
maxItems: 1
@@ -28,7 +30,8 @@ properties:
"#clock-cells":
const: 1
description:
See <dt-bindings/clock/spacemit,k1-syscon.h> for valid indices.
For K1 SoC, check <dt-bindings/clock/spacemit,k1-syscon.h> for valid indices.
For K3 SoC, check <dt-bindings/clock/spacemit,k3-clocks.h> for valid indices.
required:
- compatible

21
Documentation/devicetree/bindings/display/msm/dp-controller.yaml
View File

@@ -253,7 +253,6 @@ allOf:
enum:
# these platforms support 2 streams MST on some interfaces,
# others are SST only
- qcom,glymur-dp
- qcom,sc8280xp-dp
- qcom,x1e80100-dp
then:
@@ -310,6 +309,26 @@ allOf:
minItems: 6
maxItems: 8
- if:
properties:
compatible:
contains:
enum:
# these platforms support 2 streams MST on some interfaces,
# others are SST only, but all controllers have 4 ports
- qcom,glymur-dp
then:
properties:
reg:
minItems: 9
maxItems: 9
clocks:
minItems: 5
maxItems: 6
clocks-names:
minItems: 5
maxItems: 6
unevaluatedProperties: false
examples:

16
Documentation/devicetree/bindings/display/msm/qcom,glymur-mdss.yaml
View File

@@ -176,13 +176,17 @@ examples:
};
};
displayport-controller@ae90000 {
displayport-controller@af54000 {
compatible = "qcom,glymur-dp";
reg = <0xae90000 0x200>,
<0xae90200 0x200>,
<0xae90400 0x600>,
<0xae91000 0x400>,
<0xae91400 0x400>;
reg = <0xaf54000 0x200>,
<0xaf54200 0x200>,
<0xaf55000 0xc00>,
<0xaf56000 0x400>,
<0xaf57000 0x400>,
<0xaf58000 0x400>,
<0xaf59000 0x400>,
<0xaf5a000 0x600>,
<0xaf5b000 0x600>;
interrupt-parent = <&mdss>;
interrupts = <12>;

2
Documentation/devicetree/bindings/display/msm/qcom,sm8750-mdss.yaml
View File

@@ -10,7 +10,7 @@ maintainers:
- Krzysztof Kozlowski <krzk@kernel.org>
description:
SM8650 MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like
SM8750 MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like
DPU display controller, DSI and DP interfaces etc.
$ref: /schemas/display/msm/mdss-common.yaml#

2
Documentation/devicetree/bindings/dma/arm-pl08x.yaml
View File

@@ -4,7 +4,7 @@
$id: http://devicetree.org/schemas/dma/arm-pl08x.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ARM PrimeCells PL080 and PL081 and derivatives DMA controller
title: ARM PrimeCell PL080 and PL081 and derivatives DMA controller
maintainers:
- Vinod Koul <vkoul@kernel.org>

4
Documentation/devicetree/bindings/dma/atmel,sama5d4-dma.yaml
View File

@@ -33,7 +33,9 @@ properties:
- microchip,sam9x7-dma
- const: atmel,sama5d4-dma
- items:
- const: microchip,sama7d65-dma
- enum:
- microchip,lan9691-dma
- microchip,sama7d65-dma
- const: microchip,sama7g5-dma
"#dma-cells":

20
Documentation/devicetree/bindings/dma/mediatek,uart-dma.yaml
View File

@@ -7,6 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek UART APDMA controller
maintainers:
- AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
- Long Cheng <long.cheng@mediatek.com>
description: |
@@ -23,11 +24,29 @@ properties:
- enum:
- mediatek,mt2712-uart-dma
- mediatek,mt6795-uart-dma
- mediatek,mt8173-uart-dma
- mediatek,mt8183-uart-dma
- mediatek,mt8365-uart-dma
- mediatek,mt8516-uart-dma
- const: mediatek,mt6577-uart-dma
- items:
- enum:
- mediatek,mt7988-uart-dma
- mediatek,mt8186-uart-dma
- mediatek,mt8188-uart-dma
- mediatek,mt8192-uart-dma
- mediatek,mt8195-uart-dma
- const: mediatek,mt6835-uart-dma
- items:
- enum:
- mediatek,mt6991-uart-dma
- mediatek,mt8196-uart-dma
- const: mediatek,mt6985-uart-dma
- enum:
- mediatek,mt6577-uart-dma
- mediatek,mt6795-uart-dma
- mediatek,mt6835-uart-dma
- mediatek,mt6985-uart-dma
reg:
minItems: 1
@@ -58,6 +77,7 @@ properties:
mediatek,dma-33bits:
type: boolean
deprecated: true
description: Enable 33-bits UART APDMA support
required:

4
Documentation/devicetree/bindings/dma/qcom,gpi.yaml
View File

@@ -24,6 +24,8 @@ properties:
- qcom,sm6350-gpi-dma
- items:
- enum:
- qcom,glymur-gpi-dma
- qcom,kaanapali-gpi-dma
- qcom,milos-gpi-dma
- qcom,qcm2290-gpi-dma
- qcom,qcs8300-gpi-dma
@@ -58,7 +60,7 @@ properties:
description:
Interrupt lines for each GPI instance
minItems: 1
maxItems: 13
maxItems: 16
"#dma-cells":
const: 3

1
Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
View File

@@ -24,6 +24,7 @@ properties:
- items:
- enum:
- renesas,r9a09g047-dmac # RZ/G3E
- renesas,r9a09g056-dmac # RZ/V2N
- const: renesas,r9a09g057-dmac
- const: renesas,r9a09g057-dmac # RZ/V2H(P)

14
Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
View File

@@ -17,11 +17,15 @@ allOf:
properties:
compatible:
enum:
- snps,axi-dma-1.01a
- intel,kmb-axi-dma
- starfive,jh7110-axi-dma
- starfive,jh8100-axi-dma
oneOf:
- enum:
- snps,axi-dma-1.01a
- intel,kmb-axi-dma
- starfive,jh7110-axi-dma
- starfive,jh8100-axi-dma
- items:
- const: altr,agilex5-axi-dma
- const: snps,axi-dma-1.01a
reg:
minItems: 1

4
Documentation/devicetree/bindings/eeprom/at24.yaml
View File

@@ -116,6 +116,7 @@ properties:
- const: atmel,24c02
- items:
- enum:
- belling,bl24c04a
- giantec,gt24c04a
- onnn,cat24c04
- onnn,cat24c05
@@ -124,6 +125,7 @@ properties:
- items:
- enum:
- belling,bl24c16a
- belling,bl24c16f
- renesas,r1ex24016
- const: atmel,24c16
- items:
@@ -132,6 +134,7 @@ properties:
- items:
- enum:
- belling,bl24s64
- giantec,gt24p64a
- onnn,n24s64b
- puya,p24c64f
- const: atmel,24c64
@@ -139,6 +142,7 @@ properties:
- enum:
- giantec,gt24p128e
- giantec,gt24p128f
- puya,p24c128f
- renesas,r1ex24128
- samsung,s524ad0xd1
- const: atmel,24c128

17
Documentation/devicetree/bindings/goldfish/events.txt
View File

@@ -1,17 +0,0 @@
Android Goldfish Events Keypad
Android goldfish events keypad device generated by android emulator.
Required properties:
- compatible : should contain "google,goldfish-events-keypad" to match emulator
- reg : <registers mapping>
- interrupts : <interrupt mapping>
Example:
goldfish-events@9040000 {
compatible = "google,goldfish-events-keypad";
reg = <0x9040000 0x1000>;
interrupts = <0x5>;
};

17
Documentation/devicetree/bindings/goldfish/pipe.txt
View File

@@ -1,17 +0,0 @@
Android Goldfish QEMU Pipe
Android pipe virtual device generated by android emulator.
Required properties:
- compatible : should contain "google,android-pipe" to match emulator
- reg : <registers mapping>
- interrupts : <interrupt mapping>
Example:
android_pipe@a010000 {
compatible = "google,android-pipe";
reg = <ff018000 0x2000>;
interrupts = <0x12>;
};

17
Documentation/devicetree/bindings/goldfish/tty.txt
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@@ -1,17 +0,0 @@
Android Goldfish TTY
Android goldfish tty device generated by android emulator.
Required properties:
- compatible : should contain "google,goldfish-tty" to match emulator
- reg : <registers mapping>
- interrupts : <interrupt mapping>
Example:
goldfish_tty@1f004000 {
compatible = "google,goldfish-tty";
reg = <0x1f004000 0x1000>;
interrupts = <0xc>;
};

1
Documentation/devicetree/bindings/hwmon/kontron,sl28cpld-hwmon.yaml
View File

@@ -16,7 +16,6 @@ description: |
properties:
compatible:
enum:
- kontron,sa67mcu-hwmon
- kontron,sl28cpld-fan
reg:

1
Documentation/devicetree/bindings/i2c/atmel,at91sam-i2c.yaml
View File

@@ -26,6 +26,7 @@ properties:
- microchip,sam9x60-i2c
- items:
- enum:
- microchip,lan9691-i2c
- microchip,sama7d65-i2c
- microchip,sama7g5-i2c
- microchip,sam9x7-i2c

1
Documentation/devicetree/bindings/i2c/i2c-mt65xx.yaml
View File

@@ -54,6 +54,7 @@ properties:
- enum:
- mediatek,mt6878-i2c
- mediatek,mt6991-i2c
- mediatek,mt8189-i2c
- mediatek,mt8196-i2c
- const: mediatek,mt8188-i2c
- items:

2
Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml
View File

@@ -28,6 +28,7 @@ properties:
- enum:
- qcom,kaanapali-cci
- qcom,qcm2290-cci
- qcom,qcs8300-cci
- qcom,sa8775p-cci
- qcom,sc7280-cci
- qcom,sc8280xp-cci
@@ -133,6 +134,7 @@ allOf:
enum:
- qcom,kaanapali-cci
- qcom,qcm2290-cci
- qcom,qcs8300-cci
- qcom,sm8750-cci
then:
properties:

100
Documentation/devicetree/bindings/i2c/silabs,cp2112.yaml Normal file
View File

@@ -0,0 +1,100 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/i2c/silabs,cp2112.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: CP2112 HID USB to SMBus/I2C Bridge
maintainers:
- Danny Kaehn <danny.kaehn@plexus.com>
description:
The CP2112 is a USB HID device which includes an integrated I2C controller
and 8 GPIO pins. Its GPIO pins can each be configured as inputs, open-drain
outputs, or push-pull outputs.
properties:
compatible:
const: usb10c4,ea90
reg:
maxItems: 1
description: The USB port number
interrupt-controller: true
"#interrupt-cells":
const: 2
gpio-controller: true
"#gpio-cells":
const: 2
gpio-line-names:
minItems: 1
maxItems: 8
i2c:
description: The SMBus/I2C controller node for the CP2112
$ref: /schemas/i2c/i2c-controller.yaml#
unevaluatedProperties: false
properties:
clock-frequency:
minimum: 10000
default: 100000
maximum: 400000
patternProperties:
"-hog(-[0-9]+)?$":
type: object
required:
- gpio-hog
required:
- compatible
- reg
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>
usb {
#address-cells = <1>;
#size-cells = <0>;
cp2112: device@1 {
compatible = "usb10c4,ea90";
reg = <1>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
#gpio-cells = <2>;
gpio-line-names = "CP2112_SDA", "CP2112_SCL", "TEST2",
"TEST3","TEST4", "TEST5", "TEST6";
fan-rst-hog {
gpio-hog;
gpios = <7 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "FAN_RST";
};
i2c {
#address-cells = <1>;
#size-cells = <0>;
sda-gpios = <&cp2112 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
scl-gpios = <&cp2112 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
temp@48 {
compatible = "national,lm75";
reg = <0x48>;
};
};
};
};

2
Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml
View File

@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Synopsys DesignWare APB I2C Controller
maintainers:
- Jarkko Nikula <jarkko.nikula@linux.intel.com>
- Mika Westerberg <mika.westerberg@linux.intel.com>
allOf:
- $ref: /schemas/i2c/i2c-controller.yaml#

3
Documentation/devicetree/bindings/i2c/spacemit,k1-i2c.yaml
View File

@@ -41,6 +41,9 @@ properties:
default: 400000
maximum: 3300000
resets:
maxItems: 1
required:
- compatible
- reg

120
Documentation/devicetree/bindings/iio/adc/adi,ad4062.yaml Normal file
View File

@@ -0,0 +1,120 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright 2025 Analog Devices Inc.
%YAML 1.2
---
$id: http://devicetree.org/schemas/iio/adc/adi,ad4062.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Analog Devices AD4062 ADC family device driver
maintainers:
- Jorge Marques <jorge.marques@analog.com>
description: |
Analog Devices AD4062 Single Channel Precision SAR ADC family
https://www.analog.com/media/en/technical-documentation/data-sheets/ad4060.pdf
https://www.analog.com/media/en/technical-documentation/data-sheets/ad4062.pdf
properties:
compatible:
enum:
- adi,ad4060
- adi,ad4062
reg:
maxItems: 1
interrupts:
description:
Two pins are available that can be configured as either a general purpose
digital output, device enable signal (used to synchronise other parts of
the signal chain with ADC sampling), device ready (GP1 only) or various
interrupt signals. If intended for use as a GPIO or device enable, will not
present here.
minItems: 1
items:
- description:
GP0 pin, cannot be configured as DEV_RDY.
- description:
GP1 pin, can be configured to any setting.
interrupt-names:
minItems: 1
items:
- const: gp0
- const: gp1
gpio-controller:
description:
Marks the device node as a GPIO controller. GPs not listed as interrupts
are exposed as a GPO.
'#gpio-cells':
const: 2
description:
The first cell is the GPIO number and the second cell specifies
GPIO flags, as defined in <dt-bindings/gpio/gpio.h>.
vdd-supply:
description: Analog power supply.
vio-supply:
description: Digital interface logic power supply.
ref-supply:
description:
Reference voltage to set the ADC full-scale range. If not present,
vdd-supply is used as the reference voltage.
required:
- compatible
- reg
- vdd-supply
- vio-supply
allOf:
- $ref: /schemas/i3c/i3c.yaml#
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
i3c {
#address-cells = <3>;
#size-cells = <0>;
adc@0,2ee007c0000 {
reg = <0x0 0x2ee 0x7c0000>;
vdd-supply = <&vdd>;
vio-supply = <&vio>;
ref-supply = <&ref>;
interrupt-parent = <&gpio>;
interrupts = <0 0 IRQ_TYPE_EDGE_RISING>,
<0 1 IRQ_TYPE_EDGE_FALLING>;
interrupt-names = "gp0", "gp1";
};
};
- |
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
i3c {
#address-cells = <3>;
#size-cells = <0>;
adc@0,2ee007c0000 {
reg = <0x0 0x2ee 0x7c0000>;
vdd-supply = <&vdd>;
vio-supply = <&vio>;
ref-supply = <&ref>;
gpio-controller;
#gpio-cells = <2>;
};
};

191
Documentation/devicetree/bindings/iio/adc/adi,ad4134.yaml Normal file
View File

@@ -0,0 +1,191 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/iio/adc/adi,ad4134.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Analog Devices AD4134 ADC
maintainers:
- Marcelo Schmitt <marcelo.schmitt@analog.com>
description: |
The AD4134 is a quad channel, low noise, simultaneous sampling, precision
analog-to-digital converter (ADC).
Specifications can be found at:
https://www.analog.com/media/en/technical-documentation/data-sheets/ad4134.pdf
$ref: /schemas/spi/spi-peripheral-props.yaml#
properties:
compatible:
enum:
- adi,ad4134
reg:
maxItems: 1
spi-max-frequency:
maximum: 50000000
avdd5-supply:
description: A 5V supply that powers the chip's analog circuitry.
dvdd5-supply:
description: A 5V supply that powers the chip's digital circuitry.
iovdd-supply:
description:
A 1.8V supply that sets the logic levels for the digital interface pins.
refin-supply:
description:
A 4.096V or 5V supply that serves as reference for ADC conversions.
avdd1v8-supply:
description: A 1.8V supply used by the analog circuitry.
dvdd1v8-supply:
description: A 1.8V supply used by the digital circuitry.
clkvdd-supply:
description: A 1.8V supply for the chip's clock management circuit.
ldoin-supply:
description:
A 2.6V to 5.5V supply that generates 1.8V for AVDD1V8, DVDD1V8, and CLKVDD
pins.
clocks:
maxItems: 1
description:
Required external clock source. Can specify either a crystal or CMOS clock
source. If an external crystal is set, connect the CLKSEL pin to IOVDD.
Otherwise, connect the CLKSEL pin to IOGND and the external CMOS clock
signal to the XTAL2/CLKIN pin.
clock-names:
enum:
- xtal
- clkin
default: clkin
'#clock-cells':
const: 0
clock-output-names:
maxItems: 1
regulators:
type: object
description:
list of regulators provided by this controller.
properties:
vcm-output:
$ref: /schemas/regulator/regulator.yaml#
type: object
unevaluatedProperties: false
additionalProperties: false
reset-gpios:
maxItems: 1
powerdown-gpios:
description:
Active low GPIO connected to the /PDN pin. Forces the device into full
power-down mode when brought low. Pull this input to IOVDD for normal
operation.
maxItems: 1
odr-gpios:
description:
GPIO connected to ODR pin. Used to sample ADC data in minimum I/O mode.
maxItems: 1
adi,asrc-mode:
$ref: /schemas/types.yaml#/definitions/string
description:
Asynchronous Sample Rate Converter (ASRC) operation mode control input.
Describes whether the MODE pin is set to a high level (for master mode
operation) or to a low level (for slave mode operation).
enum: [ high, low ]
default: low
adi,dclkio:
description:
DCLK pin I/O direction control for when the device operates in Pin Control
Slave Mode or in SPI Control Mode. Describes if DEC0/DCLKIO pin is at a
high level (which configures DCLK as an output) or to set to a low level
(configuring DCLK for input).
enum: [ out, in ]
default: in
adi,dclkmode:
description:
DCLK mode control for when the device operates in Pin Control Slave Mode
or in SPI Control Mode. Describes whether the DEC1/DCLKMODE pin is set to
a high level (configuring the DCLK to operate in free running mode) or
to a low level (to configure DCLK to operate in gated mode).
enum: [ free-running, gated ]
default: gated
required:
- compatible
- reg
- avdd5-supply
- dvdd5-supply
- iovdd-supply
- refin-supply
- clocks
- clock-names
oneOf:
- required:
- ldoin-supply
- required:
- avdd1v8-supply
- dvdd1v8-supply
- clkvdd-supply
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
spi {
#address-cells = <1>;
#size-cells = <0>;
adc@0 {
compatible = "adi,ad4134";
reg = <0>;
spi-max-frequency = <1000000>;
reset-gpios = <&gpio0 86 GPIO_ACTIVE_LOW>;
odr-gpios = <&gpio0 87 GPIO_ACTIVE_HIGH>;
powerdown-gpios = <&gpio0 88 GPIO_ACTIVE_LOW>;
clocks = <&sys_clk>;
clock-names = "clkin";
avdd5-supply = <&avdd5>;
dvdd5-supply = <&dvdd5>;
iovdd-supply = <&iovdd>;
refin-supply = <&refin>;
avdd1v8-supply = <&avdd1v8>;
dvdd1v8-supply = <&dvdd1v8>;
clkvdd-supply = <&clkvdd>;
regulators {
vcm_reg: vcm-output {
regulator-name = "ad4134-vcm";
};
};
};
};
...

64
Documentation/devicetree/bindings/iio/adc/adi,ad7768-1.yaml
View File

@@ -4,18 +4,26 @@
$id: http://devicetree.org/schemas/iio/adc/adi,ad7768-1.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Analog Devices AD7768-1 ADC device driver
title: Analog Devices AD7768-1 ADC family
maintainers:
- Michael Hennerich <michael.hennerich@analog.com>
description: |
Datasheet at:
https://www.analog.com/media/en/technical-documentation/data-sheets/ad7768-1.pdf
Analog Devices AD7768-1 24-Bit Single Channel Low Power sigma-delta ADC family
https://www.analog.com/media/en/technical-documentation/data-sheets/ad7768-1.pdf
https://www.analog.com/media/en/technical-documentation/data-sheets/adaq7767-1.pdf
https://www.analog.com/media/en/technical-documentation/data-sheets/adaq7768-1.pdf
https://www.analog.com/media/en/technical-documentation/data-sheets/adaq7769-1.pdf
properties:
compatible:
const: adi,ad7768-1
enum:
- adi,ad7768-1
- adi,adaq7767-1
- adi,adaq7768-1
- adi,adaq7769-1
reg:
maxItems: 1
@@ -58,6 +66,25 @@ properties:
description:
ADC reference voltage supply
adi,aaf-gain-bp:
description: |
Specifies the gain applied by the Analog Anti-Aliasing Filter (AAF)
to the ADC input in basis points (one hundredth of a percent).
The hardware gain is determined by which input pin(s) the signal goes
through into the AAF. The possible connections are:
* For the ADAQ7767-1: Input connected to IN1±, IN2± or IN3±.
* For the ADAQ7769-1: OUT_PGA pin connected to IN1_AAF+, IN2_AAF+,
or IN3_AAF+.
enum: [1430, 3640, 10000]
default: 10000
pga-gpios:
description:
GAIN 0, GAIN1 and GAIN2 pins for gain selection. For devices that have
PGA configuration input pins, pga-gpios must be defined.
minItems: 3
maxItems: 3
adi,sync-in-gpios:
maxItems: 1
description:
@@ -147,6 +174,35 @@ patternProperties:
allOf:
- $ref: /schemas/spi/spi-peripheral-props.yaml#
# AAF Gain property only applies to ADAQ7767-1 and ADAQ7769-1 devices
- if:
properties:
compatible:
contains:
enum:
- adi,adaq7767-1
- adi,adaq7769-1
then:
required:
- adi,aaf-gain-bp
else:
properties:
adi,aaf-gain-bp: false
- if:
properties:
compatible:
contains:
enum:
- adi,adaq7768-1
- adi,adaq7769-1
then:
required:
- pga-gpios
else:
properties:
pga-gpios: false
unevaluatedProperties: false
examples:

2
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@@ -18,6 +18,7 @@ description: |
All the parts support the register map described by Application Note AN-877
https://www.analog.com/media/en/technical-documentation/application-notes/AN-877.pdf
https://www.analog.com/media/en/technical-documentation/data-sheets/AD9211.pdf
https://www.analog.com/media/en/technical-documentation/data-sheets/AD9265.pdf
https://www.analog.com/media/en/technical-documentation/data-sheets/AD9434.pdf
https://www.analog.com/media/en/technical-documentation/data-sheets/AD9467.pdf
@@ -25,6 +26,7 @@ description: |
properties:
compatible:
enum:
- adi,ad9211
- adi,ad9265
- adi,ad9434
- adi,ad9467

3
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@@ -44,6 +44,9 @@ properties:
Input clock used to derive the sample clock. Expected to be the
SoC's APB clock.
interrupts:
maxItems: 1
resets:
maxItems: 1

63
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@@ -0,0 +1,63 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/iio/adc/nxp,s32g2-sar-adc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NXP Successive Approximation ADC
description:
The NXP SAR ADC provides fast and accurate analog-to-digital
conversion using the Successive Approximation Register (SAR) method.
It has 12-bit resolution with 8 input channels. Conversions can be
launched in software or using hardware triggers. It supports
continuous and one-shot modes with separate registers.
maintainers:
- Daniel Lezcano <daniel.lezcano@kernel.org>
properties:
compatible:
oneOf:
- const: nxp,s32g2-sar-adc
- items:
- const: nxp,s32g3-sar-adc
- const: nxp,s32g2-sar-adc
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
maxItems: 1
dmas:
maxItems: 1
dma-names:
const: rx
required:
- compatible
- reg
- interrupts
- clocks
- dmas
- dma-names
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
adc@401f8000 {
compatible = "nxp,s32g2-sar-adc";
reg = <0x401f8000 0x1000>;
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks 0x41>;
dmas = <&edma0 0 32>;
dma-names = "rx";
};

82
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@@ -0,0 +1,82 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/iio/adc/ti,ads1018.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: TI ADS1018/ADS1118 SPI analog to digital converter
maintainers:
- Kurt Borja <kuurtb@gmail.com>
description: |
The ADS1018/ADS1118 is a precision, low-power, 12-bit/16-bit, analog to
digital converter (ADC). It integrates a programmable gain amplifier (PGA),
internal voltage reference, oscillator and high-accuracy temperature sensor.
Datasheets:
- ADS1018: https://www.ti.com/lit/ds/symlink/ads1018.pdf
- ADS1118: https://www.ti.com/lit/ds/symlink/ads1118.pdf
properties:
compatible:
enum:
- ti,ads1018
- ti,ads1118
reg:
maxItems: 1
vdd-supply: true
spi-max-frequency:
maximum: 4000000
spi-cpha: true
interrupts:
description: DOUT/DRDY (Data Out/Data Ready) line.
maxItems: 1
drdy-gpios:
description:
Extra GPIO line connected to DOUT/DRDY (Data Out/Data Ready). This allows
distinguishing between interrupts triggered by the data-ready signal and
interrupts triggered by an SPI transfer.
maxItems: 1
'#io-channel-cells':
const: 1
required:
- compatible
- reg
- vdd-supply
allOf:
- $ref: /schemas/spi/spi-peripheral-props.yaml#
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>
spi {
#address-cells = <1>;
#size-cells = <0>;
adc@0 {
compatible = "ti,ads1118";
reg = <0>;
spi-max-frequency = <4000000>;
spi-cpha;
vdd-supply = <&vdd_3v3_reg>;
interrupts-extended = <&gpio 14 IRQ_TYPE_EDGE_FALLING>;
drdy-gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
};
};

208
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@@ -0,0 +1,208 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/iio/adc/ti,ads131m02.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Texas Instruments ADS131M0x 2-, 3-, 4-, 6- and 8-Channel ADCs
maintainers:
- Oleksij Rempel <o.rempel@pengutronix.de>
description: |
The ADS131M0x are a family of multichannel, simultaneous sampling,
24-bit, delta-sigma, analog-to-digital converters (ADCs) with a
built-in programmable gain amplifier (PGA) and internal reference.
Communication with the ADC chip is via SPI.
Datasheets:
- ADS131M02: https://www.ti.com/lit/ds/symlink/ads131m02.pdf
- ADS131M03: https://www.ti.com/lit/ds/symlink/ads131m03.pdf
- ADS131M04: https://www.ti.com/lit/ds/symlink/ads131m04.pdf
- ADS131M06: https://www.ti.com/lit/ds/symlink/ads131m06.pdf
- ADS131M08: https://www.ti.com/lit/ds/symlink/ads131m08.pdf
properties:
compatible:
enum:
- ti,ads131m02
- ti,ads131m03
- ti,ads131m04
- ti,ads131m06
- ti,ads131m08
reg:
description: SPI chip select number.
clocks:
description:
Phandle to the external clock source required by the ADC's CLKIN pin.
The datasheet recommends specific frequencies based on the desired power
mode (e.g., 8.192 MHz for High-Resolution mode).
maxItems: 1
avdd-supply:
description: Analog power supply (AVDD).
dvdd-supply:
description: Digital power supply (DVDD).
interrupts:
description: DRDY (Data Ready) output signal.
maxItems: 1
reset-gpios:
description: Optional RESET signal.
maxItems: 1
clock-names:
description:
Indicates if a crystal oscillator (XTAL) or CMOS signal is connected
(CLKIN). Note that XTAL mode is only supported on ADS131M06 and ADS131M08.
enum: [xtal, clkin]
refin-supply:
description: Optional external reference supply (REFIN).
'#address-cells':
const: 1
'#size-cells':
const: 0
required:
- compatible
- reg
- clocks
- clock-names
- avdd-supply
- dvdd-supply
patternProperties:
"^channel@[0-7]$":
type: object
$ref: /schemas/iio/adc/adc.yaml#
description: Properties for a single ADC channel.
properties:
reg:
description: The channel index (0-7).
minimum: 0
maximum: 7 # Max channels on ADS131M08
label: true
required:
- reg
unevaluatedProperties: false
allOf:
- $ref: /schemas/spi/spi-peripheral-props.yaml#
- if:
# 20-pin devices: M02, M03, M04
# These do not support XTAL or REFIN.
properties:
compatible:
enum:
- ti,ads131m02
- ti,ads131m03
- ti,ads131m04
then:
properties:
clock-names:
const: clkin
refin-supply: false
- if:
# ADS131M02: 2 channels max (0-1)
properties:
compatible:
contains:
const: ti,ads131m02
then:
patternProperties:
"^channel@[0-1]$":
properties:
reg:
maximum: 1
"^channel@[2-7]$": false
- if:
# ADS131M03: 3 channels max (0-2)
properties:
compatible:
contains:
const: ti,ads131m03
then:
patternProperties:
"^channel@[0-2]$":
properties:
reg:
maximum: 2
"^channel@[3-7]$": false
- if:
# ADS131M04: 4 channels max (0-3)
properties:
compatible:
contains:
const: ti,ads131m04
then:
patternProperties:
"^channel@[0-3]$":
properties:
reg:
maximum: 3
"^channel@[4-7]$": false
- if:
# ADS131M06: 6 channels max (0-5)
properties:
compatible:
contains:
const: ti,ads131m06
then:
patternProperties:
"^channel@[0-5]$":
properties:
reg:
maximum: 5
"^channel@[6-7]$": false
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/stm32mp1-clks.h>
spi1 {
#address-cells = <1>;
#size-cells = <0>;
adc@0 {
compatible = "ti,ads131m02";
reg = <0>;
spi-max-frequency = <8000000>;
clocks = <&rcc CK_MCO2>;
clock-names = "clkin";
avdd-supply = <&vdd_ana>;
dvdd-supply = <&vdd_dig>;
#address-cells = <1>;
#size-cells = <0>;
channel@0 {
reg = <0>;
label = "input_voltage";
};
channel@1 {
reg = <1>;
label = "input_current";
};
};
};

87
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@@ -0,0 +1,87 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/iio/amplifiers/adi,adl8113.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Analog Devices ADL8113 Low Noise Amplifier with integrated bypass switches
maintainers:
- Antoniu Miclaus <antoniu.miclaus@analog.com>
description: |
The ADL8113 is a 10MHz to 12GHz Low Noise Amplifier with integrated bypass
switches controlled by two GPIO pins (VA and VB). The device supports four
operation modes:
- Internal Amplifier: VA=0, VB=0 - Signal passes through the internal LNA
- Internal Bypass: VA=1, VB=1 - Signal bypasses through internal path
- External Bypass A: VA=0, VB=1 - Signal routes from RFIN to OUT_A and from IN_A to RFOUT
- External Bypass B: VA=1, VB=0 - Signal routes from RFIN to OUT_B and from IN_B to RFOUT
https://www.analog.com/en/products/adl8113.html
properties:
compatible:
const: adi,adl8113
vdd1-supply: true
vdd2-supply: true
vss2-supply: true
ctrl-gpios:
items:
- description: VA control pin
- description: VB control pin
adi,external-bypass-a-gain-db:
description:
Gain in dB of external amplifier connected to bypass path A (OUT_A/IN_A).
When specified, this gain value becomes selectable via the hardwaregain
attribute and automatically routes through the external A path.
adi,external-bypass-b-gain-db:
description:
Gain in dB of external amplifier connected to bypass path B (OUT_B/IN_B).
When specified, this gain value becomes selectable via the hardwaregain
attribute and automatically routes through the external B path.
required:
- compatible
- ctrl-gpios
- vdd1-supply
- vdd2-supply
- vss2-supply
additionalProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
/* Basic configuration with only internal paths */
amplifier {
compatible = "adi,adl8113";
ctrl-gpios = <&gpio 22 GPIO_ACTIVE_HIGH>,
<&gpio 23 GPIO_ACTIVE_HIGH>;
vdd1-supply = <&vdd1_5v>;
vdd2-supply = <&vdd2_3v3>;
vss2-supply = <&vss2_neg>;
};
- |
#include <dt-bindings/gpio/gpio.h>
/* Configuration with external bypass amplifiers */
amplifier {
compatible = "adi,adl8113";
ctrl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>,
<&gpio 25 GPIO_ACTIVE_HIGH>;
vdd1-supply = <&vdd1_5v>;
vdd2-supply = <&vdd2_3v3>;
vss2-supply = <&vss2_neg>;
adi,external-bypass-a-gain-db = <20>; /* 20dB external amp on path A */
adi,external-bypass-b-gain-db = <6>; /* 6dB external amp on path B */
};
...

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/iio/dac/adi,max22007.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Analog Devices MAX22007 DAC
maintainers:
- Janani Sunil <janani.sunil@analog.com>
description:
The MAX22007 is a quad-channel, 12-bit digital-to-analog converter (DAC)
with integrated precision output amplifiers and current output capability.
Each channel can be independently configured for voltage or current output.
Datasheet available at https://www.analog.com/en/products/max22007.html
$ref: /schemas/spi/spi-peripheral-props.yaml#
properties:
compatible:
const: adi,max22007
reg:
maxItems: 1
spi-max-frequency:
maximum: 500000
'#address-cells':
const: 1
'#size-cells':
const: 0
vdd-supply:
description: Low-Voltage Power Supply from +2.7V to +5.5V.
hvdd-supply:
description:
Positive High-Voltage Power Supply from +8V to (HVSS +24V) for
the Output Channels.
hvss-supply:
description:
Optional Negative High-Voltage Power Supply from -2V to 0V for the Output
Channels. For most applications HVSS can be connected to GND (0V), but for
applications requiring output down to true 0V or 0mA, connect to a -2V supply.
reset-gpios:
maxItems: 1
description:
Active low GPIO.
patternProperties:
"^channel@[0-3]$":
$ref: /schemas/iio/dac/dac.yaml#
type: object
description:
Represents the external channels which are connected to the DAC.
properties:
reg:
description: Channel number
items:
minimum: 0
maximum: 3
adi,ch-func:
description:
Channel output type. Use CH_FUNC_VOLTAGE_OUTPUT for voltage
output or CH_FUNC_CURRENT_OUTPUT for current output.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [1, 2]
required:
- reg
- adi,ch-func
unevaluatedProperties: false
required:
- compatible
- reg
- vdd-supply
- hvdd-supply
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/iio/addac/adi,ad74413r.h>
spi {
#address-cells = <1>;
#size-cells = <0>;
dac@0 {
compatible = "adi,max22007";
reg = <0>;
spi-max-frequency = <500000>;
reset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
vdd-supply = <&vdd_reg>;
hvdd-supply = <&hvdd_reg>;
#address-cells = <1>;
#size-cells = <0>;
channel@0 {
reg = <0>;
adi,ch-func = <CH_FUNC_VOLTAGE_OUTPUT>;
};
channel@1 {
reg = <1>;
adi,ch-func = <CH_FUNC_CURRENT_OUTPUT>;
};
};
};
...

302
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/iio/dac/microchip,mcp47feb02.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Microchip MCP47F(E/V)B(0/1/2)(1/2/4/8) DAC with I2C Interface Families
maintainers:
- Ariana Lazar <ariana.lazar@microchip.com>
description: |
Datasheet for MCP47FEB01, MCP47FEB11, MCP47FEB21, MCP47FEB02, MCP47FEB12,
MCP47FEB22 can be found here:
https://ww1.microchip.com/downloads/aemDocuments/documents/OTH/ProductDocuments/DataSheets/20005375A.pdf
Datasheet for MCP47FVB01, MCP47FVB11, MCP47FVB21, MCP47FVB02, MCP47FVB12,
MCP47FVB22 can be found here:
https://ww1.microchip.com/downloads/aemDocuments/documents/OTH/ProductDocuments/DataSheets/20005405A.pdf
Datasheet for MCP47FEB04, MCP47FEB14, MCP47FEB24, MCP47FEB08, MCP47FEB18,
MCP47FEB28, MCP47FVB04, MCP47FVB14, MCP47FVB24, MCP47FVB08, MCP47FVB18,
MCP47FVB28 can be found here:
https://ww1.microchip.com/downloads/aemDocuments/documents/MSLD/ProductDocuments/DataSheets/MCP47FXBX48-Data-Sheet-DS200006368A.pdf
+------------+--------------+-------------+-------------+------------+
| Device | Resolution | Channels | Vref number | Memory |
|------------|--------------|-------------|-------------|------------|
| MCP47FEB01 | 8-bit | 1 | 1 | EEPROM |
| MCP47FEB11 | 10-bit | 1 | 1 | EEPROM |
| MCP47FEB21 | 12-bit | 1 | 1 | EEPROM |
|------------|--------------|-------------|-------------|------------|
| MCP47FEB02 | 8-bit | 2 | 1 | EEPROM |
| MCP47FEB12 | 10-bit | 2 | 1 | EEPROM |
| MCP47FEB22 | 12-bit | 2 | 1 | EEPROM |
|------------|--------------|-------------|-------------|------------|
| MCP47FVB01 | 8-bit | 1 | 1 | RAM |
| MCP47FVB11 | 10-bit | 1 | 1 | RAM |
| MCP47FVB21 | 12-bit | 1 | 1 | RAM |
|------------|--------------|-------------|-------------|------------|
| MCP47FVB02 | 8-bit | 2 | 1 | RAM |
| MCP47FVB12 | 10-bit | 2 | 1 | RAM |
| MCP47FVB22 | 12-bit | 2 | 1 | RAM |
|------------|--------------|-------------|-------------|------------|
| MCP47FVB04 | 8-bit | 4 | 2 | RAM |
| MCP47FVB14 | 10-bit | 4 | 2 | RAM |
| MCP47FVB24 | 12-bit | 4 | 2 | RAM |
|------------|--------------|-------------|-------------|------------|
| MCP47FVB08 | 8-bit | 8 | 2 | RAM |
| MCP47FVB18 | 10-bit | 8 | 2 | RAM |
| MCP47FVB28 | 12-bit | 8 | 2 | RAM |
|------------|--------------|-------------|-------------|------------|
| MCP47FEB04 | 8-bit | 4 | 2 | EEPROM |
| MCP47FEB14 | 10-bit | 4 | 2 | EEPROM |
| MCP47FEB24 | 12-bit | 4 | 2 | EEPROM |
|------------|--------------|-------------|-------------|------------|
| MCP47FEB08 | 8-bit | 8 | 2 | EEPROM |
| MCP47FEB18 | 10-bit | 8 | 2 | EEPROM |
| MCP47FEB28 | 12-bit | 8 | 2 | EEPROM |
+------------+--------------+-------------+-------------+------------+
properties:
compatible:
enum:
- microchip,mcp47feb01
- microchip,mcp47feb11
- microchip,mcp47feb21
- microchip,mcp47feb02
- microchip,mcp47feb12
- microchip,mcp47feb22
- microchip,mcp47fvb01
- microchip,mcp47fvb11
- microchip,mcp47fvb21
- microchip,mcp47fvb02
- microchip,mcp47fvb12
- microchip,mcp47fvb22
- microchip,mcp47fvb04
- microchip,mcp47fvb14
- microchip,mcp47fvb24
- microchip,mcp47fvb08
- microchip,mcp47fvb18
- microchip,mcp47fvb28
- microchip,mcp47feb04
- microchip,mcp47feb14
- microchip,mcp47feb24
- microchip,mcp47feb08
- microchip,mcp47feb18
- microchip,mcp47feb28
reg:
maxItems: 1
"#address-cells":
const: 1
"#size-cells":
const: 0
vdd-supply:
description:
Provides power to the chip and it could be used as reference voltage. The
voltage is used to calculate scale. For parts without EEPROM at powerup
this will be the selected as voltage reference.
vref-supply:
description: |
Vref pin (it could be found as Vref0 into the datasheet) may be used as a
voltage reference when this supply is specified. The internal reference
will be taken into account for voltage reference besides VDD if this supply
does not exist.
This supply will be voltage reference for the following outputs:
- for single-channel device: Vout0;
- for dual-channel device: Vout0, Vout1;
- for quad-channel device: Vout0, Vout2;
- for octal-channel device: Vout0, Vout2, Vout6, Vout8;
vref1-supply:
description: |
Vref1 pin may be used as a voltage reference when this supply is specified.
The internal reference will be taken into account for voltage reference
beside VDD if this supply does not exist.
This supply will be voltage reference for the following outputs:
- for quad-channel device: Vout1, Vout3;
- for octal-channel device: Vout1, Vout3, Vout5, Vout7;
lat-gpios:
description:
LAT pin to be used as a hardware trigger to synchronously update the DAC
channels. The pin is active Low. It could be also found as LAT0 in
datasheet.
maxItems: 1
lat1-gpios:
description:
LAT1 pin to be used as a hardware trigger to synchronously update the odd
DAC channels on devices with 4 and 8 channels. The pin is active Low.
maxItems: 1
microchip,vref-buffered:
type: boolean
description:
Enable buffering of the external Vref/Vref0 pin in cases where the
external reference voltage does not have sufficient current capability in
order not to drop it’s voltage when connected to the internal resistor
ladder circuit.
microchip,vref1-buffered:
type: boolean
description:
Enable buffering of the external Vref1 pin in cases where the external
reference voltage does not have sufficient current capability in order not
to drop it’s voltage when connected to the internal resistor ladder
circuit.
patternProperties:
"^channel@[0-7]$":
$ref: dac.yaml
type: object
description: Voltage output channel.
properties:
reg:
description: The channel number.
minItems: 1
maxItems: 8
label:
description: Unique name to identify which channel this is.
required:
- reg
unevaluatedProperties: false
required:
- compatible
- reg
- vdd-supply
allOf:
- if:
properties:
compatible:
contains:
enum:
- microchip,mcp47feb01
- microchip,mcp47feb11
- microchip,mcp47feb21
- microchip,mcp47fvb01
- microchip,mcp47fvb11
- microchip,mcp47fvb21
then:
properties:
lat1-gpios: false
vref1-supply: false
microchip,vref1-buffered: false
channel@0:
properties:
reg:
const: 0
patternProperties:
"^channel@[1-7]$": false
- if:
properties:
compatible:
contains:
enum:
- microchip,mcp47feb02
- microchip,mcp47feb12
- microchip,mcp47feb22
- microchip,mcp47fvb02
- microchip,mcp47fvb12
- microchip,mcp47fvb22
then:
properties:
lat1-gpios: false
vref1-supply: false
microchip,vref1-buffered: false
patternProperties:
"^channel@[0-1]$":
properties:
reg:
enum: [0, 1]
"^channel@[2-7]$": false
- if:
properties:
compatible:
contains:
enum:
- microchip,mcp47fvb04
- microchip,mcp47fvb14
- microchip,mcp47fvb24
- microchip,mcp47feb04
- microchip,mcp47feb14
- microchip,mcp47feb24
then:
patternProperties:
"^channel@[0-3]$":
properties:
reg:
enum: [0, 1, 2, 3]
"^channel@[4-7]$": false
- if:
properties:
compatible:
contains:
enum:
- microchip,mcp47fvb08
- microchip,mcp47fvb18
- microchip,mcp47fvb28
- microchip,mcp47feb08
- microchip,mcp47feb18
- microchip,mcp47feb28
then:
patternProperties:
"^channel@[0-7]$":
properties:
reg:
enum: [0, 1, 2, 3, 4, 5, 6, 7]
- if:
not:
required:
- vref-supply
then:
properties:
microchip,vref-buffered: false
- if:
not:
required:
- vref1-supply
then:
properties:
microchip,vref1-buffered: false
additionalProperties: false
examples:
- |
i2c {
#address-cells = <1>;
#size-cells = <0>;
dac@0 {
compatible = "microchip,mcp47feb02";
reg = <0>;
vdd-supply = <&vdac_vdd>;
vref-supply = <&vref_reg>;
#address-cells = <1>;
#size-cells = <0>;
channel@0 {
reg = <0>;
label = "Adjustable_voltage_ch0";
};
channel@1 {
reg = <0x1>;
label = "Adjustable_voltage_ch1";
};
};
};
...

8
Documentation/devicetree/bindings/iio/frequency/adi,adf4377.yaml
View File

@@ -40,6 +40,12 @@ properties:
items:
- const: ref_in
'#clock-cells':
const: 0
clock-output-names:
maxItems: 1
chip-enable-gpios:
description:
GPIO that controls the Chip Enable Pin.
@@ -97,6 +103,8 @@ examples:
spi-max-frequency = <10000000>;
clocks = <&adf4377_ref_in>;
clock-names = "ref_in";
#clock-cells = <0>;
clock-output-names = "adf4377";
};
};
...

132
Documentation/devicetree/bindings/iio/pressure/honeywell,abp2030pa.yaml Normal file
View File

@@ -0,0 +1,132 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/iio/pressure/honeywell,abp2030pa.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Honeywell abp2030pa pressure sensor
maintainers:
- Petre Rodan <petre.rodan@subdimension.ro>
description: |
Honeywell pressure sensor of model abp2030pa.
This sensor has an I2C and SPI interface.
There are many models with different pressure ranges available. The vendor
calls them "ABP2 series". All of them have an identical programming model and
differ in the pressure range and measurement unit.
To support different models one needs to specify its pressure triplet.
For custom silicon chips not covered by the Honeywell ABP2 series datasheet,
the pressure values can be specified manually via honeywell,pmin-pascal and
honeywell,pmax-pascal.
Specifications about the devices can be found at:
https://prod-edam.honeywell.com/content/dam/honeywell-edam/sps/siot/en-us/products/sensors/pressure-sensors/board-mount-pressure-sensors/basic-abp2-series/documents/sps-siot-abp2-series-datasheet-32350268-en.pdf
properties:
compatible:
const: honeywell,abp2030pa
reg:
maxItems: 1
interrupts:
description:
Optional interrupt for indicating end of conversion.
SPI variants of ABP2 chips do not provide this feature.
maxItems: 1
honeywell,pressure-triplet:
description: |
Case-sensitive five character string that defines pressure range, unit
and type as part of the device nomenclature. In the unlikely case of a
custom chip, unset and provide pmin-pascal and pmax-pascal instead.
enum: [001BA, 1.6BA, 2.5BA, 004BA, 006BA, 008BA, 010BA, 012BA, 001BD,
1.6BD, 2.5BD, 004BD, 001BG, 1.6BG, 2.5BG, 004BG, 006BG, 008BG,
010BG, 012BG, 001GG, 1.2GG, 100KA, 160KA, 250KA, 001KD, 1.6KD,
2.5KD, 004KD, 006KD, 010KD, 016KD, 025KD, 040KD, 060KD, 100KD,
160KD, 250KD, 400KD, 001KG, 1.6KG, 2.5KG, 004KG, 006KG, 010KG,
016KG, 025KG, 040KG, 060KG, 100KG, 160KG, 250KG, 400KG, 600KG,
800KG, 250LD, 600LD, 600LG, 2.5MD, 006MD, 010MD, 016MD, 025MD,
040MD, 060MD, 100MD, 160MD, 250MD, 400MD, 600MD, 006MG, 010MG,
016MG, 025MG, 040MG, 060MG, 100MG, 160MG, 250MG, 400MG, 600MG,
001ND, 002ND, 004ND, 005ND, 010ND, 020ND, 030ND, 002NG, 004NG,
005NG, 010NG, 020NG, 030NG, 015PA, 030PA, 060PA, 100PA, 150PA,
175PA, 001PD, 005PD, 015PD, 030PD, 060PD, 001PG, 005PG, 015PG,
030PG, 060PG, 100PG, 150PG, 175PG]
$ref: /schemas/types.yaml#/definitions/string
honeywell,pmin-pascal:
description:
Minimum pressure value the sensor can measure in pascal.
honeywell,pmax-pascal:
description:
Maximum pressure value the sensor can measure in pascal.
spi-max-frequency:
maximum: 800000
vdd-supply: true
required:
- compatible
- reg
- vdd-supply
oneOf:
- required:
- honeywell,pressure-triplet
- required:
- honeywell,pmin-pascal
- honeywell,pmax-pascal
allOf:
- $ref: /schemas/spi/spi-peripheral-props.yaml
- if:
required:
- honeywell,pressure-triplet
then:
properties:
honeywell,pmin-pascal: false
honeywell,pmax-pascal: false
additionalProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
i2c {
#address-cells = <1>;
#size-cells = <0>;
pressure@18 {
compatible = "honeywell,abp2030pa";
reg = <0x18>;
interrupt-parent = <&gpio3>;
interrupts = <21 IRQ_TYPE_EDGE_RISING>;
honeywell,pressure-triplet = "001BA";
vdd-supply = <&vcc_3v3>;
};
};
- |
spi {
#address-cells = <1>;
#size-cells = <0>;
pressure@0 {
compatible = "honeywell,abp2030pa";
reg = <0>;
spi-max-frequency = <800000>;
honeywell,pressure-triplet = "001PD";
vdd-supply = <&vcc_3v3>;
};
};
...

53
Documentation/devicetree/bindings/iio/proximity/rfdigital,rfd77402.yaml Normal file
View File

@@ -0,0 +1,53 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/iio/proximity/rfdigital,rfd77402.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: RF Digital RFD77402 ToF sensor
maintainers:
- Shrikant Raskar <raskar.shree97@gmail.com>
description:
The RF Digital RFD77402 is a Time-of-Flight (ToF) proximity and distance
sensor providing up to 200 mm range measurement over an I2C interface.
properties:
compatible:
const: rfdigital,rfd77402
reg:
maxItems: 1
interrupts:
maxItems: 1
description:
Interrupt asserted when a new distance measurement is available.
vdd-supply:
description: Regulator that provides power to the sensor.
required:
- compatible
- reg
- vdd-supply
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
i2c {
#address-cells = <1>;
#size-cells = <0>;
proximity@4c {
compatible = "rfdigital,rfd77402";
reg = <0x4c>;
vdd-supply = <&vdd_3v3>;
interrupt-parent = <&gpio>;
interrupts = <4 IRQ_TYPE_EDGE_FALLING>;
};
};
...

66
Documentation/devicetree/bindings/input/focaltech,ft8112.yaml Normal file
View File

@@ -0,0 +1,66 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/input/focaltech,ft8112.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: FocalTech FT8112 touchscreen controller
maintainers:
- Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com>
description:
Supports the FocalTech FT8112 touchscreen controller.
This touchscreen controller uses the i2c-hid protocol with a reset GPIO.
allOf:
- $ref: /schemas/input/touchscreen/touchscreen.yaml#
properties:
compatible:
enum:
- focaltech,ft8112
reg:
maxItems: 1
interrupts:
maxItems: 1
panel: true
reset-gpios:
maxItems: 1
vcc33-supply: true
vccio-supply: true
required:
- compatible
- reg
- interrupts
- vcc33-supply
additionalProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
i2c {
#address-cells = <1>;
#size-cells = <0>;
touchscreen@38 {
compatible = "focaltech,ft8112";
reg = <0x38>;
interrupt-parent = <&pio>;
interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&pio 126 GPIO_ACTIVE_LOW>;
vcc33-supply = <&pp3300_tchscr_x>;
};
};

41
Documentation/devicetree/bindings/input/google,goldfish-events-keypad.yaml Normal file
View File

@@ -0,0 +1,41 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/input/google,goldfish-events-keypad.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Android Goldfish Events Keypad
maintainers:
- Kuan-Wei Chiu <visitorckw@gmail.com>
allOf:
- $ref: input.yaml#
description:
Android goldfish events keypad device generated by android emulator.
properties:
compatible:
const: google,goldfish-events-keypad
reg:
maxItems: 1
interrupts:
maxItems: 1
required:
- compatible
- reg
- interrupts
unevaluatedProperties: false
examples:
- |
keypad@9040000 {
compatible = "google,goldfish-events-keypad";
reg = <0x9040000 0x1000>;
interrupts = <5>;
};

17
Documentation/devicetree/bindings/input/qcom,pm8941-pwrkey.yaml
View File

@@ -12,11 +12,18 @@ maintainers:
properties:
compatible:
enum:
- qcom,pm8941-pwrkey
- qcom,pm8941-resin
- qcom,pmk8350-pwrkey
- qcom,pmk8350-resin
oneOf:
- enum:
- qcom,pm8941-pwrkey
- qcom,pm8941-resin
- qcom,pmk8350-pwrkey
- qcom,pmk8350-resin
- items:
- const: qcom,pmm8654au-pwrkey
- const: qcom,pmk8350-pwrkey
- items:
- const: qcom,pmm8654au-resin
- const: qcom,pmk8350-resin
interrupts:
maxItems: 1

1
Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.yaml
View File

@@ -39,6 +39,7 @@ properties:
- edt,edt-ft5406
- edt,edt-ft5506
- evervision,ev-ft5726
- focaltech,ft3518
- focaltech,ft5426
- focaltech,ft5452
- focaltech,ft6236

51
Documentation/devicetree/bindings/input/touchscreen/ilitek,ili210x.yaml Normal file
View File

@@ -0,0 +1,51 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/input/touchscreen/ilitek,ili210x.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Ilitek ILI21xx/ILI251x V3/V6 touch screen controller with i2c interface
maintainers:
- Frank Li <Frank.Li@nxp.com>
- Marek Vasut <marek.vasut+renesas@mailbox.org>
properties:
compatible:
enum:
- ilitek,ili210x
- ilitek,ili2117
- ilitek,ili2120
- ilitek,ili251x
reg:
maxItems: 1
interrupts:
maxItems: 1
reset-gpios:
maxItems: 1
wakeup-source: true
required:
- compatible
- reg
allOf:
- $ref: touchscreen.yaml
unevaluatedProperties: false
examples:
- |
i2c {
#address-cells = <1>;
#size-cells = <0>;
touchscreen@41 {
compatible = "ilitek,ili2120";
reg = <0x41>;
};
};

4
Documentation/devicetree/bindings/input/touchscreen/imagis,ist3038c.yaml
View File

@@ -55,7 +55,9 @@ allOf:
properties:
compatible:
contains:
const: imagis,ist3032c
enum:
- imagis,ist3032c
- imagis,ist3038
then:
properties:
linux,keycodes: false

10
Documentation/devicetree/bindings/input/touchscreen/sitronix,st1232.yaml
View File

@@ -14,9 +14,13 @@ allOf:
properties:
compatible:
enum:
- sitronix,st1232
- sitronix,st1633
oneOf:
- enum:
- sitronix,st1232
- sitronix,st1633
- items:
- const: sitronix,st1624
- const: sitronix,st1633
reg:
maxItems: 1

3
Documentation/devicetree/bindings/input/touchscreen/ti,tsc2007.yaml
View File

@@ -53,6 +53,9 @@ properties:
how much time to wait (in milliseconds) before reading again the
values from the tsc2007.
"#io-channel-cells":
const: 1
required:
- compatible
- reg

4
Documentation/devicetree/bindings/input/touchscreen/trivial-touch.yaml
View File

@@ -23,9 +23,6 @@ properties:
# Hynitron cstxxx series touchscreen controller
- hynitron,cst340
# Ilitek I2C Touchscreen Controller
- ilitek,ili210x
- ilitek,ili2117
- ilitek,ili2120
- ilitek,ili2130
- ilitek,ili2131
- ilitek,ili2132
@@ -33,7 +30,6 @@ properties:
- ilitek,ili2322
- ilitek,ili2323
- ilitek,ili2326
- ilitek,ili251x
- ilitek,ili2520
- ilitek,ili2521
# MAXI MAX11801 Resistive touch screen controller with i2c interface

1
Documentation/devicetree/bindings/interconnect/mediatek,mt8183-emi.yaml
View File

@@ -40,6 +40,7 @@ properties:
enum:
- mediatek,mt8183-emi
- mediatek,mt8195-emi
- mediatek,mt8196-emi
'#interconnect-cells':
const: 1

1
Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml
View File

@@ -25,6 +25,7 @@ properties:
- const: qcom,msm8998-bwmon # BWMON v4
- items:
- enum:
- qcom,glymur-cpu-bwmon
- qcom,kaanapali-cpu-bwmon
- qcom,qcm2290-cpu-bwmon
- qcom,qcs615-cpu-bwmon

2
Documentation/devicetree/bindings/interconnect/qcom,qcs615-rpmh.yaml
View File

@@ -27,7 +27,6 @@ properties:
- qcom,qcs615-config-noc
- qcom,qcs615-dc-noc
- qcom,qcs615-gem-noc
- qcom,qcs615-ipa-virt
- qcom,qcs615-mc-virt
- qcom,qcs615-mmss-noc
- qcom,qcs615-system-noc
@@ -46,7 +45,6 @@ allOf:
contains:
enum:
- qcom,qcs615-camnoc-virt
- qcom,qcs615-ipa-virt
- qcom,qcs615-mc-virt
then:
properties:

74
Documentation/devicetree/bindings/leds/ams,as3668.yaml Normal file
View File

@@ -0,0 +1,74 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/leds/ams,as3668.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Osram 4-channel i2c LED driver
maintainers:
- Lukas Timmermann <linux@timmermann.space>
description:
This IC can drive up to four separate LEDs.
Having four channels suggests it could be used with a single RGBW LED.
properties:
compatible:
const: ams,as3668
reg:
maxItems: 1
"#address-cells":
const: 1
"#size-cells":
const: 0
patternProperties:
"^led@[0-3]$":
type: object
$ref: common.yaml#
unevaluatedProperties: false
properties:
reg:
maxItems: 1
required:
- compatible
- reg
- "#address-cells"
- "#size-cells"
additionalProperties: false
examples:
- |
#include <dt-bindings/leds/common.h>
i2c {
#address-cells = <1>;
#size-cells = <0>;
led-controller@42 {
compatible = "ams,as3668";
reg = <0x42>;
#address-cells = <1>;
#size-cells = <0>;
led@0 {
reg = <0x0>;
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_RED>;
};
led@1 {
reg = <0x1>;
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_GREEN>;
};
};
};

24
Documentation/devicetree/bindings/leds/backlight/qcom-wled.yaml
View File

@@ -98,8 +98,8 @@ properties:
description: |
Over-voltage protection limit. This property is for WLED4 only.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [ 18100, 19600, 29600, 31100 ]
default: 29600
minimum: 17800
maximum: 31100
qcom,num-strings:
description: |
@@ -239,6 +239,26 @@ allOf:
minimum: 0
maximum: 4095
- if:
properties:
compatible:
contains:
enum:
- qcom,pmi8950-wled
- qcom,pmi8994-wled
then:
properties:
qcom,ovp-millivolt:
enum: [ 17800, 19400, 29500, 31000 ]
default: 29500
else:
properties:
qcom,ovp-millivolt:
enum: [ 18100, 19600, 29600, 31100 ]
default: 29600
required:
- compatible
- reg

2
Documentation/devicetree/bindings/leds/leds-class-multicolor.yaml
View File

@@ -21,7 +21,7 @@ description: |
properties:
$nodename:
pattern: "^multi-led(@[0-9a-f])?$"
pattern: "^multi-led(@[0-9a-f]|-[0-9]+)?$"
color:
description: |

1
Documentation/devicetree/bindings/leds/leds-is31fl32xx.txt
View File

@@ -10,6 +10,7 @@ Required properties:
issi,is31fl3235
issi,is31fl3218
issi,is31fl3216
issi,is31fl3293
si-en,sn3218
si-en,sn3216
- reg: I2C slave address

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