mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2026-05-05 15:49:42 -04:00
Merge tag 'mvebu-dt64-4.21-1' of git://git.infradead.org/linux-mvebu into next/dt
mvebu dt64 for 4.21 (part 1) - complete the description of the clearfog-gt-8k board (Armada 8040 based board) - declare eMMC on espressobin (Armada 3720 based board) which still need to be enable by the bootloader as it is not present on all the board. - add a new version of the Macchiatobin (Armada 8040 based board): the Single Shot (without the 10G 3310 PHYs). * tag 'mvebu-dt64-4.21-1' of git://git.infradead.org/linux-mvebu: arm64: dts: clearfog-gt-8k: describe mini-PCIe CON2 USB arm64: dts: add support for Macchiatobin Single Shot board arm64: dts: marvell: armada-37xx: Enable emmc on espressobin arm64: dts: marvell: armada37xx: Add emmc/sdio pinctrl definition arm64: dts: clearfog-gt-8k: enable mini-PCIe CON2 USB arm64: dts: clearfog-gt-8k: 1G eth PHY reset signal arm64: dts: clearfog-gt-8k: fix USB regulator gpio polarity Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
@@ -6,4 +6,5 @@ dtb-$(CONFIG_ARCH_MVEBU) += armada-7040-db.dtb
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dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-clearfog-gt-8k.dtb
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dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-db.dtb
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dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-mcbin.dtb
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dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-mcbin-singleshot.dtb
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dtb-$(CONFIG_ARCH_MVEBU) += armada-8080-db.dtb
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@@ -60,9 +60,31 @@ &sdhci1 {
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cd-gpios = <&gpionb 3 GPIO_ACTIVE_LOW>;
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marvell,pad-type = "sd";
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vqmmc-supply = <&vcc_sd_reg1>;
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pinctrl-names = "default";
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pinctrl-0 = <&sdio_pins>;
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status = "okay";
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};
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/* U11 */
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&sdhci0 {
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non-removable;
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bus-width = <8>;
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mmc-ddr-1_8v;
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mmc-hs400-1_8v;
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marvell,xenon-emmc;
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marvell,xenon-tun-count = <9>;
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marvell,pad-type = "fixed-1-8v";
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pinctrl-names = "default";
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pinctrl-0 = <&mmc_pins>;
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/*
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* This eMMC is not populated on all boards, so disable it by
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* default and let the bootloader enable it, if it is present
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*/
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status = "disabled";
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};
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&spi0 {
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status = "okay";
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@@ -234,6 +234,11 @@ uart2_pins: uart2-pins {
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groups = "uart2";
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function = "uart";
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};
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mmc_pins: mmc-pins {
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groups = "emmc_nb";
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function = "emmc";
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};
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};
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nb_pm: syscon@14000 {
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@@ -266,6 +271,11 @@ rgmii_pins: mii-pins {
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function = "mii";
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};
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sdio_pins: sdio-pins {
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groups = "sdio_sb";
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function = "sdio";
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};
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};
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eth0: ethernet@30000 {
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@@ -42,7 +42,7 @@ v_3_3: regulator-3-3v {
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v_5v0_usb3_hst_vbus: regulator-usb3-vbus0 {
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compatible = "regulator-fixed";
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gpio = <&cp0_gpio2 15 GPIO_ACTIVE_HIGH>;
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gpio = <&cp0_gpio2 15 GPIO_ACTIVE_LOW>;
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pinctrl-names = "default";
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pinctrl-0 = <&cp0_xhci_vbus_pins>;
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regulator-name = "v_5v0_usb3_hst_vbus";
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@@ -246,6 +246,18 @@ sata_reset {
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gpios = <1 GPIO_ACTIVE_HIGH>;
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output-high;
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};
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lte_reset {
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gpio-hog;
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gpios = <2 GPIO_ACTIVE_LOW>;
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output-low;
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};
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lte_disable {
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gpio-hog;
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gpios = <21 GPIO_ACTIVE_LOW>;
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output-low;
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};
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};
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&cp0_ethernet {
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@@ -270,6 +282,10 @@ &cp0_sdhci0 {
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vqmmc-supply = <&v_3_3>;
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};
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&cp0_usb3_1 {
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status = "okay";
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};
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&cp1_pinctrl {
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/*
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* MPP Bus:
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@@ -333,6 +349,10 @@ ge_phy: ethernet-phy@0 {
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*/
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marvell,reg-init = <3 16 0 0x1017>;
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reg = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&cp0_copper_eth_phy_reset>;
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reset-gpios = <&cp1_gpio1 11 GPIO_ACTIVE_LOW>;
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reset-assert-us = <10000>;
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};
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switch0: switch0@4 {
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29
arch/arm64/boot/dts/marvell/armada-8040-mcbin-singleshot.dts
Normal file
29
arch/arm64/boot/dts/marvell/armada-8040-mcbin-singleshot.dts
Normal file
@@ -0,0 +1,29 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (C) 2016 Marvell Technology Group Ltd.
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*
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* Device Tree file for MACCHIATOBin Armada 8040 community board platform
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*/
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#include "armada-8040-mcbin.dtsi"
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/ {
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model = "Marvell 8040 MACCHIATOBin Single-shot";
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compatible = "marvell,armada8040-mcbin-singleshot",
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"marvell,armada8040-mcbin", "marvell,armada8040",
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"marvell,armada-ap806-quad", "marvell,armada-ap806";
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};
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&cp0_eth0 {
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status = "okay";
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phy-mode = "10gbase-kr";
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managed = "in-band-status";
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sfp = <&sfp_eth0>;
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};
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&cp1_eth0 {
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status = "okay";
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phy-mode = "10gbase-kr";
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managed = "in-band-status";
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sfp = <&sfp_eth1>;
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};
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@@ -5,226 +5,13 @@
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* Device Tree file for MACCHIATOBin Armada 8040 community board platform
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*/
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#include "armada-8040.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include "armada-8040-mcbin.dtsi"
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/ {
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model = "Marvell 8040 MACCHIATOBin";
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compatible = "marvell,armada8040-mcbin", "marvell,armada8040",
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model = "Marvell 8040 MACCHIATOBin Double-shot";
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compatible = "marvell,armada8040-mcbin-doubleshot",
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"marvell,armada8040-mcbin", "marvell,armada8040",
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"marvell,armada-ap806-quad", "marvell,armada-ap806";
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chosen {
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stdout-path = "serial0:115200n8";
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};
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memory@0 {
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device_type = "memory";
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reg = <0x0 0x0 0x0 0x80000000>;
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};
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aliases {
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ethernet0 = &cp0_eth0;
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ethernet1 = &cp1_eth0;
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ethernet2 = &cp1_eth1;
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ethernet3 = &cp1_eth2;
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};
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/* Regulator labels correspond with schematics */
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v_3_3: regulator-3-3v {
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compatible = "regulator-fixed";
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regulator-name = "v_3_3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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status = "okay";
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};
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v_vddo_h: regulator-1-8v {
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compatible = "regulator-fixed";
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regulator-name = "v_vddo_h";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-always-on;
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status = "okay";
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};
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v_5v0_usb3_hst_vbus: regulator-usb3-vbus0 {
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compatible = "regulator-fixed";
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enable-active-high;
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gpio = <&cp0_gpio2 15 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&cp0_xhci_vbus_pins>;
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regulator-name = "v_5v0_usb3_hst_vbus";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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status = "okay";
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};
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usb3h0_phy: usb3_phy0 {
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compatible = "usb-nop-xceiv";
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vcc-supply = <&v_5v0_usb3_hst_vbus>;
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};
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sfp_eth0: sfp-eth0 {
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/* CON15,16 - CPM lane 4 */
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compatible = "sff,sfp";
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i2c-bus = <&sfpp0_i2c>;
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los-gpio = <&cp1_gpio1 28 GPIO_ACTIVE_HIGH>;
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mod-def0-gpio = <&cp1_gpio1 27 GPIO_ACTIVE_LOW>;
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tx-disable-gpio = <&cp1_gpio1 29 GPIO_ACTIVE_HIGH>;
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tx-fault-gpio = <&cp1_gpio1 26 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&cp1_sfpp0_pins>;
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};
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sfp_eth1: sfp-eth1 {
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/* CON17,18 - CPS lane 4 */
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compatible = "sff,sfp";
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i2c-bus = <&sfpp1_i2c>;
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los-gpio = <&cp1_gpio1 8 GPIO_ACTIVE_HIGH>;
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mod-def0-gpio = <&cp1_gpio1 11 GPIO_ACTIVE_LOW>;
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tx-disable-gpio = <&cp1_gpio1 10 GPIO_ACTIVE_HIGH>;
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tx-fault-gpio = <&cp0_gpio2 30 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&cp1_sfpp1_pins &cp0_sfpp1_pins>;
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};
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sfp_eth3: sfp-eth3 {
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/* CON13,14 - CPS lane 5 */
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compatible = "sff,sfp";
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i2c-bus = <&sfp_1g_i2c>;
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los-gpio = <&cp0_gpio2 22 GPIO_ACTIVE_HIGH>;
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mod-def0-gpio = <&cp0_gpio2 21 GPIO_ACTIVE_LOW>;
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tx-disable-gpio = <&cp1_gpio1 24 GPIO_ACTIVE_HIGH>;
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tx-fault-gpio = <&cp0_gpio2 19 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&cp0_sfp_1g_pins &cp1_sfp_1g_pins>;
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};
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};
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&uart0 {
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status = "okay";
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pinctrl-0 = <&uart0_pins>;
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pinctrl-names = "default";
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};
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&ap_sdhci0 {
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bus-width = <8>;
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/*
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* Not stable in HS modes - phy needs "more calibration", so add
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* the "slow-mode" and disable SDR104, SDR50 and DDR50 modes.
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*/
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marvell,xenon-phy-slow-mode;
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no-1-8-v;
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no-sd;
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no-sdio;
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non-removable;
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status = "okay";
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vqmmc-supply = <&v_vddo_h>;
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};
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&cp0_i2c0 {
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&cp0_i2c0_pins>;
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status = "okay";
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};
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&cp0_i2c1 {
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&cp0_i2c1_pins>;
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status = "okay";
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i2c-switch@70 {
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compatible = "nxp,pca9548";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x70>;
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|
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sfpp0_i2c: i2c@0 {
|
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#address-cells = <1>;
|
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#size-cells = <0>;
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||||
reg = <0>;
|
||||
};
|
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sfpp1_i2c: i2c@1 {
|
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#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <1>;
|
||||
};
|
||||
sfp_1g_i2c: i2c@2 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* J25 UART header */
|
||||
&cp0_uart1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cp0_uart1_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp0_mdio {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cp0_ge_mdio_pins>;
|
||||
status = "okay";
|
||||
|
||||
ge_phy: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&cp0_pcie0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cp0_pcie_pins>;
|
||||
num-lanes = <4>;
|
||||
num-viewport = <8>;
|
||||
reset-gpio = <&cp0_gpio1 20 GPIO_ACTIVE_LOW>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp0_pinctrl {
|
||||
cp0_ge_mdio_pins: ge-mdio-pins {
|
||||
marvell,pins = "mpp32", "mpp34";
|
||||
marvell,function = "ge";
|
||||
};
|
||||
cp0_i2c1_pins: i2c1-pins {
|
||||
marvell,pins = "mpp35", "mpp36";
|
||||
marvell,function = "i2c1";
|
||||
};
|
||||
cp0_i2c0_pins: i2c0-pins {
|
||||
marvell,pins = "mpp37", "mpp38";
|
||||
marvell,function = "i2c0";
|
||||
};
|
||||
cp0_uart1_pins: uart1-pins {
|
||||
marvell,pins = "mpp40", "mpp41";
|
||||
marvell,function = "uart1";
|
||||
};
|
||||
cp0_xhci_vbus_pins: xhci0-vbus-pins {
|
||||
marvell,pins = "mpp47";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
cp0_sfp_1g_pins: sfp-1g-pins {
|
||||
marvell,pins = "mpp51", "mpp53", "mpp54";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
cp0_pcie_pins: pcie-pins {
|
||||
marvell,pins = "mpp52";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
cp0_sdhci_pins: sdhci-pins {
|
||||
marvell,pins = "mpp55", "mpp56", "mpp57", "mpp58", "mpp59",
|
||||
"mpp60", "mpp61";
|
||||
marvell,function = "sdio";
|
||||
};
|
||||
cp0_sfpp1_pins: sfpp1-pins {
|
||||
marvell,pins = "mpp62";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
};
|
||||
|
||||
&cp0_xmdio {
|
||||
@@ -243,46 +30,11 @@ phy8: ethernet-phy@8 {
|
||||
};
|
||||
};
|
||||
|
||||
&cp0_ethernet {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp0_eth0 {
|
||||
status = "okay";
|
||||
/* Network PHY */
|
||||
phy = <&phy0>;
|
||||
phy-mode = "10gbase-kr";
|
||||
/* Generic PHY, providing serdes lanes */
|
||||
phys = <&cp0_comphy4 0>;
|
||||
};
|
||||
|
||||
&cp0_sata0 {
|
||||
/* CPM Lane 0 - U29 */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp0_sdhci0 {
|
||||
/* U6 */
|
||||
broken-cd;
|
||||
bus-width = <4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cp0_sdhci_pins>;
|
||||
status = "okay";
|
||||
vqmmc-supply = <&v_3_3>;
|
||||
};
|
||||
|
||||
&cp0_usb3_0 {
|
||||
/* J38? - USB2.0 only */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp0_usb3_1 {
|
||||
/* J38? - USB2.0 only */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp1_ethernet {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp1_eth0 {
|
||||
@@ -290,81 +42,4 @@ &cp1_eth0 {
|
||||
/* Network PHY */
|
||||
phy = <&phy8>;
|
||||
phy-mode = "10gbase-kr";
|
||||
/* Generic PHY, providing serdes lanes */
|
||||
phys = <&cp1_comphy4 0>;
|
||||
};
|
||||
|
||||
&cp1_eth1 {
|
||||
/* CPS Lane 0 - J5 (Gigabit RJ45) */
|
||||
status = "okay";
|
||||
/* Network PHY */
|
||||
phy = <&ge_phy>;
|
||||
phy-mode = "sgmii";
|
||||
/* Generic PHY, providing serdes lanes */
|
||||
phys = <&cp1_comphy0 1>;
|
||||
};
|
||||
|
||||
&cp1_eth2 {
|
||||
/* CPS Lane 5 */
|
||||
status = "okay";
|
||||
/* Network PHY */
|
||||
phy-mode = "2500base-x";
|
||||
managed = "in-band-status";
|
||||
/* Generic PHY, providing serdes lanes */
|
||||
phys = <&cp1_comphy5 2>;
|
||||
sfp = <&sfp_eth3>;
|
||||
};
|
||||
|
||||
&cp1_pinctrl {
|
||||
cp1_sfpp1_pins: sfpp1-pins {
|
||||
marvell,pins = "mpp8", "mpp10", "mpp11";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
cp1_spi1_pins: spi1-pins {
|
||||
marvell,pins = "mpp12", "mpp13", "mpp14", "mpp15", "mpp16";
|
||||
marvell,function = "spi1";
|
||||
};
|
||||
cp1_uart0_pins: uart0-pins {
|
||||
marvell,pins = "mpp6", "mpp7";
|
||||
marvell,function = "uart0";
|
||||
};
|
||||
cp1_sfp_1g_pins: sfp-1g-pins {
|
||||
marvell,pins = "mpp24";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
cp1_sfpp0_pins: sfpp0-pins {
|
||||
marvell,pins = "mpp26", "mpp27", "mpp28", "mpp29";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
};
|
||||
|
||||
/* J27 UART header */
|
||||
&cp1_uart0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cp1_uart0_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp1_sata0 {
|
||||
/* CPS Lane 1 - U32 */
|
||||
/* CPS Lane 3 - U31 */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp1_spi1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cp1_spi1_pins>;
|
||||
status = "okay";
|
||||
|
||||
spi-flash@0 {
|
||||
compatible = "st,w25q32";
|
||||
spi-max-frequency = <50000000>;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&cp1_usb3_0 {
|
||||
/* CPS Lane 2 - CON7 */
|
||||
usb-phy = <&usb3h0_phy>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
346
arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
Normal file
346
arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
Normal file
@@ -0,0 +1,346 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (C) 2016 Marvell Technology Group Ltd.
|
||||
*
|
||||
* Device Tree file for MACCHIATOBin Armada 8040 community board platform
|
||||
*/
|
||||
|
||||
#include "armada-8040.dtsi"
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/ {
|
||||
model = "Marvell 8040 MACCHIATOBin";
|
||||
compatible = "marvell,armada8040-mcbin", "marvell,armada8040",
|
||||
"marvell,armada-ap806-quad", "marvell,armada-ap806";
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x0 0x0 0x80000000>;
|
||||
};
|
||||
|
||||
aliases {
|
||||
ethernet0 = &cp0_eth0;
|
||||
ethernet1 = &cp1_eth0;
|
||||
ethernet2 = &cp1_eth1;
|
||||
ethernet3 = &cp1_eth2;
|
||||
};
|
||||
|
||||
/* Regulator labels correspond with schematics */
|
||||
v_3_3: regulator-3-3v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "v_3_3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
v_vddo_h: regulator-1-8v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "v_vddo_h";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
v_5v0_usb3_hst_vbus: regulator-usb3-vbus0 {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&cp0_gpio2 15 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cp0_xhci_vbus_pins>;
|
||||
regulator-name = "v_5v0_usb3_hst_vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usb3h0_phy: usb3_phy0 {
|
||||
compatible = "usb-nop-xceiv";
|
||||
vcc-supply = <&v_5v0_usb3_hst_vbus>;
|
||||
};
|
||||
|
||||
sfp_eth0: sfp-eth0 {
|
||||
/* CON15,16 - CPM lane 4 */
|
||||
compatible = "sff,sfp";
|
||||
i2c-bus = <&sfpp0_i2c>;
|
||||
los-gpio = <&cp1_gpio1 28 GPIO_ACTIVE_HIGH>;
|
||||
mod-def0-gpio = <&cp1_gpio1 27 GPIO_ACTIVE_LOW>;
|
||||
tx-disable-gpio = <&cp1_gpio1 29 GPIO_ACTIVE_HIGH>;
|
||||
tx-fault-gpio = <&cp1_gpio1 26 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cp1_sfpp0_pins>;
|
||||
};
|
||||
|
||||
sfp_eth1: sfp-eth1 {
|
||||
/* CON17,18 - CPS lane 4 */
|
||||
compatible = "sff,sfp";
|
||||
i2c-bus = <&sfpp1_i2c>;
|
||||
los-gpio = <&cp1_gpio1 8 GPIO_ACTIVE_HIGH>;
|
||||
mod-def0-gpio = <&cp1_gpio1 11 GPIO_ACTIVE_LOW>;
|
||||
tx-disable-gpio = <&cp1_gpio1 10 GPIO_ACTIVE_HIGH>;
|
||||
tx-fault-gpio = <&cp0_gpio2 30 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cp1_sfpp1_pins &cp0_sfpp1_pins>;
|
||||
};
|
||||
|
||||
sfp_eth3: sfp-eth3 {
|
||||
/* CON13,14 - CPS lane 5 */
|
||||
compatible = "sff,sfp";
|
||||
i2c-bus = <&sfp_1g_i2c>;
|
||||
los-gpio = <&cp0_gpio2 22 GPIO_ACTIVE_HIGH>;
|
||||
mod-def0-gpio = <&cp0_gpio2 21 GPIO_ACTIVE_LOW>;
|
||||
tx-disable-gpio = <&cp1_gpio1 24 GPIO_ACTIVE_HIGH>;
|
||||
tx-fault-gpio = <&cp0_gpio2 19 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cp0_sfp_1g_pins &cp1_sfp_1g_pins>;
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&uart0_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
&ap_sdhci0 {
|
||||
bus-width = <8>;
|
||||
/*
|
||||
* Not stable in HS modes - phy needs "more calibration", so add
|
||||
* the "slow-mode" and disable SDR104, SDR50 and DDR50 modes.
|
||||
*/
|
||||
marvell,xenon-phy-slow-mode;
|
||||
no-1-8-v;
|
||||
no-sd;
|
||||
no-sdio;
|
||||
non-removable;
|
||||
status = "okay";
|
||||
vqmmc-supply = <&v_vddo_h>;
|
||||
};
|
||||
|
||||
&cp0_i2c0 {
|
||||
clock-frequency = <100000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cp0_i2c0_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp0_i2c1 {
|
||||
clock-frequency = <100000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cp0_i2c1_pins>;
|
||||
status = "okay";
|
||||
|
||||
i2c-switch@70 {
|
||||
compatible = "nxp,pca9548";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x70>;
|
||||
|
||||
sfpp0_i2c: i2c@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
};
|
||||
sfpp1_i2c: i2c@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <1>;
|
||||
};
|
||||
sfp_1g_i2c: i2c@2 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* J25 UART header */
|
||||
&cp0_uart1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cp0_uart1_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp0_mdio {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cp0_ge_mdio_pins>;
|
||||
status = "okay";
|
||||
|
||||
ge_phy: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&cp0_pcie0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cp0_pcie_pins>;
|
||||
num-lanes = <4>;
|
||||
num-viewport = <8>;
|
||||
reset-gpio = <&cp0_gpio1 20 GPIO_ACTIVE_LOW>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp0_pinctrl {
|
||||
cp0_ge_mdio_pins: ge-mdio-pins {
|
||||
marvell,pins = "mpp32", "mpp34";
|
||||
marvell,function = "ge";
|
||||
};
|
||||
cp0_i2c1_pins: i2c1-pins {
|
||||
marvell,pins = "mpp35", "mpp36";
|
||||
marvell,function = "i2c1";
|
||||
};
|
||||
cp0_i2c0_pins: i2c0-pins {
|
||||
marvell,pins = "mpp37", "mpp38";
|
||||
marvell,function = "i2c0";
|
||||
};
|
||||
cp0_uart1_pins: uart1-pins {
|
||||
marvell,pins = "mpp40", "mpp41";
|
||||
marvell,function = "uart1";
|
||||
};
|
||||
cp0_xhci_vbus_pins: xhci0-vbus-pins {
|
||||
marvell,pins = "mpp47";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
cp0_sfp_1g_pins: sfp-1g-pins {
|
||||
marvell,pins = "mpp51", "mpp53", "mpp54";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
cp0_pcie_pins: pcie-pins {
|
||||
marvell,pins = "mpp52";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
cp0_sdhci_pins: sdhci-pins {
|
||||
marvell,pins = "mpp55", "mpp56", "mpp57", "mpp58", "mpp59",
|
||||
"mpp60", "mpp61";
|
||||
marvell,function = "sdio";
|
||||
};
|
||||
cp0_sfpp1_pins: sfpp1-pins {
|
||||
marvell,pins = "mpp62";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
};
|
||||
|
||||
&cp0_ethernet {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp0_eth0 {
|
||||
/* Generic PHY, providing serdes lanes */
|
||||
phys = <&cp0_comphy4 0>;
|
||||
};
|
||||
|
||||
&cp0_sata0 {
|
||||
/* CPM Lane 0 - U29 */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp0_sdhci0 {
|
||||
/* U6 */
|
||||
broken-cd;
|
||||
bus-width = <4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cp0_sdhci_pins>;
|
||||
status = "okay";
|
||||
vqmmc-supply = <&v_3_3>;
|
||||
};
|
||||
|
||||
&cp0_usb3_0 {
|
||||
/* J38? - USB2.0 only */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp0_usb3_1 {
|
||||
/* J38? - USB2.0 only */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp1_ethernet {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp1_eth0 {
|
||||
/* Generic PHY, providing serdes lanes */
|
||||
phys = <&cp1_comphy4 0>;
|
||||
};
|
||||
|
||||
&cp1_eth1 {
|
||||
/* CPS Lane 0 - J5 (Gigabit RJ45) */
|
||||
status = "okay";
|
||||
/* Network PHY */
|
||||
phy = <&ge_phy>;
|
||||
phy-mode = "sgmii";
|
||||
/* Generic PHY, providing serdes lanes */
|
||||
phys = <&cp1_comphy0 1>;
|
||||
};
|
||||
|
||||
&cp1_eth2 {
|
||||
/* CPS Lane 5 */
|
||||
status = "okay";
|
||||
/* Network PHY */
|
||||
phy-mode = "2500base-x";
|
||||
managed = "in-band-status";
|
||||
/* Generic PHY, providing serdes lanes */
|
||||
phys = <&cp1_comphy5 2>;
|
||||
sfp = <&sfp_eth3>;
|
||||
};
|
||||
|
||||
&cp1_pinctrl {
|
||||
cp1_sfpp1_pins: sfpp1-pins {
|
||||
marvell,pins = "mpp8", "mpp10", "mpp11";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
cp1_spi1_pins: spi1-pins {
|
||||
marvell,pins = "mpp12", "mpp13", "mpp14", "mpp15", "mpp16";
|
||||
marvell,function = "spi1";
|
||||
};
|
||||
cp1_uart0_pins: uart0-pins {
|
||||
marvell,pins = "mpp6", "mpp7";
|
||||
marvell,function = "uart0";
|
||||
};
|
||||
cp1_sfp_1g_pins: sfp-1g-pins {
|
||||
marvell,pins = "mpp24";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
cp1_sfpp0_pins: sfpp0-pins {
|
||||
marvell,pins = "mpp26", "mpp27", "mpp28", "mpp29";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
};
|
||||
|
||||
/* J27 UART header */
|
||||
&cp1_uart0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cp1_uart0_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp1_sata0 {
|
||||
/* CPS Lane 1 - U32 */
|
||||
/* CPS Lane 3 - U31 */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp1_spi1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cp1_spi1_pins>;
|
||||
status = "okay";
|
||||
|
||||
spi-flash@0 {
|
||||
compatible = "st,w25q32";
|
||||
spi-max-frequency = <50000000>;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&cp1_usb3_0 {
|
||||
/* CPS Lane 2 - CON7 */
|
||||
usb-phy = <&usb3h0_phy>;
|
||||
status = "okay";
|
||||
};
|
||||
Reference in New Issue
Block a user