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Merge tag 'actions-arm-dt-for-v5.10' of git://git.kernel.org/pub/scm/linux/kernel/git/mani/linux-actions into arm/dt

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Actions Semi ARM DT for v5.10:

- Add devicetree support for Caninos Loucos Labrador SBC manufactured
  by Laboratory of Integrated Technological Systems (LSI-TEC), Brazil.
  This board is based on Actions Semi S500 SoC. More information about
  this board can be found in their website: https://caninosloucos.org/en/

- Fix PPI interrupt specifiers for peripherals attached to Cortex-A9 CPU

- Add devicetree support for RoseapplePi SBC manufactured by Roseapple Pi
  team in Taiwan. This board is based on Actions Semi S500 SoC.
  More information about this board can be found in their website:
  http://roseapplepi.org/

* tag 'actions-arm-dt-for-v5.10' of git://git.kernel.org/pub/scm/linux/kernel/git/mani/linux-actions:
  ARM: dts: owl-s500: Add RoseapplePi
  ARM: dts: owl-s500: Fix incorrect PPI interrupt specifiers
  ARM: dts: Add Caninos Loucos Labrador v2

Link: https://lore.kernel.org/r/20200922113712.GB11251@Mani-XPS-13-9360
Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
2020-10-03 12:35:55 -07:00
parent a6d862f21a 47be1cdee7
commit d4509b6545
5 changed files with 109 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm/boot/dts/Makefile
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@@ -873,6 +873,8 @@ dtb-$(CONFIG_ARCH_ORION5X) += \
dtb-$(CONFIG_ARCH_ACTIONS) += \
owl-s500-cubieboard6.dtb \
owl-s500-guitar-bb-rev-b.dtb \
owl-s500-labrador-base-m.dtb \
owl-s500-roseapplepi.dtb \
owl-s500-sparky.dtb
dtb-$(CONFIG_ARCH_PICOXCELL) += \
picoxcell-pc7302-pc3x2.dtb \

35
arch/arm/boot/dts/owl-s500-labrador-base-m.dts Normal file
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@@ -0,0 +1,35 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Caninos Labrador Base Board
*
* Copyright (c) 2019-2020 Matheus Castello
*/
/dts-v1/;
#include "owl-s500-labrador-v2.dtsi"
/ {
model = "Caninos Labrador Core v2 on Labrador Base-M v1";
compatible = "caninos,labrador-base-m",
"caninos,labrador-v2", "actions,s500";
aliases {
serial3 = &uart3;
};
chosen {
stdout-path = "serial3:115200n8";
};
uart3_clk: uart3-clk {
compatible = "fixed-clock";
clock-frequency = <921600>;
#clock-cells = <0>;
};
};
&uart3 {
status = "okay";
clocks = <&uart3_clk>;
};

22
arch/arm/boot/dts/owl-s500-labrador-v2.dtsi Normal file
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@@ -0,0 +1,22 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Caninos Labrador SoM V2
*
* Copyright (c) 2019-2020 Matheus Castello
*/
#include "owl-s500.dtsi"
/ {
model = "Caninos Labrador Core V2.1";
compatible = "caninos,labrador-v2", "actions,s500";
memory@0 {
device_type = "memory";
reg = <0x0 0x80000000>;
};
};
&timer {
clocks = <&hosc>;
};

47
arch/arm/boot/dts/owl-s500-roseapplepi.dts Normal file
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@@ -0,0 +1,47 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Roseapple Pi
*
* Copyright (C) 2020 Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
*/
/dts-v1/;
#include "owl-s500.dtsi"
/ {
compatible = "roseapplepi,roseapplepi", "actions,s500";
model = "Roseapple Pi";
aliases {
serial2 = &uart2;
};
chosen {
stdout-path = "serial2:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x0 0x80000000>; /* 2GB */
};
uart2_clk: uart2-clk {
compatible = "fixed-clock";
clock-frequency = <921600>;
#clock-cells = <0>;
};
};
&twd_timer {
status = "okay";
};
&timer {
clocks = <&hosc>;
};
&uart2 {
status = "okay";
clocks = <&uart2_clk>;
};

6
arch/arm/boot/dts/owl-s500.dtsi
View File

@@ -84,21 +84,21 @@ scu: scu@b0020000 {
global_timer: timer@b0020200 {
compatible = "arm,cortex-a9-global-timer";
reg = <0xb0020200 0x100>;
interrupts = <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
status = "disabled";
};
twd_timer: timer@b0020600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0xb0020600 0x20>;
interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
status = "disabled";
};
twd_wdt: wdt@b0020620 {
compatible = "arm,cortex-a9-twd-wdt";
reg = <0xb0020620 0xe0>;
interrupts = <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
status = "disabled";
};