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Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux
Pull arm64 fixes from Will Deacon:
"There's nothing major (even the vmalloc one is just suppressing a
potential warning) but all worth having, nonetheless.
- Suppress KASAN false positive in stack unwinding code
- Drop redundant reset of the GCS state on exec()
- Don't try to descend into a !present PMD when creating a huge
vmap() entry at the PUD level
- Fix a small typo in the arm64 booting Documentation"
* tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux:
arm64/ptrace: Fix stack-out-of-bounds read in regs_get_kernel_stack_nth()
arm64/gcs: Don't call gcs_free() during flush_gcs()
arm64: Restrict pagetable teardown to avoid false warning
docs: arm64: Fix ICC_SRE_EL2 register typo in booting.rst
This commit is contained in:
@@ -234,7 +234,7 @@ Before jumping into the kernel, the following conditions must be met:
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- If the kernel is entered at EL1:
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- ICC.SRE_EL2.Enable (bit 3) must be initialised to 0b1
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- ICC_SRE_EL2.Enable (bit 3) must be initialised to 0b1
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- ICC_SRE_EL2.SRE (bit 0) must be initialised to 0b1.
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- The DT or ACPI tables must describe a GICv3 interrupt controller.
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@@ -288,7 +288,9 @@ static void flush_gcs(void)
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if (!system_supports_gcs())
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return;
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gcs_free(current);
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current->thread.gcspr_el0 = 0;
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current->thread.gcs_base = 0;
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current->thread.gcs_size = 0;
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current->thread.gcs_el0_mode = 0;
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write_sysreg_s(GCSCRE0_EL1_nTR, SYS_GCSCRE0_EL1);
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write_sysreg_s(0, SYS_GCSPR_EL0);
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@@ -141,7 +141,7 @@ unsigned long regs_get_kernel_stack_nth(struct pt_regs *regs, unsigned int n)
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addr += n;
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if (regs_within_kernel_stack(regs, (unsigned long)addr))
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return *addr;
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return READ_ONCE_NOCHECK(*addr);
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else
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return 0;
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}
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@@ -1305,7 +1305,8 @@ int pud_free_pmd_page(pud_t *pudp, unsigned long addr)
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next = addr;
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end = addr + PUD_SIZE;
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do {
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pmd_free_pte_page(pmdp, next);
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if (pmd_present(pmdp_get(pmdp)))
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pmd_free_pte_page(pmdp, next);
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} while (pmdp++, next += PMD_SIZE, next != end);
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pud_clear(pudp);
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