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https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2026-05-16 09:02:21 -04:00
ASoC: Drop RPL driver
The RPL driver is no longer needed because its functionality has been superseded by the YC driver Signed-off-by: Mingyou Chen <qby140326@gmail.com> Reviewed-by: Mario Limonciello (AMD) <superm1@kernel.org> Link: https://patch.msgid.link/20260213055904.110256-3-qby140326@gmail.com Reviewed-by: Vijendar Mukunda <Vijendar.Mukunda@amd.com> Signed-off-by: Mark Brown <broonie@kernel.org>
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@@ -122,16 +122,6 @@ config SND_AMD_ACP_CONFIG
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source "sound/soc/amd/acp/Kconfig"
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config SND_SOC_AMD_RPL_ACP6x
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tristate "AMD Audio Coprocessor-v6.2 RPL support"
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depends on X86 && PCI
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help
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This option enables Audio Coprocessor i.e. ACP v6.2 support on
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AMD RPL platform. By enabling this flag build will be
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triggered for ACP PCI driver.
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Say m if you have such a device.
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If unsure select "N".
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config SND_SOC_AMD_ACP63_TOPLEVEL
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tristate "support for AMD platforms with ACP version >= 6.3"
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default SND_AMD_ACP_CONFIG
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@@ -17,5 +17,4 @@ obj-$(CONFIG_SND_SOC_AMD_ACP5x) += vangogh/
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obj-$(CONFIG_SND_SOC_AMD_ACP6x) += yc/
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obj-$(CONFIG_SND_AMD_ACP_CONFIG) += acp/
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obj-$(CONFIG_SND_AMD_ACP_CONFIG) += snd-acp-config.o
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obj-$(CONFIG_SND_SOC_AMD_RPL_ACP6x) += rpl/
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obj-$(CONFIG_SND_SOC_AMD_PS) += ps/
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@@ -1,5 +0,0 @@
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# SPDX-License-Identifier: GPL-2.0+
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# RPL platform Support
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snd-rpl-pci-acp6x-y := rpl-pci-acp6x.o
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obj-$(CONFIG_SND_SOC_AMD_RPL_ACP6x) += snd-rpl-pci-acp6x.o
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@@ -1,227 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* AMD RPL ACP PCI Driver
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*
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* Copyright 2022 Advanced Micro Devices, Inc.
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*/
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#include <linux/pci.h>
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#include <linux/module.h>
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#include <linux/io.h>
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#include <linux/delay.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include "rpl_acp6x.h"
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struct rpl_dev_data {
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void __iomem *acp6x_base;
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};
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static int rpl_power_on(void __iomem *acp_base)
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{
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u32 val;
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int timeout;
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val = rpl_acp_readl(acp_base + ACP_PGFSM_STATUS);
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if (!val)
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return val;
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if ((val & ACP_PGFSM_STATUS_MASK) != ACP_POWER_ON_IN_PROGRESS)
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rpl_acp_writel(ACP_PGFSM_CNTL_POWER_ON_MASK, acp_base + ACP_PGFSM_CONTROL);
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timeout = 0;
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while (++timeout < 500) {
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val = rpl_acp_readl(acp_base + ACP_PGFSM_STATUS);
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if (!val)
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return 0;
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udelay(1);
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}
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return -ETIMEDOUT;
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}
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static int rpl_reset(void __iomem *acp_base)
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{
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u32 val;
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int timeout;
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rpl_acp_writel(1, acp_base + ACP_SOFT_RESET);
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timeout = 0;
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while (++timeout < 500) {
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val = rpl_acp_readl(acp_base + ACP_SOFT_RESET);
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if (val & ACP_SOFT_RESET_SOFTRESET_AUDDONE_MASK)
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break;
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cpu_relax();
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}
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rpl_acp_writel(0, acp_base + ACP_SOFT_RESET);
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timeout = 0;
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while (++timeout < 500) {
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val = rpl_acp_readl(acp_base + ACP_SOFT_RESET);
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if (!val)
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return 0;
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cpu_relax();
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}
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return -ETIMEDOUT;
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}
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static int rpl_init(void __iomem *acp_base)
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{
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int ret;
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/* power on */
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ret = rpl_power_on(acp_base);
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if (ret) {
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pr_err("ACP power on failed\n");
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return ret;
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}
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rpl_acp_writel(0x01, acp_base + ACP_CONTROL);
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/* Reset */
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ret = rpl_reset(acp_base);
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if (ret) {
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pr_err("ACP reset failed\n");
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return ret;
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}
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rpl_acp_writel(0x03, acp_base + ACP_CLKMUX_SEL);
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return 0;
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}
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static int rpl_deinit(void __iomem *acp_base)
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{
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int ret;
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/* Reset */
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ret = rpl_reset(acp_base);
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if (ret) {
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pr_err("ACP reset failed\n");
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return ret;
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}
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rpl_acp_writel(0x00, acp_base + ACP_CLKMUX_SEL);
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rpl_acp_writel(0x00, acp_base + ACP_CONTROL);
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return 0;
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}
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static int snd_rpl_probe(struct pci_dev *pci,
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const struct pci_device_id *pci_id)
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{
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struct rpl_dev_data *adata;
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u32 addr;
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int ret;
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/* RPL device check */
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switch (pci->revision) {
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case 0x62:
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break;
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default:
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dev_dbg(&pci->dev, "acp6x pci device not found\n");
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return -ENODEV;
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}
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if (pci_enable_device(pci)) {
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dev_err(&pci->dev, "pci_enable_device failed\n");
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return -ENODEV;
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}
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ret = pci_request_regions(pci, "AMD ACP6x audio");
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if (ret < 0) {
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dev_err(&pci->dev, "pci_request_regions failed\n");
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goto disable_pci;
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}
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adata = devm_kzalloc(&pci->dev, sizeof(struct rpl_dev_data),
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GFP_KERNEL);
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if (!adata) {
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ret = -ENOMEM;
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goto release_regions;
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}
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addr = pci_resource_start(pci, 0);
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adata->acp6x_base = devm_ioremap(&pci->dev, addr,
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pci_resource_len(pci, 0));
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if (!adata->acp6x_base) {
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ret = -ENOMEM;
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goto release_regions;
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}
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pci_set_master(pci);
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pci_set_drvdata(pci, adata);
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ret = rpl_init(adata->acp6x_base);
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if (ret)
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goto release_regions;
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pm_runtime_set_autosuspend_delay(&pci->dev, ACP_SUSPEND_DELAY_MS);
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pm_runtime_use_autosuspend(&pci->dev);
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pm_runtime_put_noidle(&pci->dev);
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pm_runtime_allow(&pci->dev);
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return 0;
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release_regions:
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pci_release_regions(pci);
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disable_pci:
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pci_disable_device(pci);
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return ret;
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}
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static int snd_rpl_suspend(struct device *dev)
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{
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struct rpl_dev_data *adata;
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int ret;
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adata = dev_get_drvdata(dev);
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ret = rpl_deinit(adata->acp6x_base);
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if (ret)
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dev_err(dev, "ACP de-init failed\n");
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return ret;
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}
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static int snd_rpl_resume(struct device *dev)
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{
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struct rpl_dev_data *adata;
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int ret;
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adata = dev_get_drvdata(dev);
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ret = rpl_init(adata->acp6x_base);
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if (ret)
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dev_err(dev, "ACP init failed\n");
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return ret;
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}
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static const struct dev_pm_ops rpl_pm = {
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RUNTIME_PM_OPS(snd_rpl_suspend, snd_rpl_resume, NULL)
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SYSTEM_SLEEP_PM_OPS(snd_rpl_suspend, snd_rpl_resume)
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};
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static void snd_rpl_remove(struct pci_dev *pci)
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{
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struct rpl_dev_data *adata;
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int ret;
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adata = pci_get_drvdata(pci);
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ret = rpl_deinit(adata->acp6x_base);
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if (ret)
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dev_err(&pci->dev, "ACP de-init failed\n");
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pm_runtime_forbid(&pci->dev);
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pm_runtime_get_noresume(&pci->dev);
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pci_release_regions(pci);
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pci_disable_device(pci);
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}
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static const struct pci_device_id snd_rpl_ids[] = {
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, ACP_DEVICE_ID),
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.class = PCI_CLASS_MULTIMEDIA_OTHER << 8,
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.class_mask = 0xffffff },
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{ 0, },
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};
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MODULE_DEVICE_TABLE(pci, snd_rpl_ids);
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static struct pci_driver rpl_acp6x_driver = {
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.name = KBUILD_MODNAME,
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.id_table = snd_rpl_ids,
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.probe = snd_rpl_probe,
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.remove = snd_rpl_remove,
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.driver = {
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.pm = pm_ptr(&rpl_pm),
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}
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};
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module_pci_driver(rpl_acp6x_driver);
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MODULE_DESCRIPTION("AMD ACP RPL PCI driver");
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MODULE_LICENSE("GPL v2");
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@@ -1,36 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* AMD ACP Driver
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*
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* Copyright (C) 2021 Advanced Micro Devices, Inc. All rights reserved.
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*/
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#include "rpl_acp6x_chip_offset_byte.h"
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#define ACP_DEVICE_ID 0x15E2
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#define ACP6x_PHY_BASE_ADDRESS 0x1240000
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#define ACP_SOFT_RESET_SOFTRESET_AUDDONE_MASK 0x00010001
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#define ACP_PGFSM_CNTL_POWER_ON_MASK 1
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#define ACP_PGFSM_CNTL_POWER_OFF_MASK 0
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#define ACP_PGFSM_STATUS_MASK 3
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#define ACP_POWERED_ON 0
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#define ACP_POWER_ON_IN_PROGRESS 1
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#define ACP_POWERED_OFF 2
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#define ACP_POWER_OFF_IN_PROGRESS 3
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#define DELAY_US 5
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#define ACP_COUNTER 20000
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/* time in ms for runtime suspend delay */
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#define ACP_SUSPEND_DELAY_MS 2000
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static inline u32 rpl_acp_readl(void __iomem *base_addr)
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{
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return readl(base_addr - ACP6x_PHY_BASE_ADDRESS);
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}
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static inline void rpl_acp_writel(u32 val, void __iomem *base_addr)
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{
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writel(val, base_addr - ACP6x_PHY_BASE_ADDRESS);
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}
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@@ -1,30 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* AMD ACP 6.2 Register Documentation
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*
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* Copyright 2022 Advanced Micro Devices, Inc.
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*/
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#ifndef _rpl_acp6x_OFFSET_HEADER
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#define _rpl_acp6x_OFFSET_HEADER
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/* Registers from ACP_CLKRST block */
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#define ACP_SOFT_RESET 0x1241000
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#define ACP_CONTROL 0x1241004
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#define ACP_STATUS 0x1241008
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#define ACP_DYNAMIC_CG_MASTER_CONTROL 0x1241010
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#define ACP_PGFSM_CONTROL 0x124101C
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#define ACP_PGFSM_STATUS 0x1241020
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#define ACP_CLKMUX_SEL 0x1241024
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/* Registers from ACP_AON block */
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#define ACP_PME_EN 0x1241400
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#define ACP_DEVICE_STATE 0x1241404
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#define AZ_DEVICE_STATE 0x1241408
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#define ACP_PIN_CONFIG 0x1241440
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#define ACP_PAD_PULLUP_CTRL 0x1241444
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#define ACP_PAD_PULLDOWN_CTRL 0x1241448
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#define ACP_PAD_DRIVE_STRENGTH_CTRL 0x124144C
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#define ACP_PAD_SCHMEN_CTRL 0x1241450
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#endif
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