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arm64: dts: ti: j7200-main: Add CPSW5G nodes

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TI's J7200 SoC has a 5 port Ethernet Switch instance with 4 external
ports and 1 host port, referred to as CPSW5G.

Add device-tree nodes for CPSW5G and disable it by default. Device-tree
overlays will be used to enable it.

Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Reviewed-by: Andrew Davis <afd@ti.com>
Link: https://lore.kernel.org/r/20230315062307.1612220-4-s-vadapalli@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
This commit is contained in:
Siddharth Vadapalli
2023-03-15 11:53:06 +05:30
committed by Nishanth Menon
parent 86e7de8bf9
commit d3bac98015
1 changed files with 88 additions and 0 deletions
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88
arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
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@@ -39,6 +39,13 @@ serdes_ln_ctrl: mux-controller@4080 {
<0x4088 0x3>, <0x408c 0x3>; /* SERDES0 lane2/3 select */
};
cpsw0_phy_gmii_sel: phy@4044 {
compatible = "ti,j7200-cpsw5g-phy-gmii-sel";
ti,qsgmii-main-ports = <1>;
reg = <0x4044 0x10>;
#phy-cells = <1>;
};
usb_serdes_mux: mux-controller@4000 {
compatible = "mmio-mux";
#mux-control-cells = <1>;
@@ -304,6 +311,87 @@ cpts@310d0000 {
};
};
cpsw0: ethernet@c000000 {
compatible = "ti,j7200-cpswxg-nuss";
#address-cells = <2>;
#size-cells = <2>;
reg = <0x00 0xc000000 0x00 0x200000>;
reg-names = "cpsw_nuss";
ranges = <0x00 0x00 0x00 0xc000000 0x00 0x200000>;
clocks = <&k3_clks 19 33>;
clock-names = "fck";
power-domains = <&k3_pds 19 TI_SCI_PD_EXCLUSIVE>;
dmas = <&main_udmap 0xca00>,
<&main_udmap 0xca01>,
<&main_udmap 0xca02>,
<&main_udmap 0xca03>,
<&main_udmap 0xca04>,
<&main_udmap 0xca05>,
<&main_udmap 0xca06>,
<&main_udmap 0xca07>,
<&main_udmap 0x4a00>;
dma-names = "tx0", "tx1", "tx2", "tx3",
"tx4", "tx5", "tx6", "tx7",
"rx";
status = "disabled";
ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
cpsw0_port1: port@1 {
reg = <1>;
ti,mac-only;
label = "port1";
status = "disabled";
};
cpsw0_port2: port@2 {
reg = <2>;
ti,mac-only;
label = "port2";
status = "disabled";
};
cpsw0_port3: port@3 {
reg = <3>;
ti,mac-only;
label = "port3";
status = "disabled";
};
cpsw0_port4: port@4 {
reg = <4>;
ti,mac-only;
label = "port4";
status = "disabled";
};
};
cpsw5g_mdio: mdio@f00 {
compatible = "ti,cpsw-mdio","ti,davinci_mdio";
reg = <0x00 0xf00 0x00 0x100>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&k3_clks 19 33>;
clock-names = "fck";
bus_freq = <1000000>;
status = "disabled";
};
cpts@3d000 {
compatible = "ti,j721e-cpts";
reg = <0x00 0x3d000 0x00 0x400>;
clocks = <&k3_clks 19 16>;
clock-names = "cpts";
interrupts-extended = <&gic500 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "cpts";
ti,cpts-ext-ts-inputs = <4>;
ti,cpts-periodic-outputs = <2>;
};
};
main_pmx0: pinctrl@11c000 {
compatible = "pinctrl-single";
/* Proxy 0 addressing */