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Merge tag 'imx-dt64-5.13' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/dt

Browse Source 
i.MX arm64 device tree update for 5.13:

- A series from Dong Aisheng to update i.MX8Q device trees for adopting
  SS (SubSystems) based bindings.
- New board support:  Kontron pitx-imx8m, Engicam i.Core MX8M Mini.
- A series from Adrien Grassein to add various peripheral support for
  imx8mm-nitrogen-r2 board.
- A series from Guido Günther to update librem5-devkit device tree.
- A number of patches from Michael Walle to add Root Complex Event
  Collector interrupt, update MTD partitions and add rtc0 alias for
  ls1028a-kontron-sl28 board.
- Add EQOS MAC support for phyBOARD-Pollux-i.MX8MP.
- Add 2x2 SFP+ cage support for clearfog-itx boards.
- Small and random update for various boards.

* tag 'imx-dt64-5.13' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (55 commits)
  arm64: dts: fsl-ls1028a-kontron-sl28: add rtc0 alias
  arm64: dts: ls1028a: move rtc alias to individual boards
  arm64: dts: fsl-ls1028a-kontron-sl28: combine unused partitions
  arm64: dts: fsl-ls1028a-kontron-sl28: move MTD partitions
  arm64: dts: imx8mp-evk: Improve the Ethernet PHY description
  arm64: dts: imx8mq-librem5-r3: Mark buck3 as always on
  arm64: dts: imx8mq-librem5: Hog the correct gpio
  arm64: dts: lx2160a-clearfog-itx: add SFP support
  arm64: dts: imx8mp-phyboard-pollux-rdk: Change debug UART
  arm64: dts: imx8mn: Reorder flexspi clock-names entry
  arm64: dts: imx8mm: Reorder flexspi clock-names entry
  arm64: dts: ls1028a: set up the real link speed for ENETC port 2
  arm64: dts: imx8mm-nitrogen-r2: add ecspi2 support
  arm64: dts: imx: add imx8qm mek support
  arm64: dts: imx: add imx8qm common dts file
  arm64: dts: imx8qm: add dma ss support
  arm64: dts: imx8: split adma ss into dma and audio ss
  arm64: dts: imx8qm: add conn ss support
  arm64: dts: imx8qm: add lsio ss support
  arm64: dts: imx8: switch to new lpcg clock binding
  ...

Link: https://lore.kernel.org/r/20210331041019.31345-5-shawnguo@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
2021-04-01 21:41:48 +02:00
parent 4f662ba2be 51c8eaa1b7
commit d2adc561c9
41 changed files with 3097 additions and 519 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
arch/arm64/boot/dts/freescale/Makefile
View File

@@ -33,6 +33,8 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2162a-qds.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-beacon-kit.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-ddr4-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-icore-mx8mm-ctouch2.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-icore-mx8mm-edimm2.2.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-kontron-n801x-s.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-nitrogen-r2.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-var-som-symphony.dtb
@@ -47,6 +49,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-rdk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-hummingboard-pulse.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-kontron-pitx-imx8m.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-librem5-devkit.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-librem5-r2.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-librem5-r3.dtb
@@ -57,6 +60,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mq-pico-pi.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-thor96.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-rmb3.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-zest.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8qm-mek.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8qxp-ai_ml.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-eval-v3.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb

70
arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts
View File

@@ -25,6 +25,8 @@ aliases {
spi1 = &dspi2;
mmc0 = &esdhc1;
mmc1 = &esdhc;
rtc0 = &rtc;
rtc1 = &ftm_alarm0;
};
buttons0 {
@@ -115,8 +117,6 @@ &fspi {
status = "okay";
flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
m25p,fast-read;
spi-max-frequency = <133000000>;
@@ -125,49 +125,37 @@ flash@0 {
spi-rx-bus-width = <2>; /* 2 SPI Rx lines */
spi-tx-bus-width = <1>; /* 1 SPI Tx line */
partition@0 {
reg = <0x000000 0x010000>;
label = "rcw";
read-only;
};
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@10000 {
reg = <0x010000 0x0f0000>;
label = "failsafe bootloader";
read-only;
};
partition@0 {
reg = <0x000000 0x010000>;
label = "rcw";
read-only;
};
partition@100000 {
reg = <0x100000 0x040000>;
label = "failsafe DP firmware";
read-only;
};
partition@10000 {
reg = <0x010000 0x1d0000>;
label = "failsafe bootloader";
read-only;
};
partition@140000 {
reg = <0x140000 0x0a0000>;
label = "failsafe trusted firmware";
read-only;
};
partition@200000 {
reg = <0x200000 0x010000>;
label = "configuration store";
};
partition@1e0000 {
reg = <0x1e0000 0x020000>;
label = "reserved";
read-only;
};
partition@210000 {
reg = <0x210000 0x1d0000>;
label = "bootloader";
};
partition@200000 {
reg = <0x200000 0x010000>;
label = "configuration store";
};
partition@210000 {
reg = <0x210000 0x1d0000>;
label = "bootloader";
};
partition@3e0000 {
reg = <0x3e0000 0x020000>;
label = "bootloader environment";
partition@3e0000 {
reg = <0x3e0000 0x020000>;
label = "bootloader environment";
};
};
};
};
@@ -191,7 +179,7 @@ &gpio2 {
&i2c0 {
status = "okay";
rtc@32 {
rtc: rtc@32 {
compatible = "microcrystal,rv8803";
reg = <0x32>;
};

1
arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
View File

@@ -25,6 +25,7 @@ aliases {
serial1 = &duart1;
mmc0 = &esdhc;
mmc1 = &esdhc1;
rtc1 = &ftm_alarm0;
};
chosen {

1
arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
View File

@@ -21,6 +21,7 @@ aliases {
serial1 = &duart1;
mmc0 = &esdhc;
mmc1 = &esdhc1;
rtc1 = &ftm_alarm0;
};
chosen {

12
arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
View File

@@ -18,10 +18,6 @@ / {
#address-cells = <2>;
#size-cells = <2>;
aliases {
rtc1 = &ftm_alarm0;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -1027,7 +1023,7 @@ enetc_port2: ethernet@0,2 {
status = "disabled";
fixed-link {
speed = <1000>;
speed = <2500>;
full-duplex;
};
};
@@ -1114,6 +1110,12 @@ fixed-link {
full-duplex;
};
};
rcec@1f,0 {
reg = <0x00f800 0 0 0 0>;
/* IEP INT_A */
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
};
};
rcpm: power-controller@1e34040 {

24
arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi
View File

@@ -122,6 +122,30 @@ temperature-sensor@48 {
vcc-supply = <&sb_3v3>;
};
};
sfp0_i2c: i2c@4 {
#address-cells = <1>;
#size-cells = <0>;
reg = <4>;
};
sfp1_i2c: i2c@5 {
#address-cells = <1>;
#size-cells = <0>;
reg = <5>;
};
sfp2_i2c: i2c@6 {
#address-cells = <1>;
#size-cells = <0>;
reg = <6>;
};
sfp3_i2c: i2c@7 {
#address-cells = <1>;
#size-cells = <0>;
reg = <7>;
};
};
};

64
arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi
View File

@@ -30,6 +30,54 @@ key {
gpios = <&gpio2 6 GPIO_ACTIVE_LOW>;
};
};
sfp0: sfp-0 {
compatible = "sff,sfp";
i2c-bus = <&sfp0_i2c>;
mod-def0-gpio = <&gpio2 0 GPIO_ACTIVE_LOW>;
maximum-power-milliwatt = <2000>;
};
sfp1: sfp-1 {
compatible = "sff,sfp";
i2c-bus = <&sfp1_i2c>;
mod-def0-gpio = <&gpio2 9 GPIO_ACTIVE_LOW>;
maximum-power-milliwatt = <2000>;
};
sfp2: sfp-2 {
compatible = "sff,sfp";
i2c-bus = <&sfp2_i2c>;
mod-def0-gpio = <&gpio2 10 GPIO_ACTIVE_LOW>;
maximum-power-milliwatt = <2000>;
};
sfp3: sfp-3 {
compatible = "sff,sfp";
i2c-bus = <&sfp3_i2c>;
mod-def0-gpio = <&gpio2 11 GPIO_ACTIVE_LOW>;
maximum-power-milliwatt = <2000>;
};
};
&dpmac7 {
sfp = <&sfp0>;
managed = "in-band-status";
};
&dpmac8 {
sfp = <&sfp1>;
managed = "in-band-status";
};
&dpmac9 {
sfp = <&sfp2>;
managed = "in-band-status";
};
&dpmac10 {
sfp = <&sfp3>;
managed = "in-band-status";
};
&emdio2 {
@@ -44,6 +92,22 @@ &esdhc0 {
status = "okay";
};
&pcs_mdio7 {
status = "okay";
};
&pcs_mdio8 {
status = "okay";
};
&pcs_mdio9 {
status = "okay";
};
&pcs_mdio10 {
status = "okay";
};
&sata0 {
status = "okay";
};

8
arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi Normal file
View File

@@ -0,0 +1,8 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2018-2020 NXP
* Dong Aisheng <aisheng.dong@nxp.com>
*/
#include "imx8-ss-audio.dtsi"
#include "imx8-ss-dma.dtsi"

68
arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi Normal file
View File

@@ -0,0 +1,68 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2018-2019 NXP
* Dong Aisheng <aisheng.dong@nxp.com>
*/
#include <dt-bindings/clock/imx8-lpcg.h>
#include <dt-bindings/firmware/imx/rsrc.h>
audio_subsys: bus@59000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x59000000 0x0 0x59000000 0x1000000>;
audio_ipg_clk: clock-audio-ipg {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <120000000>;
clock-output-names = "audio_ipg_clk";
};
dsp_lpcg: clock-controller@59580000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x59580000 0x10000>;
#clock-cells = <1>;
clocks = <&audio_ipg_clk>,
<&audio_ipg_clk>,
<&audio_ipg_clk>;
clock-indices = <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
<IMX_LPCG_CLK_7>;
clock-output-names = "dsp_lpcg_adb_clk",
"dsp_lpcg_ipg_clk",
"dsp_lpcg_core_clk";
power-domains = <&pd IMX_SC_R_DSP>;
};
dsp_ram_lpcg: clock-controller@59590000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x59590000 0x10000>;
#clock-cells = <1>;
clocks = <&audio_ipg_clk>;
clock-indices = <IMX_LPCG_CLK_4>;
clock-output-names = "dsp_ram_lpcg_ipg_clk";
power-domains = <&pd IMX_SC_R_DSP_RAM>;
};
dsp: dsp@596e8000 {
compatible = "fsl,imx8qxp-dsp";
reg = <0x596e8000 0x88000>;
clocks = <&dsp_lpcg IMX_LPCG_CLK_5>,
<&dsp_ram_lpcg IMX_LPCG_CLK_4>,
<&dsp_lpcg IMX_LPCG_CLK_7>;
clock-names = "ipg", "ocram", "core";
power-domains = <&pd IMX_SC_R_MU_13A>,
<&pd IMX_SC_R_MU_13B>,
<&pd IMX_SC_R_DSP>,
<&pd IMX_SC_R_DSP_RAM>;
mbox-names = "txdb0", "txdb1",
"rxdb0", "rxdb1";
mboxes = <&lsio_mu13 2 0>,
<&lsio_mu13 2 1>,
<&lsio_mu13 3 0>,
<&lsio_mu13 3 1>;
memory-region = <&dsp_reserved>;
status = "disabled";
};
};

184
arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi Normal file
View File

@@ -0,0 +1,184 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2018-2019 NXP
* Dong Aisheng <aisheng.dong@nxp.com>
*/
#include <dt-bindings/clock/imx8-lpcg.h>
#include <dt-bindings/firmware/imx/rsrc.h>
conn_subsys: bus@5b000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x5b000000 0x0 0x5b000000 0x1000000>;
conn_axi_clk: clock-conn-axi {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <333333333>;
clock-output-names = "conn_axi_clk";
};
conn_ahb_clk: clock-conn-ahb {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <166666666>;
clock-output-names = "conn_ahb_clk";
};
conn_ipg_clk: clock-conn-ipg {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <83333333>;
clock-output-names = "conn_ipg_clk";
};
usdhc1: mmc@5b010000 {
interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x5b010000 0x10000>;
clocks = <&sdhc0_lpcg IMX_LPCG_CLK_4>,
<&sdhc0_lpcg IMX_LPCG_CLK_5>,
<&sdhc0_lpcg IMX_LPCG_CLK_0>;
clock-names = "ipg", "per", "ahb";
power-domains = <&pd IMX_SC_R_SDHC_0>;
status = "disabled";
};
usdhc2: mmc@5b020000 {
interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x5b020000 0x10000>;
clocks = <&sdhc1_lpcg IMX_LPCG_CLK_4>,
<&sdhc1_lpcg IMX_LPCG_CLK_5>,
<&sdhc1_lpcg IMX_LPCG_CLK_0>;
clock-names = "ipg", "per", "ahb";
power-domains = <&pd IMX_SC_R_SDHC_1>;
fsl,tuning-start-tap = <20>;
fsl,tuning-step= <2>;
status = "disabled";
};
usdhc3: mmc@5b030000 {
interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x5b030000 0x10000>;
clocks = <&sdhc2_lpcg IMX_LPCG_CLK_4>,
<&sdhc2_lpcg IMX_LPCG_CLK_5>,
<&sdhc2_lpcg IMX_LPCG_CLK_0>;
clock-names = "ipg", "per", "ahb";
power-domains = <&pd IMX_SC_R_SDHC_2>;
status = "disabled";
};
fec1: ethernet@5b040000 {
reg = <0x5b040000 0x10000>;
interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&enet0_lpcg IMX_LPCG_CLK_4>,
<&enet0_lpcg IMX_LPCG_CLK_2>,
<&enet0_lpcg IMX_LPCG_CLK_1>,
<&enet0_lpcg IMX_LPCG_CLK_0>;
clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";
fsl,num-tx-queues=<3>;
fsl,num-rx-queues=<3>;
power-domains = <&pd IMX_SC_R_ENET_0>;
status = "disabled";
};
fec2: ethernet@5b050000 {
reg = <0x5b050000 0x10000>;
interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&enet1_lpcg IMX_LPCG_CLK_4>,
<&enet1_lpcg IMX_LPCG_CLK_2>,
<&enet1_lpcg IMX_LPCG_CLK_1>,
<&enet1_lpcg IMX_LPCG_CLK_0>;
clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";
fsl,num-tx-queues=<3>;
fsl,num-rx-queues=<3>;
power-domains = <&pd IMX_SC_R_ENET_1>;
status = "disabled";
};
/* LPCG clocks */
sdhc0_lpcg: clock-controller@5b200000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5b200000 0x10000>;
#clock-cells = <1>;
clocks = <&clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER>,
<&conn_ipg_clk>, <&conn_axi_clk>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>,
<IMX_LPCG_CLK_5>;
clock-output-names = "sdhc0_lpcg_per_clk",
"sdhc0_lpcg_ipg_clk",
"sdhc0_lpcg_ahb_clk";
power-domains = <&pd IMX_SC_R_SDHC_0>;
};
sdhc1_lpcg: clock-controller@5b210000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5b210000 0x10000>;
#clock-cells = <1>;
clocks = <&clk IMX_SC_R_SDHC_1 IMX_SC_PM_CLK_PER>,
<&conn_ipg_clk>, <&conn_axi_clk>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>,
<IMX_LPCG_CLK_5>;
clock-output-names = "sdhc1_lpcg_per_clk",
"sdhc1_lpcg_ipg_clk",
"sdhc1_lpcg_ahb_clk";
power-domains = <&pd IMX_SC_R_SDHC_1>;
};
sdhc2_lpcg: clock-controller@5b220000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5b220000 0x10000>;
#clock-cells = <1>;
clocks = <&clk IMX_SC_R_SDHC_2 IMX_SC_PM_CLK_PER>,
<&conn_ipg_clk>, <&conn_axi_clk>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>,
<IMX_LPCG_CLK_5>;
clock-output-names = "sdhc2_lpcg_per_clk",
"sdhc2_lpcg_ipg_clk",
"sdhc2_lpcg_ahb_clk";
power-domains = <&pd IMX_SC_R_SDHC_2>;
};
enet0_lpcg: clock-controller@5b230000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5b230000 0x10000>;
#clock-cells = <1>;
clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>,
<&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>,
<&conn_axi_clk>, <&conn_ipg_clk>, <&conn_ipg_clk>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
<IMX_LPCG_CLK_2>, <IMX_LPCG_CLK_4>,
<IMX_LPCG_CLK_5>;
clock-output-names = "enet0_ipg_root_clk",
"enet0_tx_clk",
"enet0_ahb_clk",
"enet0_ipg_clk",
"enet0_ipg_s_clk";
power-domains = <&pd IMX_SC_R_ENET_0>;
};
enet1_lpcg: clock-controller@5b240000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5b240000 0x10000>;
#clock-cells = <1>;
clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>,
<&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>,
<&conn_axi_clk>, <&conn_ipg_clk>, <&conn_ipg_clk>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
<IMX_LPCG_CLK_2>, <IMX_LPCG_CLK_4>,
<IMX_LPCG_CLK_5>;
clock-output-names = "enet1_ipg_root_clk",
"enet1_tx_clk",
"enet1_ahb_clk",
"enet1_ipg_clk",
"enet1_ipg_s_clk";
power-domains = <&pd IMX_SC_R_ENET_1>;
};
};

18
arch/arm64/boot/dts/freescale/imx8-ss-ddr.dtsi Normal file
View File

@@ -0,0 +1,18 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2019-2020 NXP
* Dong Aisheng <aisheng.dong@nxp.com>
*/
ddr_subsys: bus@5c000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x5c000000 0x0 0x5c000000 0x1000000>;
ddr-pmu@5c020000 {
compatible = "fsl,imx8-ddr-pmu";
reg = <0x5c020000 0x10000>;
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
};
};

202
arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi Normal file
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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2018-2019 NXP
* Dong Aisheng <aisheng.dong@nxp.com>
*/
#include <dt-bindings/clock/imx8-lpcg.h>
#include <dt-bindings/firmware/imx/rsrc.h>
dma_subsys: bus@5a000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x5a000000 0x0 0x5a000000 0x1000000>;
dma_ipg_clk: clock-dma-ipg {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <120000000>;
clock-output-names = "dma_ipg_clk";
};
lpuart0: serial@5a060000 {
reg = <0x5a060000 0x1000>;
interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&uart0_lpcg IMX_LPCG_CLK_4>,
<&uart0_lpcg IMX_LPCG_CLK_0>;
clock-names = "ipg", "baud";
power-domains = <&pd IMX_SC_R_UART_0>;
status = "disabled";
};
lpuart1: serial@5a070000 {
reg = <0x5a070000 0x1000>;
interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&uart1_lpcg IMX_LPCG_CLK_4>,
<&uart1_lpcg IMX_LPCG_CLK_0>;
clock-names = "ipg", "baud";
power-domains = <&pd IMX_SC_R_UART_1>;
status = "disabled";
};
lpuart2: serial@5a080000 {
reg = <0x5a080000 0x1000>;
interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&uart2_lpcg IMX_LPCG_CLK_4>,
<&uart2_lpcg IMX_LPCG_CLK_0>;
clock-names = "ipg", "baud";
power-domains = <&pd IMX_SC_R_UART_2>;
status = "disabled";
};
lpuart3: serial@5a090000 {
reg = <0x5a090000 0x1000>;
interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&uart3_lpcg IMX_LPCG_CLK_4>,
<&uart3_lpcg IMX_LPCG_CLK_0>;
clock-names = "ipg", "baud";
power-domains = <&pd IMX_SC_R_UART_3>;
status = "disabled";
};
uart0_lpcg: clock-controller@5a460000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5a460000 0x10000>;
#clock-cells = <1>;
clocks = <&clk IMX_SC_R_UART_0 IMX_SC_PM_CLK_PER>,
<&dma_ipg_clk>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
clock-output-names = "uart0_lpcg_baud_clk",
"uart0_lpcg_ipg_clk";
power-domains = <&pd IMX_SC_R_UART_0>;
};
uart1_lpcg: clock-controller@5a470000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5a470000 0x10000>;
#clock-cells = <1>;
clocks = <&clk IMX_SC_R_UART_1 IMX_SC_PM_CLK_PER>,
<&dma_ipg_clk>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
clock-output-names = "uart1_lpcg_baud_clk",
"uart1_lpcg_ipg_clk";
power-domains = <&pd IMX_SC_R_UART_1>;
};
uart2_lpcg: clock-controller@5a480000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5a480000 0x10000>;
#clock-cells = <1>;
clocks = <&clk IMX_SC_R_UART_2 IMX_SC_PM_CLK_PER>,
<&dma_ipg_clk>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
clock-output-names = "uart2_lpcg_baud_clk",
"uart2_lpcg_ipg_clk";
power-domains = <&pd IMX_SC_R_UART_2>;
};
uart3_lpcg: clock-controller@5a490000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5a490000 0x10000>;
#clock-cells = <1>;
clocks = <&clk IMX_SC_R_UART_3 IMX_SC_PM_CLK_PER>,
<&dma_ipg_clk>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
clock-output-names = "uart3_lpcg_baud_clk",
"uart3_lpcg_ipg_clk";
power-domains = <&pd IMX_SC_R_UART_3>;
};
i2c0: i2c@5a800000 {
reg = <0x5a800000 0x4000>;
interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&i2c0_lpcg IMX_LPCG_CLK_0>;
clock-names = "per";
assigned-clocks = <&clk IMX_SC_R_I2C_0 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <24000000>;
power-domains = <&pd IMX_SC_R_I2C_0>;
status = "disabled";
};
i2c1: i2c@5a810000 {
reg = <0x5a810000 0x4000>;
interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&i2c1_lpcg IMX_LPCG_CLK_0>;
clock-names = "per";
assigned-clocks = <&clk IMX_SC_R_I2C_1 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <24000000>;
power-domains = <&pd IMX_SC_R_I2C_1>;
status = "disabled";
};
i2c2: i2c@5a820000 {
reg = <0x5a820000 0x4000>;
interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&i2c2_lpcg IMX_LPCG_CLK_0>;
clock-names = "per";
assigned-clocks = <&clk IMX_SC_R_I2C_2 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <24000000>;
power-domains = <&pd IMX_SC_R_I2C_2>;
status = "disabled";
};
i2c3: i2c@5a830000 {
reg = <0x5a830000 0x4000>;
interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&i2c3_lpcg IMX_LPCG_CLK_0>;
clock-names = "per";
assigned-clocks = <&clk IMX_SC_R_I2C_3 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <24000000>;
power-domains = <&pd IMX_SC_R_I2C_3>;
status = "disabled";
};
i2c0_lpcg: clock-controller@5ac00000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5ac00000 0x10000>;
#clock-cells = <1>;
clocks = <&clk IMX_SC_R_I2C_0 IMX_SC_PM_CLK_PER>,
<&dma_ipg_clk>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
clock-output-names = "i2c0_lpcg_clk",
"i2c0_lpcg_ipg_clk";
power-domains = <&pd IMX_SC_R_I2C_0>;
};
i2c1_lpcg: clock-controller@5ac10000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5ac10000 0x10000>;
#clock-cells = <1>;
clocks = <&clk IMX_SC_R_I2C_1 IMX_SC_PM_CLK_PER>,
<&dma_ipg_clk>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
clock-output-names = "i2c1_lpcg_clk",
"i2c1_lpcg_ipg_clk";
power-domains = <&pd IMX_SC_R_I2C_1>;
};
i2c2_lpcg: clock-controller@5ac20000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5ac20000 0x10000>;
#clock-cells = <1>;
clocks = <&clk IMX_SC_R_I2C_2 IMX_SC_PM_CLK_PER>,
<&dma_ipg_clk>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
clock-output-names = "i2c2_lpcg_clk",
"i2c2_lpcg_ipg_clk";
power-domains = <&pd IMX_SC_R_I2C_2>;
};
i2c3_lpcg: clock-controller@5ac30000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5ac30000 0x10000>;
#clock-cells = <1>;
clocks = <&clk IMX_SC_R_I2C_3 IMX_SC_PM_CLK_PER>,
<&dma_ipg_clk>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
clock-output-names = "i2c3_lpcg_clk",
"i2c3_lpcg_ipg_clk";
power-domains = <&pd IMX_SC_R_I2C_3>;
};
};

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arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi Normal file
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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2018-2020 NXP
* Dong Aisheng <aisheng.dong@nxp.com>
*/
#include <dt-bindings/clock/imx8-lpcg.h>
#include <dt-bindings/firmware/imx/rsrc.h>
lsio_subsys: bus@5d000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x5d000000 0x0 0x5d000000 0x1000000>;
lsio_mem_clk: clock-lsio-mem {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <200000000>;
clock-output-names = "lsio_mem_clk";
};
lsio_bus_clk: clock-lsio-bus {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
clock-output-names = "lsio_bus_clk";
};
lsio_gpio0: gpio@5d080000 {
reg = <0x5d080000 0x10000>;
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
power-domains = <&pd IMX_SC_R_GPIO_0>;
};
lsio_gpio1: gpio@5d090000 {
reg = <0x5d090000 0x10000>;
interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
power-domains = <&pd IMX_SC_R_GPIO_1>;
};
lsio_gpio2: gpio@5d0a0000 {
reg = <0x5d0a0000 0x10000>;
interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
power-domains = <&pd IMX_SC_R_GPIO_2>;
};
lsio_gpio3: gpio@5d0b0000 {
reg = <0x5d0b0000 0x10000>;
interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
power-domains = <&pd IMX_SC_R_GPIO_3>;
};
lsio_gpio4: gpio@5d0c0000 {
reg = <0x5d0c0000 0x10000>;
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
power-domains = <&pd IMX_SC_R_GPIO_4>;
};
lsio_gpio5: gpio@5d0d0000 {
reg = <0x5d0d0000 0x10000>;
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
power-domains = <&pd IMX_SC_R_GPIO_5>;
};
lsio_gpio6: gpio@5d0e0000 {
reg = <0x5d0e0000 0x10000>;
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
power-domains = <&pd IMX_SC_R_GPIO_6>;
};
lsio_gpio7: gpio@5d0f0000 {
reg = <0x5d0f0000 0x10000>;
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
power-domains = <&pd IMX_SC_R_GPIO_7>;
};
lsio_mu0: mailbox@5d1b0000 {
reg = <0x5d1b0000 0x10000>;
interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <2>;
status = "disabled";
};
lsio_mu1: mailbox@5d1c0000 {
reg = <0x5d1c0000 0x10000>;
interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <2>;
};
lsio_mu2: mailbox@5d1d0000 {
reg = <0x5d1d0000 0x10000>;
interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <2>;
status = "disabled";
};
lsio_mu3: mailbox@5d1e0000 {
reg = <0x5d1e0000 0x10000>;
interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <2>;
status = "disabled";
};
lsio_mu4: mailbox@5d1f0000 {
reg = <0x5d1f0000 0x10000>;
interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <2>;
status = "disabled";
};
lsio_mu13: mailbox@5d280000 {
reg = <0x5d280000 0x10000>;
interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <2>;
power-domains = <&pd IMX_SC_R_MU_13A>;
};
/* LPCG clocks */
pwm0_lpcg: clock-controller@5d400000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5d400000 0x10000>;
#clock-cells = <1>;
clocks = <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>,
<&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>,
<&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>,
<&lsio_bus_clk>,
<&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
<IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
<IMX_LPCG_CLK_6>;
clock-output-names = "pwm0_lpcg_ipg_clk",
"pwm0_lpcg_ipg_hf_clk",
"pwm0_lpcg_ipg_s_clk",
"pwm0_lpcg_ipg_slv_clk",
"pwm0_lpcg_ipg_mstr_clk";
power-domains = <&pd IMX_SC_R_PWM_0>;
};
pwm1_lpcg: clock-controller@5d410000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5d410000 0x10000>;
#clock-cells = <1>;
clocks = <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>,
<&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>,
<&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>,
<&lsio_bus_clk>,
<&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
<IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
<IMX_LPCG_CLK_6>;
clock-output-names = "pwm1_lpcg_ipg_clk",
"pwm1_lpcg_ipg_hf_clk",
"pwm1_lpcg_ipg_s_clk",
"pwm1_lpcg_ipg_slv_clk",
"pwm1_lpcg_ipg_mstr_clk";
power-domains = <&pd IMX_SC_R_PWM_1>;
};
pwm2_lpcg: clock-controller@5d420000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5d420000 0x10000>;
#clock-cells = <1>;
clocks = <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>,
<&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>,
<&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>,
<&lsio_bus_clk>,
<&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
<IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
<IMX_LPCG_CLK_6>;
clock-output-names = "pwm2_lpcg_ipg_clk",
"pwm2_lpcg_ipg_hf_clk",
"pwm2_lpcg_ipg_s_clk",
"pwm2_lpcg_ipg_slv_clk",
"pwm2_lpcg_ipg_mstr_clk";
power-domains = <&pd IMX_SC_R_PWM_2>;
};
pwm3_lpcg: clock-controller@5d430000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5d430000 0x10000>;
#clock-cells = <1>;
clocks = <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>,
<&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>,
<&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>,
<&lsio_bus_clk>,
<&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
<IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
<IMX_LPCG_CLK_6>;
clock-output-names = "pwm3_lpcg_ipg_clk",
"pwm3_lpcg_ipg_hf_clk",
"pwm3_lpcg_ipg_s_clk",
"pwm3_lpcg_ipg_slv_clk",
"pwm3_lpcg_ipg_mstr_clk";
power-domains = <&pd IMX_SC_R_PWM_3>;
};
pwm4_lpcg: clock-controller@5d440000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5d440000 0x10000>;
#clock-cells = <1>;
clocks = <&clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER>,
<&clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER>,
<&clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER>,
<&lsio_bus_clk>,
<&clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
<IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
<IMX_LPCG_CLK_6>;
clock-output-names = "pwm4_lpcg_ipg_clk",
"pwm4_lpcg_ipg_hf_clk",
"pwm4_lpcg_ipg_s_clk",
"pwm4_lpcg_ipg_slv_clk",
"pwm4_lpcg_ipg_mstr_clk";
power-domains = <&pd IMX_SC_R_PWM_4>;
};
pwm5_lpcg: clock-controller@5d450000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5d450000 0x10000>;
#clock-cells = <1>;
clocks = <&clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER>,
<&clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER>,
<&clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER>,
<&lsio_bus_clk>,
<&clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
<IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
<IMX_LPCG_CLK_6>;
clock-output-names = "pwm5_lpcg_ipg_clk",
"pwm5_lpcg_ipg_hf_clk",
"pwm5_lpcg_ipg_s_clk",
"pwm5_lpcg_ipg_slv_clk",
"pwm5_lpcg_ipg_mstr_clk";
power-domains = <&pd IMX_SC_R_PWM_5>;
};
pwm6_lpcg: clock-controller@5d460000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5d460000 0x10000>;
#clock-cells = <1>;
clocks = <&clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER>,
<&clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER>,
<&clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER>,
<&lsio_bus_clk>,
<&clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
<IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
<IMX_LPCG_CLK_6>;
clock-output-names = "pwm6_lpcg_ipg_clk",
"pwm6_lpcg_ipg_hf_clk",
"pwm6_lpcg_ipg_s_clk",
"pwm6_lpcg_ipg_slv_clk",
"pwm6_lpcg_ipg_mstr_clk";
power-domains = <&pd IMX_SC_R_PWM_6>;
};
pwm7_lpcg: clock-controller@5d470000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5d470000 0x10000>;
#clock-cells = <1>;
clocks = <&clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER>,
<&clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER>,
<&clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER>,
<&lsio_bus_clk>,
<&clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
<IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
<IMX_LPCG_CLK_6>;
clock-output-names = "pwm7_lpcg_ipg_clk",
"pwm7_lpcg_ipg_hf_clk",
"pwm7_lpcg_ipg_s_clk",
"pwm7_lpcg_ipg_slv_clk",
"pwm7_lpcg_ipg_mstr_clk";
power-domains = <&pd IMX_SC_R_PWM_7>;
};
};

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arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm-ctouch2.dts Normal file
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2019 NXP
* Copyright (c) 2019 Engicam srl
* Copyright (c) 2020 Amarula Solutions(India)
*/
/dts-v1/;
#include "imx8mm.dtsi"
#include "imx8mm-icore-mx8mm.dtsi"
/ {
model = "Engicam i.Core MX8M Mini C.TOUCH 2.0";
compatible = "engicam,icore-mx8mm-ctouch2", "engicam,icore-mx8mm",
"fsl,imx8mm";
chosen {
stdout-path = &uart2;
};
};
&fec1 {
status = "okay";
};
&i2c2 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
};
&i2c4 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4>;
status = "okay";
};
&iomuxc {
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
>;
};
pinctrl_usdhc1_gpio: usdhc1gpiogrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x41
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
>;
};
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
/* SD */
&usdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>;
cd-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
max-frequency = <50000000>;
bus-width = <4>;
no-1-8-v;
pm-ignore-notify;
keep-power-in-suspend;
status = "okay";
};

97
arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm-edimm2.2.dts Normal file
View File

@@ -0,0 +1,97 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2019 NXP
* Copyright (c) 2019 Engicam srl
* Copyright (c) 2020 Amarula Solutions(India)
*/
/dts-v1/;
#include "imx8mm.dtsi"
#include "imx8mm-icore-mx8mm.dtsi"
/ {
model = "Engicam i.Core MX8M Mini EDIMM2.2 Starter Kit";
compatible = "engicam,icore-mx8mm-edimm2.2", "engicam,icore-mx8mm",
"fsl,imx8mm";
chosen {
stdout-path = &uart2;
};
};
&fec1 {
status = "okay";
};
&i2c2 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
};
&i2c4 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4>;
status = "okay";
};
&iomuxc {
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
>;
};
pinctrl_usdhc1_gpio: usdhc1gpiogrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x41
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
>;
};
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
/* SD */
&usdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>;
cd-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
max-frequency = <50000000>;
bus-width = <4>;
no-1-8-v;
pm-ignore-notify;
keep-power-in-suspend;
status = "okay";
};

232
arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm.dtsi Normal file
View File

@@ -0,0 +1,232 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2018 NXP
* Copyright (c) 2019 Engicam srl
* Copyright (c) 2020 Amarula Solutons(India)
*/
/ {
compatible = "engicam,icore-mx8mm", "fsl,imx8mm";
};
&A53_0 {
cpu-supply = <&reg_buck4>;
};
&A53_1 {
cpu-supply = <&reg_buck4>;
};
&A53_2 {
cpu-supply = <&reg_buck4>;
};
&A53_3 {
cpu-supply = <&reg_buck4>;
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy: ethernet-phy@3 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <3>;
reset-gpios = <&gpio3 7 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
};
};
};
&i2c1 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
pmic@8 {
compatible = "nxp,pf8121a";
reg = <0x08>;
regulators {
reg_ldo1: ldo1 {
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
regulator-boot-on;
};
reg_ldo2: ldo2 {
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
regulator-boot-on;
};
reg_ldo3: ldo3 {
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
regulator-boot-on;
};
reg_ldo4: ldo4 {
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
regulator-boot-on;
};
reg_buck1: buck1 {
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
reg_buck2: buck2 {
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
reg_buck3: buck3 {
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
reg_buck4: buck4 {
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
reg_buck5: buck5 {
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
reg_buck6: buck6 {
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
reg_buck7: buck7 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
};
reg_vsnvs: vsnvs {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
};
};
};
};
&iomuxc {
pinctrl_fec1: fec1grp {
fsl,pins = <
MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7 0x19
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
>;
};
pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
>;
};
pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
>;
};
};
/* eMMC */
&usdhc3 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
bus-width = <8>;
non-removable;
status = "okay";
};

314
arch/arm64/boot/dts/freescale/imx8mm-nitrogen-r2.dts
View File

@@ -9,6 +9,53 @@
/ {
model = "Boundary Devices i.MX8MMini Nitrogen8MM Rev2";
compatible = "boundary,imx8mm-nitrogen8mm", "fsl,imx8mm";
reg_vref_1v8: regulator-vref-1v8 {
compatible = "regulator-fixed";
regulator-name = "vref-1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
reg_vref_3v3: regulator-vref-3v3 {
compatible = "regulator-fixed";
regulator-name = "vref-3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
reg_wlan_vmmc: regulator-wlan-vmmc {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_wlan_vmmc>;
regulator-name = "reg_wlan_vmmc";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio3 20 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
sound-wm8960 {
audio-cpu = <&sai1>;
audio-codec = <&wm8960>;
audio-routing =
"Headphone Jack", "HP_L",
"Headphone Jack", "HP_R",
"Ext Spk", "SPK_LP",
"Ext Spk", "SPK_LN",
"Ext Spk", "SPK_RP",
"Ext Spk", "SPK_RN",
"RINPUT1", "Mic Jack",
"Mic Jack", "MICB";
compatible = "fsl,imx-audio-wm8960";
/* JD2: hp detect high for headphone*/
hp-det-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;
/* Jack is not stuffed */
mic-det-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
model = "wm8960-audio";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sound_wm8960>;
};
};
&A53_0 {
@@ -27,6 +74,17 @@ &A53_3 {
cpu-supply = <&reg_buck3>;
};
/* J15 */
&ecspi2 {
assigned-clocks = <&clk IMX8MM_CLK_ECSPI2>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_40M>;
assigned-clock-rates = <40000000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi2>;
cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
status = "okay";
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;
@@ -47,6 +105,12 @@ ethphy0: ethernet-phy@4 {
};
};
&flexspi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexspi>;
status = "okay";
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
@@ -156,7 +220,7 @@ i2cmux@70 {
#address-cells = <1>;
#size-cells = <0>;
i2c3 {
i2c3@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
@@ -173,12 +237,88 @@ rtc@68 {
};
};
&i2c4 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4>;
status = "okay";
wm8960: codec@1a {
compatible = "wlf,wm8960";
reg = <0x1a>;
clocks = <&clk IMX8MM_CLK_SAI1_ROOT>;
clock-names = "mclk1";
wlf,shared-lrclk;
#sound-dai-cells = <0>;
};
};
&pwm1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
status = "okay";
};
&pwm2 {
assigned-clocks = <&clk IMX8MM_CLK_PWM2>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_40M>;
assigned-clock-rates = <40000000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm2>;
status = "okay";
};
&pwm3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm3>;
status = "okay";
};
&pwm4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm4>;
status = "okay";
};
&sai1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai1>;
status = "okay";
};
&sai2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai2>;
status = "okay";
};
/* BT */
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
uart-has-rtscts;
status = "okay";
};
/* console */
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
assigned-clocks = <&clk IMX8MM_CLK_UART2>;
assigned-clock-parents = <&clk IMX8MM_CLK_24M>;
status = "okay";
};
/* J15 */
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
uart-has-rtscts;
status = "okay";
};
/* J9 */
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4>;
status = "okay";
};
@@ -191,6 +331,8 @@ &usdhc1 {
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
vmmc-supply = <&reg_vref_3v3>;
vqmmc-supply = <&reg_vref_1v8>;
status = "okay";
};
@@ -206,6 +348,48 @@ &usdhc2 {
status = "okay";
};
/* wlan */
&usdhc3 {
bus-width = <4>;
sdhci-caps-mask = <0x2 0x0>;
non-removable;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
vmmc-supply = <&reg_wlan_vmmc>;
vqmmc-supply = <&reg_vref_1v8>;
status = "okay";
};
/* USB OTG port */
&usbotg1 {
dr_mode = "otg";
over-current-active-low;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg1>;
power-active-high;
status = "okay";
};
/* USB Host port */
&usbotg2 {
dr_mode = "host";
over-current-active-low;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg2>;
power-active-high;
/*
* FIXME: having USB2 enabled hangs the boot just after:
*[ 1.655941] ci_hdrc ci_hdrc.1: EHCI Host Controller
*[ 1.660880] ci_hdrc ci_hdrc.1: new USB bus registered, assigned bus number 2
*[ 1.681505] ci_hdrc ci_hdrc.1: USB 2.0 started, EHCI 1.00
*[ 1.687730] hub 2-0:1.0: USB hub found
*[ 1.691528] hub 2-0:1.0: 1 port detected
*/
status = "disabled";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
@@ -217,6 +401,15 @@ &iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
pinctrl_ecspi2: ecspi2grp {
fsl,pins = <
MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x140
MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x19
MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x19
MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x19
>;
};
pinctrl_fec1: fec1grp {
fsl,pins = <
MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
@@ -237,6 +430,17 @@ MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x159
>;
};
pinctrl_flexspi: flexspigrp {
fsl,pins = <
MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2
MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
>;
};
pinctrl_hog: hoggrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x09
@@ -258,12 +462,86 @@ MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3
>;
};
pinctrl_i2c3a_rv4162: i2c3a-rv4162grp {
fsl,pins = <
MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x1c0
>;
};
pinctrl_pwm1: pwm1grp {
fsl,pins = <
MX8MM_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x16
>;
};
pinctrl_pwm2: pwm2grp {
fsl,pins = <
MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT 0x16
>;
};
pinctrl_pwm3: pwm3grp {
fsl,pins = <
MX8MM_IOMUXC_SPDIF_TX_PWM3_OUT 0x16
>;
};
pinctrl_pwm4: pwm4grp {
fsl,pins = <
MX8MM_IOMUXC_SAI3_MCLK_PWM4_OUT 0x16
>;
};
pinctrl_reg_wlan_vmmc: reg-wlan-vmmcgrp {
fsl,pins = <
MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x16
>;
};
pinctrl_sai1: sai1grp {
fsl,pins = <
/* wm8960 */
MX8MM_IOMUXC_SAI1_MCLK_SAI1_MCLK 0xd6
MX8MM_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6
MX8MM_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6
MX8MM_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6
MX8MM_IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0xd6
>;
};
pinctrl_sai2: sai2grp {
fsl,pins = <
/* Bluetooth PCM */
MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6
MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6
MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6
MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6
>;
};
pinctrl_sound_wm8960: sound-wm8960grp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x80
MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x80
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
MX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140
MX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
@@ -271,6 +549,36 @@ MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x140
MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x140
MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x140
MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x140
>;
};
pinctrl_uart4: uart4grp {
fsl,pins = <
MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140
MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140
>;
};
pinctrl_usbotg1: usbotg1grp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x16
MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x156
>;
};
pinctrl_usbotg2: usbotg2grp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x16
MX8MM_IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x15
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190

2
arch/arm64/boot/dts/freescale/imx8mm.dtsi
View File

@@ -887,7 +887,7 @@ flexspi: spi@30bb0000 {
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MM_CLK_QSPI_ROOT>,
<&clk IMX8MM_CLK_QSPI_ROOT>;
clock-names = "fspi", "fspi_en";
clock-names = "fspi_en", "fspi";
status = "disabled";
};

6
arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi
View File

@@ -262,8 +262,12 @@ bluetooth {
&usdhc1 {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
vmmc-supply = <&buck4_reg>;
vqmmc-supply = <&buck5_reg>;
bus-width = <4>;
non-removable;
cap-power-off-card;

2
arch/arm64/boot/dts/freescale/imx8mn.dtsi
View File

@@ -898,7 +898,7 @@ flexspi: spi@30bb0000 {
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MN_CLK_QSPI_ROOT>,
<&clk IMX8MN_CLK_QSPI_ROOT>;
clock-names = "fspi", "fspi_en";
clock-names = "fspi_en", "fspi";
status = "disabled";
};

2
arch/arm64/boot/dts/freescale/imx8mp-evk.dts
View File

@@ -98,6 +98,8 @@ ethphy1: ethernet-phy@1 {
reg = <1>;
eee-broken-1000t;
reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
reset-deassert-us = <80000>;
};
};
};

56
arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts
View File

@@ -16,7 +16,7 @@ / {
"phytec,imx8mp-phycore-som", "fsl,imx8mp";
chosen {
stdout-path = &uart2;
stdout-path = &uart1;
};
reg_usdhc2_vmmc: regulator-usdhc2 {
@@ -33,6 +33,30 @@ reg_usdhc2_vmmc: regulator-usdhc2 {
};
};
&eqos {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_eqos>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy0>;
status = "okay";
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x1>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
enet-phy-lane-no-swap;
};
};
};
&i2c2 {
clock-frequency = <400000>;
pinctrl-names = "default";
@@ -71,9 +95,9 @@ &snvs_pwrkey {
};
/* debug console */
&uart2 {
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
@@ -90,6 +114,26 @@ &usdhc2 {
};
&iomuxc {
pinctrl_eqos: eqosgrp {
fsl,pins = <
MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3
MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3
MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91
MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91
MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91
MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91
MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91
MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91
MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f
MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f
MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f
MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f
MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f
MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f
MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x10
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c3
@@ -110,10 +154,10 @@ MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41
>;
};
pinctrl_uart2: uart2grp {
pinctrl_uart1: uart1grp {
fsl,pins = <
MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x49
MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x49
MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x49
MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x49
>;
};

39
arch/arm64/boot/dts/freescale/imx8mp.dtsi
View File

@@ -18,6 +18,7 @@ / {
aliases {
ethernet0 = &fec;
ethernet1 = &eqos;
gpio0 = &gpio1;
gpio1 = &gpio2;
gpio2 = &gpio3;
@@ -312,6 +313,22 @@ wdog1: watchdog@30280000 {
status = "disabled";
};
wdog2: watchdog@30290000 {
compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";
reg = <0x30290000 0x10000>;
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_WDOG2_ROOT>;
status = "disabled";
};
wdog3: watchdog@302a0000 {
compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";
reg = <0x302a0000 0x10000>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_WDOG3_ROOT>;
status = "disabled";
};
iomuxc: pinctrl@30330000 {
compatible = "fsl,imx8mp-iomuxc";
reg = <0x30330000 0x10000>;
@@ -786,6 +803,28 @@ fec: ethernet@30be0000 {
nvmem_macaddr_swap;
status = "disabled";
};
eqos: ethernet@30bf0000 {
compatible = "nxp,imx8mp-dwmac-eqos", "snps,dwmac-5.10a";
reg = <0x30bf0000 0x10000>;
interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "eth_wake_irq", "macirq";
clocks = <&clk IMX8MP_CLK_ENET_QOS_ROOT>,
<&clk IMX8MP_CLK_QOS_ENET_ROOT>,
<&clk IMX8MP_CLK_ENET_QOS_TIMER>,
<&clk IMX8MP_CLK_ENET_QOS>;
clock-names = "stmmaceth", "pclk", "ptp_ref", "tx";
assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>,
<&clk IMX8MP_CLK_ENET_QOS_TIMER>,
<&clk IMX8MP_CLK_ENET_QOS>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
<&clk IMX8MP_SYS_PLL2_100M>,
<&clk IMX8MP_SYS_PLL2_125M>;
assigned-clock-rates = <0>, <100000000>, <125000000>;
intf_mode = <&gpr 0x4>;
status = "disabled";
};
};
gic: interrupt-controller@38800000 {

613
arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts Normal file
View File

@@ -0,0 +1,613 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree File for the Kontron pitx-imx8m board.
*
* Copyright (C) 2021 Heiko Thiery <heiko.thiery@gmail.com>
*/
/dts-v1/;
#include "imx8mq.dtsi"
#include <dt-bindings/net/ti-dp83867.h>
/ {
model = "Kontron pITX-imx8m";
compatible = "kontron,pitx-imx8m", "fsl,imx8mq";
aliases {
i2c0 = &i2c1;
i2c1 = &i2c2;
i2c2 = &i2c3;
mmc0 = &usdhc1;
mmc1 = &usdhc2;
serial0 = &uart1;
serial1 = &uart2;
serial2 = &uart3;
spi0 = &qspi0;
spi1 = &ecspi2;
};
chosen {
stdout-path = "serial2:115200n8";
};
pcie0_refclk: pcie0-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
};
pcie1_refclk: pcie1-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
};
reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usdhc2>;
regulator-name = "V_3V3_SD";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
off-on-delay-us = <20000>;
enable-active-high;
};
};
&ecspi2 {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs>;
cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
status = "okay";
tpm@0 {
compatible = "infineon,slb9670";
reg = <0>;
spi-max-frequency = <43000000>;
};
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy0>;
fsl,magic-packet;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
reset-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
reset-assert-us = <10>;
reset-deassert-us = <280>;
};
};
};
&i2c1 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
pmic@8 {
compatible = "fsl,pfuze100";
fsl,pfuze-support-disable-sw;
reg = <0x8>;
regulators {
sw1a_reg: sw1ab {
regulator-name = "V_0V9_GPU";
regulator-min-microvolt = <825000>;
regulator-max-microvolt = <1100000>;
};
sw1c_reg: sw1c {
regulator-name = "V_0V9_VPU";
regulator-min-microvolt = <825000>;
regulator-max-microvolt = <1100000>;
};
sw2_reg: sw2 {
regulator-name = "V_1V1_NVCC_DRAM";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
regulator-always-on;
};
sw3a_reg: sw3ab {
regulator-name = "V_1V0_DRAM";
regulator-min-microvolt = <825000>;
regulator-max-microvolt = <1100000>;
regulator-always-on;
};
sw4_reg: sw4 {
regulator-name = "V_1V8_S0";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
swbst_reg: swbst {
regulator-name = "NC";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5150000>;
};
snvs_reg: vsnvs {
regulator-name = "V_0V9_SNVS";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <3000000>;
regulator-always-on;
};
vref_reg: vrefddr {
regulator-name = "V_0V55_VREF_DDR";
regulator-always-on;
};
vgen1_reg: vgen1 {
regulator-name = "V_1V5_CSI";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1550000>;
};
vgen2_reg: vgen2 {
regulator-name = "V_0V9_PHY";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <975000>;
regulator-always-on;
};
vgen3_reg: vgen3 {
regulator-name = "V_1V8_PHY";
regulator-min-microvolt = <1675000>;
regulator-max-microvolt = <1975000>;
regulator-always-on;
};
vgen4_reg: vgen4 {
regulator-name = "V_1V8_VDDA";
regulator-min-microvolt = <1625000>;
regulator-max-microvolt = <1875000>;
regulator-always-on;
};
vgen5_reg: vgen5 {
regulator-name = "V_3V3_PHY";
regulator-min-microvolt = <3075000>;
regulator-max-microvolt = <3625000>;
regulator-always-on;
};
vgen6_reg: vgen6 {
regulator-name = "V_2V8_CAM";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
};
};
fan-controller@1b {
compatible = "maxim,max6650";
reg = <0x1b>;
maxim,fan-microvolt = <5000000>;
};
rtc@32 {
compatible = "microcrystal,rv8803";
reg = <0x32>;
};
sensor@4b {
compatible = "national,lm75b";
reg = <0x4b>;
};
eeprom@51 {
compatible = "atmel,24c32";
reg = <0x51>;
pagesize = <32>;
};
};
&i2c2 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
};
&i2c3 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
};
/* M.2 B-key slot */
&pcie0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie0>;
reset-gpio = <&gpio1 9 GPIO_ACTIVE_LOW>;
clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
<&clk IMX8MQ_CLK_PCIE1_AUX>,
<&clk IMX8MQ_CLK_PCIE1_PHY>,
<&pcie0_refclk>;
clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
status = "okay";
};
/* Intel Ethernet Controller I210/I211 */
&pcie1 {
clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
<&clk IMX8MQ_CLK_PCIE2_AUX>,
<&clk IMX8MQ_CLK_PCIE2_PHY>,
<&pcie1_refclk>;
clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
fsl,max-link-speed = <1>;
status = "okay";
};
&pgc_gpu {
power-supply = <&sw1a_reg>;
};
&pgc_vpu {
power-supply = <&sw1c_reg>;
};
&qspi0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_qspi>;
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
m25p,fast-read;
spi-max-frequency = <50000000>;
};
};
&snvs_pwrkey {
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
assigned-clocks = <&clk IMX8MQ_CLK_UART1>;
assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
assigned-clocks = <&clk IMX8MQ_CLK_UART2>;
assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
fsl,uart-has-rtscts;
assigned-clocks = <&clk IMX8MQ_CLK_UART3>;
assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
status = "okay";
};
&usb3_phy0 {
status = "okay";
};
&usb3_phy1 {
status = "okay";
};
&usb_dwc3_0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb0>;
dr_mode = "otg";
hnp-disable;
srp-disable;
adp-disable;
maximum-speed = "high-speed";
status = "okay";
};
&usb_dwc3_1 {
dr_mode = "host";
status = "okay";
};
&usdhc1 {
assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
assigned-clock-rates = <400000000>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
vqmmc-supply = <&sw4_reg>;
bus-width = <8>;
non-removable;
no-sd;
no-sdio;
status = "okay";
};
&usdhc2 {
assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>;
assigned-clock-rates = <200000000>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
bus-width = <4>;
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
vmmc-supply = <&reg_usdhc2_vmmc>;
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
pinctrl_hog: hoggrp {
fsl,pins = <
MX8MQ_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x19 /* TPM Reset */
MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x19 /* USB2 Hub Reset */
>;
};
pinctrl_gpio: gpiogrp {
fsl,pins = <
MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x19 /* GPIO0 */
MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15 0x19 /* GPIO1 */
MX8MQ_IOMUXC_NAND_WE_B_GPIO3_IO17 0x19 /* GPIO2 */
MX8MQ_IOMUXC_NAND_WP_B_GPIO3_IO18 0x19 /* GPIO3 */
MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 /* GPIO4 */
MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10 0x19 /* GPIO5 */
MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11 0x19 /* GPIO6 */
MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12 0x19 /* GPIO7 */
>;
};
pinctrl_pcie0: pcie0grp {
fsl,pins = <
MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x16 /* PCIE_PERST */
MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29 0x16 /* W_DISABLE */
>;
};
pinctrl_reg_usdhc2: regusdhc2gpiogrp {
fsl,pins = <
MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
>;
};
pinctrl_fec1: fec1grp {
fsl,pins = <
MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x16
MX8MQ_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x16
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f
MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000007f
MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x4000007f
>;
};
pinctrl_qspi: qspigrp {
fsl,pins = <
MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82
MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
>;
};
pinctrl_ecspi2: ecspi2grp {
fsl,pins = <
MX8MQ_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x19
MX8MQ_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x19
MX8MQ_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x19
>;
};
pinctrl_ecspi2_cs: ecspi2csgrp {
fsl,pins = <
MX8MQ_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x19
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49
MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49
MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x49
MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x49
MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x49
MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x49
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83
MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
>;
};
pinctrl_usdhc1_100mhz: usdhc1-100grp {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd
MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d
MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
>;
};
pinctrl_usdhc1_200mhz: usdhc1-200grp {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf
MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f
MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
>;
};
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41
MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20 0x19
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
>;
};
pinctrl_usdhc2_100mhz: usdhc2-100grp {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x8d
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcd
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcd
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcd
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcd
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcd
MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
>;
};
pinctrl_usdhc2_200mhz: usdhc2-200grp {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x9f
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xdf
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xdf
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xdf
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xdf
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xdf
MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
>;
};
pinctrl_usb0: usb0grp {
fsl,pins = <
MX8MQ_IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x19
MX8MQ_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x19
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
>;
};
};

70
arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts
View File

@@ -50,13 +50,6 @@ btn2 {
linux,code = <KEY_VOLUMEDOWN>;
};
hp-det {
label = "HP_DET";
gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
wakeup-source;
linux,code = <KEY_HP>;
};
wwan-wake {
label = "WWAN_WAKE";
gpios = <&gpio3 8 GPIO_ACTIVE_LOW>;
@@ -163,21 +156,35 @@ wwan_codec: sound-wwan-codec {
#sound-dai-cells = <0>;
};
mic_mux: mic-mux {
compatible = "simple-audio-mux";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_micsel>;
mux-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>;
sound-name-prefix = "Mic Mux";
};
sound {
compatible = "simple-audio-card";
simple-audio-card,name = "sgtl5000";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hpdet>;
simple-audio-card,aux-devs = <&speaker_amp>, <&mic_mux>;
simple-audio-card,name = "Librem 5 Devkit";
simple-audio-card,format = "i2s";
simple-audio-card,widgets =
"Microphone", "Microphone Jack",
"Headphone", "Headphone Jack",
"Speaker", "Speaker Ext",
"Line", "Line In Jack";
"Microphone", "Builtin Microphone",
"Microphone", "Headset Microphone",
"Headphone", "Headphones",
"Speaker", "Builtin Speaker";
simple-audio-card,routing =
"MIC_IN", "Microphone Jack",
"Microphone Jack", "Mic Bias",
"LINE_IN", "Line In Jack",
"Headphone Jack", "HP_OUT",
"Speaker Ext", "LINE_OUT";
"MIC_IN", "Mic Mux OUT",
"Mic Mux IN1", "Headset Microphone",
"Mic Mux IN2", "Builtin Microphone",
"Mic Mux OUT", "Mic Bias",
"Headphones", "HP_OUT",
"Builtin Speaker", "Speaker Amp OUTR",
"Speaker Amp INR", "LINE_OUT";
simple-audio-card,hp-det-gpio = <&gpio3 20 GPIO_ACTIVE_HIGH>;
simple-audio-card,cpu {
sound-dai = <&sai2>;
@@ -207,6 +214,15 @@ telephony_link_master: simple-audio-card,codec {
};
};
speaker_amp: speaker-amp {
compatible = "simple-audio-amplifier";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spkamp>;
VCC-supply = <&reg_3v3_p>;
sound-name-prefix = "Speaker Amp";
enable-gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>;
};
vibrator {
compatible = "gpio-vibrator";
pinctrl-names = "default";
@@ -315,7 +331,6 @@ buck3_reg: BUCK3 {
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1300000>;
regulator-boot-on;
regulator-enable-ramp-delay = <200>;
rohm,dvs-run-voltage = <900000>;
};
@@ -610,7 +625,6 @@ pinctrl_gpio_keys: gpiokeygrp {
fsl,pins = <
MX8MQ_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x16
MX8MQ_IOMUXC_SAI2_RXC_GPIO4_IO22 0x16
MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20 0x180 /* HP_DET */
MX8MQ_IOMUXC_NAND_DATA02_GPIO3_IO8 0x80 /* nWoWWAN */
>;
};
@@ -621,6 +635,12 @@ MX8MQ_IOMUXC_SPDIF_RX_GPIO5_IO4 0xc6 /* nHAPTIC */
>;
};
pinctrl_hpdet: hpdetgrp {
fsl,pins = <
MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20 0xC0 /* HP_DET */
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000001f
@@ -641,6 +661,18 @@ MX8MQ_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x8 /* IMU_INT */
>;
};
pinctrl_micsel: micselgrp {
fsl,pins = <
MX8MQ_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0xc6 /* MIC_SEL */
>;
};
pinctrl_spkamp: spkamp {
fsl,pins = <
MX8MQ_IOMUXC_SPDIF_TX_GPIO5_IO3 0x81 /* MUTE */
>;
};
pinctrl_pmic: pmicgrp {
fsl,pins = <
MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x80 /* PMIC intr */

2
arch/arm64/boot/dts/freescale/imx8mq-librem5-r2.dts
View File

@@ -25,5 +25,5 @@ &accel_gyro {
};
&proximity {
proximity-near-level = <220>;
proximity-near-level = <120>;
};

4
arch/arm64/boot/dts/freescale/imx8mq-librem5-r3.dts
View File

@@ -28,6 +28,10 @@ &bq25895 {
ti,termination-current = <144000>; /* uA */
};
&buck3_reg {
regulator-always-on;
};
&proximity {
proximity-near-level = <25>;
};

24
arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi
View File

@@ -258,6 +258,25 @@ nor_flash: flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <1000000>;
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "protected0";
reg = <0x0 0x30000>;
read-only;
};
partition@30000 {
label = "protected1";
reg = <0x30000 0x10000>;
read-only;
};
partition@40000 {
label = "rw";
reg = <0x40000 0x1C0000>;
};
};
};
@@ -267,8 +286,9 @@ &gpio1 {
pmic-5v-hog {
gpio-hog;
gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
gpios = <1 GPIO_ACTIVE_HIGH>;
input;
lane-mapping = "pmic-5v";
};
};
@@ -1051,8 +1071,6 @@ &sai2 {
assigned-clocks = <&clk IMX8MQ_CLK_SAI2>;
assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
assigned-clock-rates = <24576000>;
assigned-clocks = <&clk IMX8MQ_AUDIO_PLL1>, <&clk IMX8MQ_AUDIO_PLL2>;
assigned-clock-rates = <786432000>, <722534400>;
status = "okay";
};

144
arch/arm64/boot/dts/freescale/imx8qm-mek.dts Normal file
View File

@@ -0,0 +1,144 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2018-2019 NXP
* Dong Aisheng <aisheng.dong@nxp.com>
*/
/dts-v1/;
#include "imx8qm.dtsi"
/ {
model = "Freescale i.MX8QM MEK";
compatible = "fsl,imx8qm-mek", "fsl,imx8qm";
chosen {
stdout-path = &lpuart0;
};
cpus {
/delete-node/ cpu-map;
/delete-node/ cpu@100;
/delete-node/ cpu@101;
};
memory@80000000 {
device_type = "memory";
reg = <0x00000000 0x80000000 0 0x40000000>;
};
reg_usdhc2_vmmc: usdhc2-vmmc {
compatible = "regulator-fixed";
regulator-name = "SD1_SPWR";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
gpio = <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};
&lpuart0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart0>;
status = "okay";
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy0>;
fsl,magic-packet;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
};
ethphy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
};
};
};
&usdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
bus-width = <8>;
no-sd;
no-sdio;
non-removable;
status = "okay";
};
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
bus-width = <4>;
vmmc-supply = <&reg_usdhc2_vmmc>;
cd-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>;
wp-gpios = <&lsio_gpio4 21 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&iomuxc {
pinctrl_fec1: fec1grp {
fsl,pins = <
IMX8QM_ENET0_MDC_CONN_ENET0_MDC 0x06000020
IMX8QM_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020
IMX8QM_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020
IMX8QM_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000020
IMX8QM_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020
IMX8QM_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020
IMX8QM_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000020
IMX8QM_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000020
IMX8QM_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000020
IMX8QM_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020
IMX8QM_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000020
IMX8QM_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020
IMX8QM_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020
IMX8QM_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020
>;
};
pinctrl_lpuart0: lpuart0grp {
fsl,pins = <
IMX8QM_UART0_RX_DMA_UART0_RX 0x06000020
IMX8QM_UART0_TX_DMA_UART0_TX 0x06000020
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021
IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021
IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021
IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021
IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021
IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021
IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021
IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021
IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021
IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041
IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021
IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021
IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021
IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021
IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021
IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021
>;
};
};

21
arch/arm64/boot/dts/freescale/imx8qm-ss-conn.dtsi Normal file
View File

@@ -0,0 +1,21 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2019-2020 NXP
* Dong Aisheng <aisheng.dong@nxp.com>
*/
&fec1 {
compatible = "fsl,imx8qm-fec", "fsl,imx6sx-fec";
};
&fec2 {
compatible = "fsl,imx8qm-fec", "fsl,imx6sx-fec";
};
&usdhc1 {
compatible = "fsl,imx8qm-usdhc", "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";
};
&usdhc2 {
compatible = "fsl,imx8qm-usdhc", "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";
};

51
arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi Normal file
View File

@@ -0,0 +1,51 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2018-2019 NXP
* Dong Aisheng <aisheng.dong@nxp.com>
*/
&dma_subsys {
uart4_lpcg: clock-controller@5a4a0000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5a4a0000 0x10000>;
#clock-cells = <1>;
clocks = <&clk IMX_SC_R_UART_4 IMX_SC_PM_CLK_PER>,
<&dma_ipg_clk>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
clock-output-names = "uart4_lpcg_baud_clk",
"uart4_lpcg_ipg_clk";
power-domains = <&pd IMX_SC_R_UART_4>;
};
};
&lpuart0 {
compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart";
};
&lpuart1 {
compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart";
};
&lpuart2 {
compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart";
};
&lpuart3 {
compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart";
};
&i2c0 {
compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
};
&i2c1 {
compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
};
&i2c2 {
compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
};
&i2c3 {
compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
};

61
arch/arm64/boot/dts/freescale/imx8qm-ss-lsio.dtsi Normal file
View File

@@ -0,0 +1,61 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2019-2020 NXP
* Dong Aisheng <aisheng.dong@nxp.com>
*/
&lsio_gpio0 {
compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
};
&lsio_gpio1 {
compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
};
&lsio_gpio2 {
compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
};
&lsio_gpio3 {
compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
};
&lsio_gpio4 {
compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
};
&lsio_gpio5 {
compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
};
&lsio_gpio6 {
compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
};
&lsio_gpio7 {
compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
};
&lsio_mu0 {
compatible = "fsl,imx8-mu-scu", "fsl,imx8qm-mu", "fsl,imx6sx-mu";
};
&lsio_mu1 {
compatible = "fsl,imx8-mu-scu", "fsl,imx8qm-mu", "fsl,imx6sx-mu";
};
&lsio_mu2 {
compatible = "fsl,imx8-mu-scu", "fsl,imx8qm-mu", "fsl,imx6sx-mu";
};
&lsio_mu3 {
compatible = "fsl,imx8-mu-scu", "fsl,imx8qm-mu", "fsl,imx6sx-mu";
};
&lsio_mu4 {
compatible = "fsl,imx8-mu-scu", "fsl,imx8qm-mu", "fsl,imx6sx-mu";
};
&lsio_mu13 {
compatible = "fsl,imx8qm-mu", "fsl,imx6sx-mu";
};

176
arch/arm64/boot/dts/freescale/imx8qm.dtsi Normal file
View File

@@ -0,0 +1,176 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2018-2019 NXP
* Dong Aisheng <aisheng.dong@nxp.com>
*/
#include <dt-bindings/clock/imx8-lpcg.h>
#include <dt-bindings/firmware/imx/rsrc.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/pads-imx8qm.h>
/ {
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
aliases {
mmc0 = &usdhc1;
mmc1 = &usdhc2;
mmc2 = &usdhc3;
serial0 = &lpuart0;
};
cpus {
#address-cells = <2>;
#size-cells = <0>;
cpu-map {
cluster0 {
core0 {
cpu = <&A53_0>;
};
core1 {
cpu = <&A53_1>;
};
core2 {
cpu = <&A53_2>;
};
core3 {
cpu = <&A53_3>;
};
};
cluster1 {
core0 {
cpu = <&A72_0>;
};
core1 {
cpu = <&A72_1>;
};
};
};
A53_0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x0>;
enable-method = "psci";
next-level-cache = <&A53_L2>;
};
A53_1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x1>;
enable-method = "psci";
next-level-cache = <&A53_L2>;
};
A53_2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x2>;
enable-method = "psci";
next-level-cache = <&A53_L2>;
};
A53_3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x3>;
enable-method = "psci";
next-level-cache = <&A53_L2>;
};
A72_0: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x0 0x100>;
enable-method = "psci";
next-level-cache = <&A72_L2>;
};
A72_1: cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x0 0x101>;
enable-method = "psci";
next-level-cache = <&A72_L2>;
};
A53_L2: l2-cache0 {
compatible = "cache";
};
A72_L2: l2-cache1 {
compatible = "cache";
};
};
gic: interrupt-controller@51a00000 {
compatible = "arm,gic-v3";
reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */
<0x0 0x51b00000 0 0xC0000>, /* GICR */
<0x0 0x52000000 0 0x2000>, /* GICC */
<0x0 0x52010000 0 0x1000>, /* GICH */
<0x0 0x52020000 0 0x20000>; /* GICV */
#interrupt-cells = <3>;
interrupt-controller;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
};
pmu {
compatible = "arm,armv8-pmuv3";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */
};
scu {
compatible = "fsl,imx-scu";
mbox-names = "tx0",
"rx0",
"gip3";
mboxes = <&lsio_mu1 0 0
&lsio_mu1 1 0
&lsio_mu1 3 3>;
pd: imx8qx-pd {
compatible = "fsl,imx8qm-scu-pd", "fsl,scu-pd";
#power-domain-cells = <1>;
};
clk: clock-controller {
compatible = "fsl,imx8qxp-clk", "fsl,scu-clk";
#clock-cells = <2>;
};
iomuxc: pinctrl {
compatible = "fsl,imx8qm-iomuxc";
};
};
/* sorted in register address */
#include "imx8-ss-dma.dtsi"
#include "imx8-ss-conn.dtsi"
#include "imx8-ss-lsio.dtsi"
};
#include "imx8qm-ss-dma.dtsi"
#include "imx8qm-ss-conn.dtsi"
#include "imx8qm-ss-lsio.dtsi"

20
arch/arm64/boot/dts/freescale/imx8qxp-ai_ml.dts
View File

@@ -13,13 +13,13 @@ / {
compatible = "einfochips,imx8qxp-ai_ml", "fsl,imx8qxp";
aliases {
serial1 = &adma_lpuart1;
serial2 = &adma_lpuart2;
serial3 = &adma_lpuart3;
serial1 = &lpuart1;
serial2 = &lpuart2;
serial3 = &lpuart3;
};
chosen {
stdout-path = &adma_lpuart2;
stdout-path = &lpuart2;
};
memory@80000000 {
@@ -82,7 +82,7 @@ sdio_pwrseq: sdio-pwrseq {
};
/* BT */
&adma_lpuart0 {
&lpuart0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart0>;
uart-has-rtscts;
@@ -90,21 +90,21 @@ &adma_lpuart0 {
};
/* LS-UART0 */
&adma_lpuart1 {
&lpuart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart1>;
status = "okay";
};
/* Debug */
&adma_lpuart2 {
&lpuart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart2>;
status = "okay";
};
/* PCI-E UART */
&adma_lpuart3 {
&lpuart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart3>;
status = "okay";
@@ -133,7 +133,7 @@ ethphy0: ethernet-phy@0 {
&usdhc1 {
#address-cells = <1>;
#size-cells = <0>;
assigned-clocks = <&clk IMX_CONN_SDHC0_CLK>;
assigned-clocks = <&clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <200000000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
@@ -151,7 +151,7 @@ brcmf: wifi@1 {
/* SD */
&usdhc2 {
assigned-clocks = <&clk IMX_CONN_SDHC1_CLK>;
assigned-clocks = <&clk IMX_SC_R_SDHC_1 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <200000000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;

8
arch/arm64/boot/dts/freescale/imx8qxp-colibri-eval-v3.dtsi
View File

@@ -26,7 +26,7 @@ wakeup {
};
};
&adma_i2c1 {
&i2c1 {
status = "okay";
/* M41T0M6 real time clock on carrier board */
@@ -37,17 +37,17 @@ rtc_i2c: rtc@68 {
};
/* Colibri UART_B */
&adma_lpuart0 {
&lpuart0 {
status= "okay";
};
/* Colibri UART_C */
&adma_lpuart2 {
&lpuart2 {
status= "okay";
};
/* Colibri UART_A */
&adma_lpuart3 {
&lpuart3 {
status= "okay";
};

12
arch/arm64/boot/dts/freescale/imx8qxp-colibri.dtsi
View File

@@ -10,7 +10,7 @@ / {
compatible = "toradex,colibri-imx8x", "fsl,imx8qxp";
chosen {
stdout-path = &adma_lpuart3;
stdout-path = &lpuart3;
};
reg_module_3v3: regulator-module-3v3 {
@@ -22,7 +22,7 @@ reg_module_3v3: regulator-module-3v3 {
};
/* On-module I2C */
&adma_i2c0 {
&i2c0 {
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <100000>;
@@ -49,7 +49,7 @@ touchscreen@2c {
};
/* Colibri I2C */
&adma_i2c1 {
&i2c1 {
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <100000>;
@@ -58,19 +58,19 @@ &adma_i2c1 {
};
/* Colibri UART_B */
&adma_lpuart0 {
&lpuart0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart0>;
};
/* Colibri UART_C */
&adma_lpuart2 {
&lpuart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart2>;
};
/* Colibri UART_A */
&adma_lpuart3 {
&lpuart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart3>, <&pinctrl_lpuart3_ctrl>;
};

50
arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
View File

@@ -12,7 +12,7 @@ / {
compatible = "fsl,imx8qxp-mek", "fsl,imx8qxp";
chosen {
stdout-path = &adma_lpuart0;
stdout-path = &lpuart0;
};
memory@80000000 {
@@ -30,11 +30,30 @@ reg_usdhc2_vmmc: usdhc2-vmmc {
};
};
&adma_dsp {
&dsp {
status = "okay";
};
&adma_i2c1 {
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy0>;
fsl,magic-packet;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
};
};
};
&i2c1 {
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <100000>;
@@ -110,31 +129,12 @@ light-sensor@44 {
};
};
&adma_lpuart0 {
&lpuart0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart0>;
status = "okay";
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy0>;
fsl,magic-packet;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
};
};
};
&scu_key {
status = "okay";
};
@@ -173,7 +173,7 @@ map0 {
};
&usdhc1 {
assigned-clocks = <&clk IMX_CONN_SDHC0_CLK>;
assigned-clocks = <&clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <200000000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
@@ -185,7 +185,7 @@ &usdhc1 {
};
&usdhc2 {
assigned-clocks = <&clk IMX_CONN_SDHC1_CLK>;
assigned-clocks = <&clk IMX_SC_R_SDHC_1 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <200000000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;

37
arch/arm64/boot/dts/freescale/imx8qxp-ss-adma.dtsi Normal file
View File

@@ -0,0 +1,37 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2018-2020 NXP
* Dong Aisheng <aisheng.dong@nxp.com>
*/
&lpuart0 {
compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
};
&lpuart1 {
compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
};
&lpuart2 {
compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
};
&lpuart3 {
compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
};
&i2c0 {
compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
};
&i2c1 {
compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
};
&i2c2 {
compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
};
&i2c3 {
compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
};

25
arch/arm64/boot/dts/freescale/imx8qxp-ss-conn.dtsi Normal file
View File

@@ -0,0 +1,25 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2018-2020 NXP
* Dong Aisheng <aisheng.dong@nxp.com>
*/
&usdhc1 {
compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";
};
&usdhc2 {
compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";
};
&usdhc3 {
compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";
};
&fec1 {
compatible = "fsl,imx8qxp-fec", "fsl,imx6sx-fec";
};
&fec2 {
compatible = "fsl,imx8qxp-fec", "fsl,imx6sx-fec";
};

61
arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi Normal file
View File

@@ -0,0 +1,61 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2018-2020 NXP
* Dong Aisheng <aisheng.dong@nxp.com>
*/
&lsio_gpio0 {
compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
};
&lsio_gpio1 {
compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
};
&lsio_gpio2 {
compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
};
&lsio_gpio3 {
compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
};
&lsio_gpio4 {
compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
};
&lsio_gpio5 {
compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
};
&lsio_gpio6 {
compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
};
&lsio_gpio7 {
compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
};
&lsio_mu0 {
compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
};
&lsio_mu1 {
compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
};
&lsio_mu2 {
compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
};
&lsio_mu3 {
compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
};
&lsio_mu4 {
compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
};
&lsio_mu13 {
compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
};

423
arch/arm64/boot/dts/freescale/imx8qxp.dtsi
View File

@@ -1,11 +1,12 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
* Copyright 2017-2018 NXP
* Copyright 2017-2020 NXP
* Dong Aisheng <aisheng.dong@nxp.com>
*/
#include <dt-bindings/clock/imx8-clock.h>
#include <dt-bindings/clock/imx8-lpcg.h>
#include <dt-bindings/firmware/imx/rsrc.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
@@ -29,10 +30,10 @@ aliases {
gpio5 = &lsio_gpio5;
gpio6 = &lsio_gpio6;
gpio7 = &lsio_gpio7;
i2c0 = &adma_i2c0;
i2c1 = &adma_i2c1;
i2c2 = &adma_i2c2;
i2c3 = &adma_i2c3;
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
i2c3 = &i2c3;
mmc0 = &usdhc1;
mmc1 = &usdhc2;
mmc2 = &usdhc3;
@@ -41,10 +42,10 @@ aliases {
mu2 = &lsio_mu2;
mu3 = &lsio_mu3;
mu4 = &lsio_mu4;
serial0 = &adma_lpuart0;
serial1 = &adma_lpuart1;
serial2 = &adma_lpuart2;
serial3 = &adma_lpuart3;
serial0 = &lpuart0;
serial1 = &lpuart1;
serial2 = &lpuart2;
serial3 = &lpuart3;
};
cpus {
@@ -58,7 +59,7 @@ A35_0: cpu@0 {
reg = <0x0 0x0>;
enable-method = "psci";
next-level-cache = <&A35_L2>;
clocks = <&clk IMX_A35_CLK>;
clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>;
operating-points-v2 = <&a35_opp_table>;
#cooling-cells = <2>;
};
@@ -69,7 +70,7 @@ A35_1: cpu@1 {
reg = <0x0 0x1>;
enable-method = "psci";
next-level-cache = <&A35_L2>;
clocks = <&clk IMX_A35_CLK>;
clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>;
operating-points-v2 = <&a35_opp_table>;
#cooling-cells = <2>;
};
@@ -80,7 +81,7 @@ A35_2: cpu@2 {
reg = <0x0 0x2>;
enable-method = "psci";
next-level-cache = <&A35_L2>;
clocks = <&clk IMX_A35_CLK>;
clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>;
operating-points-v2 = <&a35_opp_table>;
#cooling-cells = <2>;
};
@@ -91,7 +92,7 @@ A35_3: cpu@3 {
reg = <0x0 0x3>;
enable-method = "psci";
next-level-cache = <&A35_L2>;
clocks = <&clk IMX_A35_CLK>;
clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>;
operating-points-v2 = <&a35_opp_table>;
#cooling-cells = <2>;
};
@@ -158,9 +159,14 @@ scu {
&lsio_mu1 1 0
&lsio_mu1 3 3>;
pd: imx8qx-pd {
compatible = "fsl,imx8qxp-scu-pd", "fsl,scu-pd";
#power-domain-cells = <1>;
};
clk: clock-controller {
compatible = "fsl,imx8qxp-clk";
#clock-cells = <1>;
#clock-cells = <2>;
clocks = <&xtal32k &xtal24m>;
clock-names = "xtal_32KHz", "xtal_24Mhz";
};
@@ -175,11 +181,6 @@ ocotp: imx8qx-ocotp {
#size-cells = <1>;
};
pd: imx8qx-pd {
compatible = "fsl,imx8qxp-scu-pd";
#power-domain-cells = <1>;
};
scu_key: scu-key {
compatible = "fsl,imx8qxp-sc-key", "fsl,imx-sc-key";
linux,keycodes = <KEY_POWER>;
@@ -223,380 +224,6 @@ xtal24m: clock-xtal24m {
clock-output-names = "xtal_24MHz";
};
adma_subsys: bus@59000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x59000000 0x0 0x59000000 0x2000000>;
adma_lpcg: clock-controller@59000000 {
compatible = "fsl,imx8qxp-lpcg-adma";
reg = <0x59000000 0x2000000>;
#clock-cells = <1>;
};
adma_dsp: dsp@596e8000 {
compatible = "fsl,imx8qxp-dsp";
reg = <0x596e8000 0x88000>;
clocks = <&adma_lpcg IMX_ADMA_LPCG_DSP_IPG_CLK>,
<&adma_lpcg IMX_ADMA_LPCG_OCRAM_IPG_CLK>,
<&adma_lpcg IMX_ADMA_LPCG_DSP_CORE_CLK>;
clock-names = "ipg", "ocram", "core";
power-domains = <&pd IMX_SC_R_MU_13A>,
<&pd IMX_SC_R_MU_13B>,
<&pd IMX_SC_R_DSP>,
<&pd IMX_SC_R_DSP_RAM>;
mbox-names = "txdb0", "txdb1",
"rxdb0", "rxdb1";
mboxes = <&lsio_mu13 2 0>,
<&lsio_mu13 2 1>,
<&lsio_mu13 3 0>,
<&lsio_mu13 3 1>;
memory-region = <&dsp_reserved>;
status = "disabled";
};
adma_lpuart0: serial@5a060000 {
compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
reg = <0x5a060000 0x1000>;
interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&adma_lpcg IMX_ADMA_LPCG_UART0_IPG_CLK>,
<&adma_lpcg IMX_ADMA_LPCG_UART0_BAUD_CLK>;
clock-names = "ipg", "baud";
power-domains = <&pd IMX_SC_R_UART_0>;
status = "disabled";
};
adma_lpuart1: serial@5a070000 {
compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
reg = <0x5a070000 0x1000>;
interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&adma_lpcg IMX_ADMA_LPCG_UART1_IPG_CLK>,
<&adma_lpcg IMX_ADMA_LPCG_UART1_BAUD_CLK>;
clock-names = "ipg", "baud";
power-domains = <&pd IMX_SC_R_UART_1>;
status = "disabled";
};
adma_lpuart2: serial@5a080000 {
compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
reg = <0x5a080000 0x1000>;
interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&adma_lpcg IMX_ADMA_LPCG_UART2_IPG_CLK>,
<&adma_lpcg IMX_ADMA_LPCG_UART2_BAUD_CLK>;
clock-names = "ipg", "baud";
power-domains = <&pd IMX_SC_R_UART_2>;
status = "disabled";
};
adma_lpuart3: serial@5a090000 {
compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
reg = <0x5a090000 0x1000>;
interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&adma_lpcg IMX_ADMA_LPCG_UART3_IPG_CLK>,
<&adma_lpcg IMX_ADMA_LPCG_UART3_BAUD_CLK>;
clock-names = "ipg", "baud";
power-domains = <&pd IMX_SC_R_UART_3>;
status = "disabled";
};
adma_i2c0: i2c@5a800000 {
compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
reg = <0x5a800000 0x4000>;
interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C0_CLK>;
clock-names = "per";
assigned-clocks = <&clk IMX_ADMA_I2C0_CLK>;
assigned-clock-rates = <24000000>;
power-domains = <&pd IMX_SC_R_I2C_0>;
status = "disabled";
};
adma_i2c1: i2c@5a810000 {
compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
reg = <0x5a810000 0x4000>;
interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C1_CLK>;
clock-names = "per";
assigned-clocks = <&clk IMX_ADMA_I2C1_CLK>;
assigned-clock-rates = <24000000>;
power-domains = <&pd IMX_SC_R_I2C_1>;
status = "disabled";
};
adma_i2c2: i2c@5a820000 {
compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
reg = <0x5a820000 0x4000>;
interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C2_CLK>;
clock-names = "per";
assigned-clocks = <&clk IMX_ADMA_I2C2_CLK>;
assigned-clock-rates = <24000000>;
power-domains = <&pd IMX_SC_R_I2C_2>;
status = "disabled";
};
adma_i2c3: i2c@5a830000 {
compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
reg = <0x5a830000 0x4000>;
interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C3_CLK>;
clock-names = "per";
assigned-clocks = <&clk IMX_ADMA_I2C3_CLK>;
assigned-clock-rates = <24000000>;
power-domains = <&pd IMX_SC_R_I2C_3>;
status = "disabled";
};
};
conn_subsys: bus@5b000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x5b000000 0x0 0x5b000000 0x1000000>;
conn_lpcg: clock-controller@5b200000 {
compatible = "fsl,imx8qxp-lpcg-conn";
reg = <0x5b200000 0xb0000>;
#clock-cells = <1>;
};
usdhc1: mmc@5b010000 {
compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";
interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x5b010000 0x10000>;
clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC0_IPG_CLK>,
<&conn_lpcg IMX_CONN_LPCG_SDHC0_PER_CLK>,
<&conn_lpcg IMX_CONN_LPCG_SDHC0_HCLK>;
clock-names = "ipg", "per", "ahb";
power-domains = <&pd IMX_SC_R_SDHC_0>;
status = "disabled";
};
usdhc2: mmc@5b020000 {
compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";
interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x5b020000 0x10000>;
clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC1_IPG_CLK>,
<&conn_lpcg IMX_CONN_LPCG_SDHC1_PER_CLK>,
<&conn_lpcg IMX_CONN_LPCG_SDHC1_HCLK>;
clock-names = "ipg", "per", "ahb";
power-domains = <&pd IMX_SC_R_SDHC_1>;
fsl,tuning-start-tap = <20>;
fsl,tuning-step= <2>;
status = "disabled";
};
usdhc3: mmc@5b030000 {
compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";
interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x5b030000 0x10000>;
clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC2_IPG_CLK>,
<&conn_lpcg IMX_CONN_LPCG_SDHC2_PER_CLK>,
<&conn_lpcg IMX_CONN_LPCG_SDHC2_HCLK>;
clock-names = "ipg", "per", "ahb";
power-domains = <&pd IMX_SC_R_SDHC_2>;
status = "disabled";
};
fec1: ethernet@5b040000 {
compatible = "fsl,imx8qxp-fec", "fsl,imx6sx-fec";
reg = <0x5b040000 0x10000>;
interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&conn_lpcg IMX_CONN_LPCG_ENET0_IPG_CLK>,
<&conn_lpcg IMX_CONN_LPCG_ENET0_AHB_CLK>,
<&conn_lpcg IMX_CONN_LPCG_ENET0_TX_CLK>,
<&conn_lpcg IMX_CONN_LPCG_ENET0_ROOT_CLK>;
clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";
fsl,num-tx-queues=<3>;
fsl,num-rx-queues=<3>;
power-domains = <&pd IMX_SC_R_ENET_0>;
status = "disabled";
};
fec2: ethernet@5b050000 {
compatible = "fsl,imx8qxp-fec", "fsl,imx6sx-fec";
reg = <0x5b050000 0x10000>;
interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&conn_lpcg IMX_CONN_LPCG_ENET1_IPG_CLK>,
<&conn_lpcg IMX_CONN_LPCG_ENET1_AHB_CLK>,
<&conn_lpcg IMX_CONN_LPCG_ENET1_TX_CLK>,
<&conn_lpcg IMX_CONN_LPCG_ENET1_ROOT_CLK>;
clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";
fsl,num-tx-queues=<3>;
fsl,num-rx-queues=<3>;
power-domains = <&pd IMX_SC_R_ENET_1>;
status = "disabled";
};
};
ddr_subsyss: bus@5c000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x5c000000 0x0 0x5c000000 0x1000000>;
ddr-pmu@5c020000 {
compatible = "fsl,imx8-ddr-pmu";
reg = <0x5c020000 0x10000>;
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
};
};
lsio_subsys: bus@5d000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x5d000000 0x0 0x5d000000 0x1000000>;
lsio_gpio0: gpio@5d080000 {
compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
reg = <0x5d080000 0x10000>;
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
power-domains = <&pd IMX_SC_R_GPIO_0>;
};
lsio_gpio1: gpio@5d090000 {
compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
reg = <0x5d090000 0x10000>;
interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
power-domains = <&pd IMX_SC_R_GPIO_1>;
};
lsio_gpio2: gpio@5d0a0000 {
compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
reg = <0x5d0a0000 0x10000>;
interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
power-domains = <&pd IMX_SC_R_GPIO_2>;
};
lsio_gpio3: gpio@5d0b0000 {
compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
reg = <0x5d0b0000 0x10000>;
interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
power-domains = <&pd IMX_SC_R_GPIO_3>;
};
lsio_gpio4: gpio@5d0c0000 {
compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
reg = <0x5d0c0000 0x10000>;
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
power-domains = <&pd IMX_SC_R_GPIO_4>;
};
lsio_gpio5: gpio@5d0d0000 {
compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
reg = <0x5d0d0000 0x10000>;
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
power-domains = <&pd IMX_SC_R_GPIO_5>;
};
lsio_gpio6: gpio@5d0e0000 {
compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
reg = <0x5d0e0000 0x10000>;
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
power-domains = <&pd IMX_SC_R_GPIO_6>;
};
lsio_gpio7: gpio@5d0f0000 {
compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
reg = <0x5d0f0000 0x10000>;
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
power-domains = <&pd IMX_SC_R_GPIO_7>;
};
lsio_mu0: mailbox@5d1b0000 {
compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
reg = <0x5d1b0000 0x10000>;
interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <2>;
status = "disabled";
};
lsio_mu1: mailbox@5d1c0000 {
compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
reg = <0x5d1c0000 0x10000>;
interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <2>;
};
lsio_mu2: mailbox@5d1d0000 {
compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
reg = <0x5d1d0000 0x10000>;
interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <2>;
status = "disabled";
};
lsio_mu3: mailbox@5d1e0000 {
compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
reg = <0x5d1e0000 0x10000>;
interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <2>;
status = "disabled";
};
lsio_mu4: mailbox@5d1f0000 {
compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
reg = <0x5d1f0000 0x10000>;
interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <2>;
status = "disabled";
};
lsio_mu13: mailbox@5d280000 {
compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
reg = <0x5d280000 0x10000>;
interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <2>;
power-domains = <&pd IMX_SC_R_MU_13A>;
};
lsio_lpcg: clock-controller@5d400000 {
compatible = "fsl,imx8qxp-lpcg-lsio";
reg = <0x5d400000 0x400000>;
#clock-cells = <1>;
};
};
thermal_zones: thermal-zones {
cpu-thermal0 {
polling-delay-passive = <250>;
@@ -629,4 +256,14 @@ map0 {
};
};
};
/* sorted in register address */
#include "imx8-ss-adma.dtsi"
#include "imx8-ss-conn.dtsi"
#include "imx8-ss-ddr.dtsi"
#include "imx8-ss-lsio.dtsi"
};
#include "imx8qxp-ss-adma.dtsi"
#include "imx8qxp-ss-conn.dtsi"
#include "imx8qxp-ss-lsio.dtsi"