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Merge tag 'pinctrl-qcom-updates-for-v7.3-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux into devel

Browse Source 
Qualcomm pinctrl updates for v7.3-rc1

New drivers:
- add pinctrl drivers for Maili TLMM and Elize LPASS LPI TLMM controllers

Driver updates:
- acknowledge interrupts for the PDC interrupt controller in pinctrl-msm
- implement irq_get/set_irqchip_state() for pinctrl-msm
- add support for a new model to Qualcomm pinctrl-spmi-gpio
- drop some dead code from qcom pinctrl modules

Devicetree bindings:
- document new TLMM controllers and the new model for the SPMI GPIO

Signed-off-by: Linus Walleij <linusw@kernel.org>
This commit is contained in:
Linus Walleij
2026-08-16 18:59:43 +02:00
parent e4c90e39c9 1860fb0be2
commit d067f0f4c9
12 changed files with 2304 additions and 132 deletions
Download Patch File Download Diff File Expand all files Collapse all files

120
Documentation/devicetree/bindings/pinctrl/qcom,maili-tlmm.yaml Normal file
View File

@@ -0,0 +1,120 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,maili-tlmm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies, Inc. Maili TLMM block
maintainers:
- Jingyi Wang <jingyi.wang@oss.qualcomm.com>
description:
Top Level Mode Multiplexer pin controller in Qualcomm Maili SoC.
allOf:
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
properties:
compatible:
const: qcom,maili-tlmm
reg:
maxItems: 1
interrupts:
maxItems: 1
gpio-reserved-ranges:
minItems: 1
maxItems: 113
gpio-line-names:
maxItems: 226
patternProperties:
"-state$":
oneOf:
- $ref: "#/$defs/qcom-maili-tlmm-state"
- patternProperties:
"-pins$":
$ref: "#/$defs/qcom-maili-tlmm-state"
additionalProperties: false
$defs:
qcom-maili-tlmm-state:
type: object
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
unevaluatedProperties: false
properties:
pins:
description:
List of gpio pins affected by the properties specified in this
subnode.
items:
oneOf:
- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-9]|21[0-9]|22[0-5])$"
- enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ]
minItems: 1
maxItems: 36
function:
description:
Specify the alternative function to be configured for the specified
pins.
enum: [ gpio, aoss_cti, atest_char, atest_usb, audio_ext_mclk,
audio_ref_clk, cam_mclk, cci_async_in, cci_i2c0, cci_i2c1,
cci_i2c2, cci_i2c3, cci_timer, coex_espmi, coex_uart1_rx,
coex_uart1_tx, dbg_out_clk, ddr_bist, ddr_pxi, dp_hot, egpio,
gcc_gp, gnss_adc, host2wlan_sol, host_rst, i2chub0_se0,
i2chub0_se1, i2chub0_se2, i2chub0_se3, i2chub0_se4, i2s0, i2s1,
ibi_i3c, ibi_i3c_qup5_se0, jitter_bist, mdp_esync0, mdp_esync1,
mdp_esync2, mdp_vsync, mdp_vsync_e, mdp_vsync_p, mdp_vsync0_out,
mdp_vsync1_out, mdp_vsync2_out, mdp_vsync3_out, mdp_vsync5_out,
modem_pps_in, modem_pps_out, nav_gpio, nav_gpio0, nav_gpio3,
nav_rffe, pcie0_clk_req_n, pcie1_clk_req_n, pcie1_rst_n,
phase_flag, pll_bist_sync, pll_clk_aux, qdss_cti, qlink, qspi,
qspi_clk, qspi_cs, qup1_se0, qup1_se1, qup1_se2, qup1_se3,
qup1_se4, qup1_se5, qup1_se6, qup1_se7, qup2_se0, qup2_se1,
qup2_se2, qup2_se3, qup2_se4_01, qup2_se4_23, qup3_se0,
qup3_se1, qup3_se2, qup3_se3, qup3_se4, qup3_se5, qup4_se0,
qup4_se1, qup4_se2, qup4_se3_01, qup4_se3_23, qup4_se3_l3,
qup4_se4_01, qup4_se4_23, qup4_se4_l3, qup5_se0, rng_rosc,
sd_write_protect, sdc2_clk, sdc2_cmd, sdc2_data, sdc2_rclk,
sdc4_clk, sdc4_cmd, sdc4_data, sys_throttle, tb_trig_sdc,
tmess_rng, tsense_clm, tsense_pwm, uim0, uim1, usb0_hs, usb_phy,
vfr, vsense_trigger_mirnat, wcn_sw ]
required:
- pins
required:
- compatible
- reg
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
tlmm: pinctrl@f100000 {
compatible = "qcom,maili-tlmm";
reg = <0x0f100000 0x300000>;
interrupts = <GIC_ESPI 272 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&tlmm 0 0 227>;
interrupt-controller;
#interrupt-cells = <2>;
qup-uart7-state {
pins = "gpio62", "gpio63";
function = "qup1_se7";
};
};
...

18
Documentation/devicetree/bindings/pinctrl/qcom,milos-lpass-lpi-pinctrl.yaml
View File

@@ -15,9 +15,12 @@ description:
properties:
compatible:
const: qcom,milos-lpass-lpi-pinctrl
enum:
- qcom,eliza-lpass-lpi-pinctrl
- qcom,milos-lpass-lpi-pinctrl
reg:
minItems: 1
items:
- description: LPASS LPI TLMM Control and Status registers
- description: LPASS LPI MCC registers
@@ -74,6 +77,19 @@ $defs:
allOf:
- $ref: qcom,lpass-lpi-common.yaml#
- if:
properties:
compatible:
const: qcom,eliza-lpass-lpi-pinctrl
then:
properties:
reg:
maxItems: 1
else:
properties:
reg:
minItems: 2
required:
- compatible
- reg

3
Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml
View File

@@ -62,6 +62,7 @@ properties:
- qcom,pmc8380-gpio
- qcom,pmcx0102-gpio
- qcom,pmd8028-gpio
- qcom,pmg1110-gpio
- qcom,pmh0101-gpio
- qcom,pmh0104-gpio
- qcom,pmh0110-gpio
@@ -155,6 +156,7 @@ allOf:
- qcom,pm8450-gpio
- qcom,pm8916-gpio
- qcom,pmd8028-gpio
- qcom,pmg1110-gpio
- qcom,pmk8350-gpio
- qcom,pmr735a-gpio
- qcom,pmr735b-gpio
@@ -496,6 +498,7 @@ $defs:
- gpio1-gpio22 for pma8084
- gpio1-gpio14 for pmcx0102
- gpio1-gpio4 for pmd8028
- gpio1-gpio4 for pmg1110
- gpio1-gpio18 for pmh0101
- gpio1-gpio8 for pmh0104
- gpio1-gpio14 for pmh0110

548
drivers/irqchip/qcom-pdc.c
View File

@@ -20,22 +20,19 @@
#include <linux/spinlock.h>
#include <linux/slab.h>
#include <linux/types.h>
#include <linux/firmware/qcom/qcom_scm.h>
#define PDC_MAX_GPIO_IRQS 256
#define PDC_DRV_SIZE 0x10000
/* Valid only on HW version < 3.2 */
#define IRQ_ENABLE_BANK 0x10
#define IRQ_ENABLE_BANK_MAX (IRQ_ENABLE_BANK + BITS_TO_BYTES(PDC_MAX_GPIO_IRQS))
#define PDC_MAX_IRQS 256
#define IRQ_ENABLE_BANK_MAX BITS_TO_BYTES(PDC_MAX_IRQS)
#define IRQ_ENABLE_BANK_INDEX_MASK GENMASK(31, 5)
#define IRQ_ENABLE_BANK_BIT_MASK GENMASK(4, 0)
#define IRQ_i_CFG 0x110
/* Valid only on HW version >= 3.2 */
#define IRQ_i_CFG_IRQ_ENABLE 3
#define IRQ_i_CFG_TYPE_MASK GENMASK(2, 0)
/* Secure DRV register to configure the PDC mode via qcom_scm_io_writel() */
#define PDC_GPIO_INT_CTL_ENABLE 0xb2045e8
#define PDC_PASS_THROUGH_MODE 0x0
#define PDC_SECONDARY_MODE 0x1
#define PDC_DRV_SIZE 0x10000
#define PDC_VERSION_REG 0x1000
#define PDC_VERSION_MAJOR GENMASK(23, 16)
#define PDC_VERSION_MINOR GENMASK(15, 8)
@@ -46,22 +43,149 @@
/* Notable PDC versions */
#define PDC_VERSION_3_2 PDC_VERSION(3, 2, 0)
#define PDC_VERSION_3_0 PDC_VERSION(3, 0, 0)
#define PDC_VERSION_2_7 PDC_VERSION(2, 7, 0)
/*
* PDC Hardware registers layout per version:
*
* IRQ_ENABLE_BANK[b], b = 0....BITS_TO_BYTES(PDC_MAX_IRQS)
* IRQ_CFG[n], n = 0....PDC_MAX_IRQS
*
* +---------------------------------------------------------------+
* | v2.7 | v3.0 | v3.2 |
* |---------------------------------------------------------------|
* | BASE | BASE | BASE |
* |---------------------------------------------------------------|
* | |
* | IRQ_ENABLE_BANK | IRQ_ENABLE_BANK | NA |
* |---------------------------------------------------------------|
* | IRQ_CFG | IRQ_CFG | IRQ_CFG |
* | | | |
* | | | [31:6] Unused |
* | | [31:5] Unused | [5] GPIO_STATUS |
* | | [4] GPIO_STATUS| [4] GPIO_MASK |
* | [31:3] Unused | [3] GPIO_MASK | [3] IRQ_ENABLE |
* | [0:2] Type | [0:2] Type | [0:2] Type |
* |---------------------------------------------------------------|
* | IRQ_PARAM | IRQ_PARAM | IRQ_PARAM |
* | | |
* | [15:8] NUM_GPIO | [15:8] NUM_GPIO | [15:8] NUM_GPIO |
* | [7:0] NUM_SPI | [7:0] NUM_SPI | [7:0] NUM_SPI |
* +---------------------------------------------------------------+
*/
/**
* struct pdc_regs: PDC registers location
*
* @irq_en_reg: IRQ_ENABLE_BANK register location
* @irq_cfg_reg: IRQ_CFG register location
* @irq_param_reg: IRQ_PARAM register location
*/
struct pdc_regs {
u32 irq_en_reg;
u32 irq_cfg_reg;
u32 irq_param_reg;
};
/**
* struct pdc_irq_cfg: bit fields for PDC IRQ_CFG register
*
* @gpio_irq_sts: bit number for GPIO_STATUS field
* @gpio_irq_mask: bit number for GPIO_MASK field
* @irq_enable: bit number for IRQ_ENABLE field
* @irq_type: GENMASK for IRQ_TYPE field
*/
struct pdc_irq_cfg {
u32 gpio_irq_sts;
u32 gpio_irq_mask;
u32 irq_enable;
u32 irq_type;
};
/**
* struct pdc_desc: PDC driver state
*
* @base: PDC base register for DRV2 / HLOS
* @prev_base: PDC DRV1 base, applicable only for x1e RTL bug.
* @version: PDC version
* @num_spis: Total number of direct SPI interrupts
* @region: PDC interrupt continuous range
* @region_cnt: Total PDC ranges
* @mode: PDC_PASS_THROUGH_MODE or PDC_SECONDARY_MODE
* @x1e_quirk: x1e H/W Bug handling
* @lock: lock for IRQ_ENABLE_BANK protection
* @regs: PDC regs (IRQ_ENABLE_BANK and IRQ_CFG)
* @cfg_fields: Fields of IRQ_CFG reg
* @enable_intr: pointer to enable function based on PDC version
* @unmask_gpio: pointer to GPIO irq unmask function
* @clear_gpio: pointer to GPIO irq clear function
*/
struct pdc_desc {
void __iomem *base;
void __iomem *prev_base;
u32 version;
u32 num_spis;
struct pdc_pin_region *region;
int region_cnt;
bool x1e_quirk;
u8 mode;
raw_spinlock_t lock;
const struct pdc_regs *regs;
const struct pdc_irq_cfg *cfg_fields;
void (*enable_intr)(int pin_out, bool on);
void (*unmask_gpio)(int pin_out, bool on);
void (*clear_gpio)(int pin_out);
};
static const struct pdc_regs pdc_v3_2 = {
.irq_cfg_reg = 0x110,
.irq_param_reg = 0x100c,
};
static const struct pdc_irq_cfg pdc_cfg_v3_2 = {
.gpio_irq_sts = 5,
.gpio_irq_mask = 4,
.irq_enable = 3,
.irq_type = GENMASK(2, 0),
};
static const struct pdc_regs pdc_v3_0 = {
.irq_en_reg = 0x10,
.irq_cfg_reg = 0x110,
.irq_param_reg = 0x100c,
};
static const struct pdc_irq_cfg pdc_cfg_v3_0 = {
.gpio_irq_sts = 4,
.gpio_irq_mask = 3,
.irq_type = GENMASK(2, 0),
};
static const struct pdc_regs pdc_v2_7 = {
.irq_en_reg = 0x10,
.irq_cfg_reg = 0x110,
.irq_param_reg = 0x100c,
};
static const struct pdc_irq_cfg pdc_cfg_v2_7 = {
.irq_type = GENMASK(2, 0),
};
struct pdc_pin_region {
u32 pin_base;
u32 parent_base;
u32 cnt;
u32 pin_base;
u32 parent_base;
u32 cnt;
};
#define pin_to_hwirq(r, p) ((r)->parent_base + (p) - (r)->pin_base)
static DEFINE_RAW_SPINLOCK(pdc_lock);
static void __iomem *pdc_base;
static void __iomem *pdc_prev_base;
static struct pdc_pin_region *pdc_region;
static int pdc_region_cnt;
static unsigned int pdc_version;
static bool pdc_x1e_quirk;
static struct pdc_desc *pdc;
static void pdc_base_reg_write(void __iomem *base, int reg, u32 i, u32 val)
{
@@ -70,12 +194,21 @@ static void pdc_base_reg_write(void __iomem *base, int reg, u32 i, u32 val)
static void pdc_reg_write(int reg, u32 i, u32 val)
{
pdc_base_reg_write(pdc_base, reg, i, val);
pdc_base_reg_write(pdc->base, reg, i, val);
}
static u32 pdc_reg_read(int reg, u32 i)
{
return readl_relaxed(pdc_base + reg + i * sizeof(u32));
return readl_relaxed(pdc->base + reg + i * sizeof(u32));
}
static inline bool pdc_pin_is_gpio(int pin_out)
{
/*
* PDC allocates direct SPIs at the beginning and
* all GPIOs as SPIs are allocated after direct SPIs.
*/
return pin_out >= pdc->num_spis;
}
static void pdc_x1e_irq_enable_write(u32 bank, u32 enable)
@@ -86,24 +219,24 @@ static void pdc_x1e_irq_enable_write(u32 bank, u32 enable)
switch (bank) {
case 0 ... 1:
/* Use previous DRV (client) region and shift to bank 3-4 */
base = pdc_prev_base;
base = pdc->prev_base;
bank += 3;
break;
case 2 ... 4:
/* Use our own region and shift to bank 0-2 */
base = pdc_base;
base = pdc->base;
bank -= 2;
break;
case 5:
/* No fixup required for bank 5 */
base = pdc_base;
base = pdc->base;
break;
default:
WARN_ON(1);
return;
}
pdc_base_reg_write(base, IRQ_ENABLE_BANK, bank, enable);
pdc_base_reg_write(base, pdc->regs->irq_en_reg, bank, enable);
}
static void pdc_enable_intr_bank(int pin_out, bool on)
@@ -114,52 +247,97 @@ static void pdc_enable_intr_bank(int pin_out, bool on)
index = FIELD_GET(IRQ_ENABLE_BANK_INDEX_MASK, pin_out);
mask = FIELD_GET(IRQ_ENABLE_BANK_BIT_MASK, pin_out);
enable = pdc_reg_read(IRQ_ENABLE_BANK, index);
guard(raw_spinlock_irqsave)(&pdc->lock);
enable = pdc_reg_read(pdc->regs->irq_en_reg, index);
__assign_bit(mask, &enable, on);
if (pdc_x1e_quirk)
if (pdc->x1e_quirk)
pdc_x1e_irq_enable_write(index, enable);
else
pdc_reg_write(IRQ_ENABLE_BANK, index, enable);
pdc_reg_write(pdc->regs->irq_en_reg, index, enable);
}
static void pdc_clear_gpio_cfg(int pin_out)
{
unsigned long gpio_sts;
gpio_sts = pdc_reg_read(pdc->regs->irq_cfg_reg, pin_out);
__clear_bit(pdc->cfg_fields->gpio_irq_sts, &gpio_sts);
pdc_reg_write(pdc->regs->irq_cfg_reg, pin_out, gpio_sts);
}
static void pdc_unmask_gpio_cfg(int pin_out, bool unmask)
{
unsigned long gpio_mask;
gpio_mask = pdc_reg_read(pdc->regs->irq_cfg_reg, pin_out);
__assign_bit(pdc->cfg_fields->gpio_irq_mask, &gpio_mask, !unmask);
pdc_reg_write(pdc->regs->irq_cfg_reg, pin_out, gpio_mask);
}
static void pdc_enable_intr_cfg(int pin_out, bool on)
{
unsigned long enable = pdc_reg_read(IRQ_i_CFG, pin_out);
unsigned long enable = pdc_reg_read(pdc->regs->irq_cfg_reg, pin_out);
__assign_bit(IRQ_i_CFG_IRQ_ENABLE, &enable, on);
pdc_reg_write(IRQ_i_CFG, pin_out, enable);
__assign_bit(pdc->cfg_fields->irq_enable, &enable, on);
pdc_reg_write(pdc->regs->irq_cfg_reg, pin_out, enable);
}
static void __pdc_enable_intr(int pin_out, bool on)
static void qcom_pdc_gic_secondary_disable(struct irq_data *d)
{
if (pdc_version < PDC_VERSION_3_2)
pdc_enable_intr_bank(pin_out, on);
else
pdc_enable_intr_cfg(pin_out, on);
}
static void pdc_enable_intr(struct irq_data *d, bool on)
{
unsigned long flags;
raw_spin_lock_irqsave(&pdc_lock, flags);
__pdc_enable_intr(d->hwirq, on);
raw_spin_unlock_irqrestore(&pdc_lock, flags);
pdc->enable_intr(d->hwirq, false);
pdc->unmask_gpio(d->hwirq, false);
irq_chip_disable_parent(d);
}
static void qcom_pdc_gic_disable(struct irq_data *d)
{
pdc_enable_intr(d, false);
pdc->enable_intr(d->hwirq, false);
irq_chip_disable_parent(d);
}
static void qcom_pdc_gic_enable(struct irq_data *d)
{
pdc_enable_intr(d, true);
pdc->enable_intr(d->hwirq, true);
irq_chip_enable_parent(d);
}
static void qcom_pdc_gic_secondary_enable(struct irq_data *d)
{
pdc->enable_intr(d->hwirq, true);
pdc->unmask_gpio(d->hwirq, true);
irq_chip_enable_parent(d);
}
static void qcom_pdc_secondary_ack(struct irq_data *d)
{
if (!irqd_is_level_type(d))
pdc->clear_gpio(d->hwirq);
}
static void qcom_pdc_gic_secondary_eoi(struct irq_data *d)
{
if (irqd_is_level_type(d))
pdc->clear_gpio(d->hwirq);
irq_chip_eoi_parent(d);
}
static void qcom_pdc_secondary_mask(struct irq_data *d)
{
pdc->enable_intr(d->hwirq, false);
pdc->unmask_gpio(d->hwirq, false);
irq_chip_mask_parent(d);
}
static void qcom_pdc_secondary_unmask(struct irq_data *d)
{
pdc->enable_intr(d->hwirq, true);
pdc->unmask_gpio(d->hwirq, true);
irq_chip_unmask_parent(d);
}
/*
* GIC does not handle falling edge or active low. To allow falling edge and
* active low interrupts to be handled at GIC, PDC has an inverter that inverts
@@ -186,18 +364,18 @@ enum pdc_irq_config_bits {
/**
* qcom_pdc_gic_set_type: Configure PDC for the interrupt
*
* @d: the interrupt data
* @d: the interrupt data
* @type: the interrupt type
*
* If @type is edge triggered, forward that as Rising edge as PDC
* takes care of converting falling edge to rising edge signal
* If @type is edge triggered, forward that as rising edge as PDC
* takes care of converting all edge types to rising edge signal
* If @type is level, then forward that as level high as PDC
* takes care of converting falling edge to rising edge signal
* takes care of converting all level types to level high signal
*/
static int qcom_pdc_gic_set_type(struct irq_data *d, unsigned int type)
{
enum pdc_irq_config_bits pdc_type;
enum pdc_irq_config_bits old_pdc_type;
enum pdc_irq_config_bits pdc_type;
int ret;
switch (type) {
@@ -224,9 +402,75 @@ static int qcom_pdc_gic_set_type(struct irq_data *d, unsigned int type)
return -EINVAL;
}
old_pdc_type = pdc_reg_read(IRQ_i_CFG, d->hwirq);
pdc_type |= (old_pdc_type & ~IRQ_i_CFG_TYPE_MASK);
pdc_reg_write(IRQ_i_CFG, d->hwirq, pdc_type);
old_pdc_type = pdc_reg_read(pdc->regs->irq_cfg_reg, d->hwirq);
pdc_type |= (old_pdc_type & ~pdc->cfg_fields->irq_type);
pdc_reg_write(pdc->regs->irq_cfg_reg, d->hwirq, pdc_type);
ret = irq_chip_set_type_parent(d, type);
if (ret)
return ret;
/*
* When we change types the PDC can give a phantom interrupt.
* Clear it. Specifically the phantom shows up when reconfiguring
* polarity of interrupt without changing the state of the signal
* but let's be consistent and clear it always.
*
* Doing this works because we have IRQCHIP_SET_TYPE_MASKED so the
* interrupt will be cleared before the rest of the system sees it.
*/
if (old_pdc_type != pdc_type)
irq_chip_set_parent_state(d, IRQCHIP_STATE_PENDING, false);
return 0;
}
/**
* qcom_pdc_gic_set_type: Configure PDC for the interrupt
*
* @d: the interrupt data
* @type: the interrupt type
*
* All @type are forwarded as level high type to parent GIC
*/
static int qcom_pdc_gic_secondary_set_type(struct irq_data *d, unsigned int type)
{
enum pdc_irq_config_bits old_pdc_type;
enum pdc_irq_config_bits pdc_type;
int ret;
switch (type) {
case IRQ_TYPE_EDGE_RISING:
pdc_type = PDC_EDGE_RISING;
break;
case IRQ_TYPE_EDGE_FALLING:
pdc_type = PDC_EDGE_FALLING;
break;
case IRQ_TYPE_EDGE_BOTH:
pdc_type = PDC_EDGE_DUAL;
break;
case IRQ_TYPE_LEVEL_HIGH:
pdc_type = PDC_LEVEL_HIGH;
break;
case IRQ_TYPE_LEVEL_LOW:
pdc_type = PDC_LEVEL_LOW;
break;
default:
WARN_ON(1);
return -EINVAL;
}
old_pdc_type = pdc_reg_read(pdc->regs->irq_cfg_reg, d->hwirq);
pdc_type |= (old_pdc_type & ~pdc->cfg_fields->irq_type);
pdc_reg_write(pdc->regs->irq_cfg_reg, d->hwirq, pdc_type);
/*
* PDC forwards GPIOs as level high to GIC in secondary
* mode. Update the type and clear any previously latched
* phantom interrupt at PDC.
*/
type = IRQ_TYPE_LEVEL_HIGH;
pdc->clear_gpio(d->hwirq);
ret = irq_chip_set_type_parent(d, type);
if (ret)
@@ -266,14 +510,32 @@ static struct irq_chip qcom_pdc_gic_chip = {
.irq_set_affinity = irq_chip_set_affinity_parent,
};
static struct irq_chip qcom_pdc_gic_secondary_chip = {
.name = "PDC",
.irq_ack = qcom_pdc_secondary_ack,
.irq_eoi = qcom_pdc_gic_secondary_eoi,
.irq_mask = qcom_pdc_secondary_mask,
.irq_unmask = qcom_pdc_secondary_unmask,
.irq_disable = qcom_pdc_gic_secondary_disable,
.irq_enable = qcom_pdc_gic_secondary_enable,
.irq_get_irqchip_state = irq_chip_get_parent_state,
.irq_set_irqchip_state = irq_chip_set_parent_state,
.irq_retrigger = irq_chip_retrigger_hierarchy,
.irq_set_type = qcom_pdc_gic_secondary_set_type,
.flags = IRQCHIP_MASK_ON_SUSPEND |
IRQCHIP_SET_TYPE_MASKED |
IRQCHIP_SKIP_SET_WAKE |
IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND,
.irq_set_vcpu_affinity = irq_chip_set_vcpu_affinity_parent,
.irq_set_affinity = irq_chip_set_affinity_parent,
};
static struct pdc_pin_region *get_pin_region(int pin)
{
int i;
for (i = 0; i < pdc_region_cnt; i++) {
if (pin >= pdc_region[i].pin_base &&
pin < pdc_region[i].pin_base + pdc_region[i].cnt)
return &pdc_region[i];
for (int i = 0; i < pdc->region_cnt; i++) {
if (pin >= pdc->region[i].pin_base &&
pin < pdc->region[i].pin_base + pdc->region[i].cnt)
return &pdc->region[i];
}
return NULL;
@@ -301,24 +563,45 @@ static int qcom_pdc_alloc(struct irq_domain *domain, unsigned int virq,
if (ret)
return ret;
/*
* PDC secondary chip is only set for the GPIO interrupts as SPIs.
* Direct SPI interrupts are still in pass through mode (no latching
* at PDC).
*/
if (pdc->mode == PDC_SECONDARY_MODE && pdc_pin_is_gpio(hwirq)) {
ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
&qcom_pdc_gic_secondary_chip,
NULL);
if (ret)
return ret;
/* Secondary mode converts all interrupts to LEVEL HIGH type */
type = IRQ_TYPE_LEVEL_HIGH;
} else {
ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
&qcom_pdc_gic_chip,
NULL);
if (ret)
return ret;
if (type & IRQ_TYPE_EDGE_BOTH)
type = IRQ_TYPE_EDGE_RISING;
if (type & IRQ_TYPE_LEVEL_MASK)
type = IRQ_TYPE_LEVEL_HIGH;
}
region = get_pin_region(hwirq);
if (!region)
return irq_domain_disconnect_hierarchy(domain->parent, virq);
if (type & IRQ_TYPE_EDGE_BOTH)
type = IRQ_TYPE_EDGE_RISING;
if (type & IRQ_TYPE_LEVEL_MASK)
type = IRQ_TYPE_LEVEL_HIGH;
parent_fwspec.fwnode = domain->parent->fwnode;
parent_fwspec.param_count = 3;
parent_fwspec.param[0] = 0;
parent_fwspec.param[1] = pin_to_hwirq(region, hwirq);
parent_fwspec.param[2] = type;
return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs,
&parent_fwspec);
return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, &parent_fwspec);
}
static const struct irq_domain_ops qcom_pdc_ops = {
@@ -327,52 +610,56 @@ static const struct irq_domain_ops qcom_pdc_ops = {
.free = irq_domain_free_irqs_common,
};
static int pdc_setup_pin_mapping(struct device_node *np)
static int pdc_setup_pin_mapping(struct device *dev)
{
int ret, n, i;
struct device_node *np = dev->of_node;
int ret, n;
n = of_property_count_elems_of_size(np, "qcom,pdc-ranges", sizeof(u32));
if (n <= 0 || n % 3)
return -EINVAL;
pdc_region_cnt = n / 3;
pdc_region = kzalloc_objs(*pdc_region, pdc_region_cnt);
if (!pdc_region) {
pdc_region_cnt = 0;
pdc->region_cnt = n / 3;
pdc->region = devm_kcalloc(dev, pdc->region_cnt, sizeof(*pdc->region), GFP_KERNEL);
if (!pdc->region) {
pdc->region_cnt = 0;
return -ENOMEM;
}
for (n = 0; n < pdc_region_cnt; n++) {
ret = of_property_read_u32_index(np, "qcom,pdc-ranges",
n * 3 + 0,
&pdc_region[n].pin_base);
for (n = 0; n < pdc->region_cnt; n++) {
ret = of_property_read_u32_index(np, "qcom,pdc-ranges", n * 3 + 0,
&pdc->region[n].pin_base);
if (ret)
return ret;
ret = of_property_read_u32_index(np, "qcom,pdc-ranges",
n * 3 + 1,
&pdc_region[n].parent_base);
ret = of_property_read_u32_index(np, "qcom,pdc-ranges", n * 3 + 1,
&pdc->region[n].parent_base);
if (ret)
return ret;
ret = of_property_read_u32_index(np, "qcom,pdc-ranges",
n * 3 + 2,
&pdc_region[n].cnt);
ret = of_property_read_u32_index(np, "qcom,pdc-ranges", n * 3 + 2,
&pdc->region[n].cnt);
if (ret)
return ret;
for (i = 0; i < pdc_region[n].cnt; i++)
__pdc_enable_intr(i + pdc_region[n].pin_base, 0);
for (int i = 0; i < pdc->region[n].cnt; i++) {
if (pdc_pin_is_gpio(i + pdc->region[n].pin_base) &&
pdc->mode == PDC_SECONDARY_MODE)
pdc->clear_gpio(i + pdc->region[n].pin_base);
pdc->enable_intr(i + pdc->region[n].pin_base, false);
}
}
return 0;
}
static int qcom_pdc_probe(struct platform_device *pdev, struct device_node *parent)
{
struct irq_domain *parent_domain, *pdc_domain;
struct device_node *node = pdev->dev.of_node;
struct device *dev = &pdev->dev;
resource_size_t res_size;
struct resource res;
u32 irq_param;
int ret;
/* compat with old sm8150 DT which had very small region for PDC */
@@ -383,6 +670,34 @@ static int qcom_pdc_probe(struct platform_device *pdev, struct device_node *pare
if (res_size > resource_size(&res))
pr_warn("%pOF: invalid reg size, please fix DT\n", node);
pdc = devm_kzalloc(dev, sizeof(*pdc), GFP_KERNEL);
if (!pdc)
return -ENOMEM;
pdc->base = devm_ioremap(dev, res.start, res_size);
if (!pdc->base) {
pr_err("%pOF: unable to map PDC registers\n", node);
return -ENXIO;
}
pdc->version = pdc_reg_read(PDC_VERSION_REG, 0);
if (pdc->version >= PDC_VERSION_3_2) {
pdc->cfg_fields = &pdc_cfg_v3_2;
pdc->regs = &pdc_v3_2;
pdc->enable_intr = pdc_enable_intr_cfg;
} else if (pdc->version >= PDC_VERSION_3_0) {
pdc->cfg_fields = &pdc_cfg_v3_0;
pdc->regs = &pdc_v3_0;
pdc->enable_intr = pdc_enable_intr_bank;
} else {
pdc->cfg_fields = &pdc_cfg_v2_7;
pdc->regs = &pdc_v2_7;
pdc->enable_intr = pdc_enable_intr_bank;
}
pdc->mode = PDC_PASS_THROUGH_MODE;
/*
* PDC has multiple DRV regions, each one provides the same set of
* registers for a particular client in the system. Due to a hardware
@@ -392,57 +707,54 @@ static int qcom_pdc_probe(struct platform_device *pdev, struct device_node *pare
* region with the expected offset to preserve support for old DTs.
*/
if (of_device_is_compatible(node, "qcom,x1e80100-pdc")) {
pdc_prev_base = ioremap(res.start - PDC_DRV_SIZE, IRQ_ENABLE_BANK_MAX);
if (!pdc_prev_base) {
pdc->prev_base = devm_ioremap(dev, res.start - PDC_DRV_SIZE,
pdc->regs->irq_en_reg + IRQ_ENABLE_BANK_MAX);
if (!pdc->prev_base) {
pr_err("%pOF: unable to map previous PDC DRV region\n", node);
return -ENXIO;
}
pdc_x1e_quirk = true;
pdc->x1e_quirk = true;
if (!qcom_scm_is_available())
return -EPROBE_DEFER;
ret = qcom_scm_io_writel(PDC_GPIO_INT_CTL_ENABLE, PDC_PASS_THROUGH_MODE);
if (ret) {
pdc->mode = PDC_SECONDARY_MODE;
pdc->unmask_gpio = pdc_unmask_gpio_cfg;
pdc->clear_gpio = pdc_clear_gpio_cfg;
}
}
pdc_base = ioremap(res.start, res_size);
if (!pdc_base) {
pr_err("%pOF: unable to map PDC registers\n", node);
ret = -ENXIO;
goto fail;
}
pdc_version = pdc_reg_read(PDC_VERSION_REG, 0);
irq_param = pdc_reg_read(pdc->regs->irq_param_reg, 0);
pdc->num_spis = FIELD_GET(GENMASK(7, 0), irq_param);
parent_domain = irq_find_host(parent);
if (!parent_domain) {
pr_err("%pOF: unable to find PDC's parent domain\n", node);
ret = -ENXIO;
goto fail;
return -ENXIO;
}
ret = pdc_setup_pin_mapping(node);
raw_spin_lock_init(&pdc->lock);
ret = pdc_setup_pin_mapping(dev);
if (ret) {
pr_err("%pOF: failed to init PDC pin-hwirq mapping\n", node);
goto fail;
return ret;
}
pdc_domain = irq_domain_create_hierarchy(parent_domain,
IRQ_DOMAIN_FLAG_QCOM_PDC_WAKEUP,
PDC_MAX_GPIO_IRQS,
of_fwnode_handle(node),
&qcom_pdc_ops, NULL);
pdc_domain = irq_domain_create_hierarchy(parent_domain, IRQ_DOMAIN_FLAG_QCOM_PDC_WAKEUP,
PDC_MAX_IRQS, of_fwnode_handle(node),
&qcom_pdc_ops, NULL);
if (!pdc_domain) {
pr_err("%pOF: PDC domain add failed\n", node);
ret = -ENOMEM;
goto fail;
return -ENOMEM;
}
irq_domain_update_bus_token(pdc_domain, DOMAIN_BUS_WAKEUP);
return 0;
fail:
kfree(pdc_region);
iounmap(pdc_base);
iounmap(pdc_prev_base);
return ret;
}
IRQCHIP_PLATFORM_DRIVER_BEGIN(qcom_pdc)

10
drivers/pinctrl/qcom/Kconfig.msm
View File

@@ -153,6 +153,16 @@ config PINCTRL_KAANAPALI
Qualcomm Technologies Inc TLMM block found on the Qualcomm
Technologies Inc Kaanapali platform.
config PINCTRL_MAILI
tristate "Qualcomm Technologies Inc Maili pin controller driver"
depends on ARM64 || COMPILE_TEST
default ARCH_QCOM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm Technologies Inc TLMM block found on the Maili platform.
Say Y here to compile statically, or M here to compile it as a module.
If unsure, say N.
config PINCTRL_MSM8226
tristate "Qualcomm 8226 pin controller driver"
depends on ARM || COMPILE_TEST

1
drivers/pinctrl/qcom/Makefile
View File

@@ -17,6 +17,7 @@ obj-$(CONFIG_PINCTRL_IPQ6018) += pinctrl-ipq6018.o
obj-$(CONFIG_PINCTRL_IPQ9574) += pinctrl-ipq9574.o
obj-$(CONFIG_PINCTRL_IPQ9650) += pinctrl-ipq9650.o
obj-$(CONFIG_PINCTRL_KAANAPALI) += pinctrl-kaanapali.o
obj-$(CONFIG_PINCTRL_MAILI) += pinctrl-maili.o
obj-$(CONFIG_PINCTRL_MSM8226) += pinctrl-msm8226.o
obj-$(CONFIG_PINCTRL_MSM8660) += pinctrl-msm8660.o
obj-$(CONFIG_PINCTRL_MSM8960) += pinctrl-msm8960.o

1625
drivers/pinctrl/qcom/pinctrl-maili.c Normal file
View File

File diff suppressed because it is too large Load Diff

40
drivers/pinctrl/qcom/pinctrl-milos-lpass-lpi.c
View File

@@ -148,6 +148,33 @@ static const struct lpi_pingroup milos_groups[] = {
LPI_PINGROUP(22, LPI_NO_SLEW, i2s3_data, dmic4_data, ext_mclk1_e, _),
};
static const struct lpi_pingroup eliza_groups[] = {
LPI_PINGROUP(0, 11, swr_tx_clk, i2s0_clk, _, _),
LPI_PINGROUP(1, 11, swr_tx_data, i2s0_ws, _, _),
LPI_PINGROUP(2, 11, swr_tx_data, i2s0_data, _, _),
LPI_PINGROUP(3, 11, swr_rx_clk, i2s0_data, _, _),
LPI_PINGROUP(4, 11, swr_rx_data, i2s0_data, _, _),
LPI_PINGROUP(5, 11, swr_rx_data, ext_mclk1_c, i2s0_data, _),
LPI_PINGROUP(6, LPI_NO_SLEW, dmic1_clk, i2s1_clk, _, _),
LPI_PINGROUP(7, LPI_NO_SLEW, dmic1_data, i2s1_ws, _, _),
LPI_PINGROUP(8, LPI_NO_SLEW, dmic2_clk, i2s1_data, _, _),
LPI_PINGROUP(9, LPI_NO_SLEW, dmic2_data, i2s1_data, ext_mclk1_b, _),
LPI_PINGROUP(10, 11, wsa_swr_clk, i2s2_clk, _, _),
LPI_PINGROUP(11, 11, wsa_swr_data, i2s2_ws, _, _),
LPI_PINGROUP(12, LPI_NO_SLEW, dmic3_clk, i2s2_data, _, _),
LPI_PINGROUP(13, LPI_NO_SLEW, dmic3_data, i2s2_data, ext_mclk1_a, _),
LPI_PINGROUP(14, 11, swr_tx_data, ext_mclk1_d, _, _),
/* gpio15 - gpio18 do not really exist */
LPI_PINGROUP(15, 11, _, _, _, _),
LPI_PINGROUP(16, 11, _, _, _, _),
LPI_PINGROUP(17, LPI_NO_SLEW, _, _, _, _),
LPI_PINGROUP(18, LPI_NO_SLEW, _, _, _, _),
LPI_PINGROUP(19, LPI_NO_SLEW, i2s3_clk, slimbus_clk, qca_swr_clk, _),
LPI_PINGROUP(20, LPI_NO_SLEW, i2s3_ws, slimbus_data, qca_swr_data, _),
LPI_PINGROUP(21, LPI_NO_SLEW, i2s3_data, dmic4_clk, _, _),
LPI_PINGROUP(22, LPI_NO_SLEW, i2s3_data, dmic4_data, ext_mclk1_e, _),
};
static const struct lpi_function milos_functions[] = {
LPI_FUNCTION(gpio),
LPI_FUNCTION(dmic1_clk),
@@ -196,8 +223,21 @@ static const struct lpi_pinctrl_variant_data milos_lpi_data = {
.nfunctions = ARRAY_SIZE(milos_functions),
};
static const struct lpi_pinctrl_variant_data eliza_lpi_data = {
.pins = milos_lpi_pins,
.npins = ARRAY_SIZE(milos_lpi_pins),
.groups = eliza_groups,
.ngroups = ARRAY_SIZE(eliza_groups),
.functions = milos_functions,
.nfunctions = ARRAY_SIZE(milos_functions),
.flags = LPI_FLAG_SLEW_RATE_SAME_REG,
};
static const struct of_device_id lpi_pinctrl_of_match[] = {
{
.compatible = "qcom,eliza-lpass-lpi-pinctrl",
.data = &eliza_lpi_data,
}, {
.compatible = "qcom,milos-lpass-lpi-pinctrl",
.data = &milos_lpi_data,
},

63
drivers/pinctrl/qcom/pinctrl-msm.c
View File

@@ -810,8 +810,7 @@ static const struct gpio_chip msm_gpio_template = {
* Algorithm comes from Google's msmgpio driver.
*/
static void msm_gpio_update_dual_edge_pos(struct msm_pinctrl *pctrl,
const struct msm_pingroup *g,
struct irq_data *d)
const struct msm_pingroup *g)
{
int loop_limit = 100;
unsigned val, val2, intstat;
@@ -995,6 +994,16 @@ static void msm_gpio_irq_ack(struct irq_data *d)
if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) {
if (test_bit(d->hwirq, pctrl->dual_edge_irqs))
msm_gpio_update_dual_edge_parent(d);
/*
* During early initialization of the IRQ hierarchy,
* irq_ack() is called by __irq_set_handler() before
* the parent IRQ chip has been set up. This is why
* we additionally need to check for d->parent_data->chip.
*/
if (d->parent_data->chip && d->parent_data->chip->irq_ack)
irq_chip_ack_parent(d);
return;
}
@@ -1005,7 +1014,7 @@ static void msm_gpio_irq_ack(struct irq_data *d)
msm_ack_intr_status(pctrl, g);
if (test_bit(d->hwirq, pctrl->dual_edge_irqs))
msm_gpio_update_dual_edge_pos(pctrl, g, d);
msm_gpio_update_dual_edge_pos(pctrl, g);
raw_spin_unlock_irqrestore(&pctrl->lock, flags);
}
@@ -1035,8 +1044,6 @@ static void msm_gpio_irq_init_valid_mask(struct gpio_chip *gc,
const struct msm_pingroup *g;
int i;
bitmap_fill(valid_mask, ngpios);
for (i = 0; i < ngpios; i++) {
g = &pctrl->soc->groups[i];
@@ -1067,7 +1074,10 @@ static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type)
if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) {
clear_bit(d->hwirq, pctrl->dual_edge_irqs);
irq_set_handler_locked(d, handle_fasteoi_irq);
if (type & IRQ_TYPE_LEVEL_MASK)
irq_set_handler_locked(d, handle_fasteoi_irq);
else
irq_set_handler_locked(d, handle_fasteoi_ack_irq);
return 0;
}
@@ -1177,7 +1187,7 @@ static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type)
msm_ack_intr_status(pctrl, g);
if (test_bit(d->hwirq, pctrl->dual_edge_irqs))
msm_gpio_update_dual_edge_pos(pctrl, g, d);
msm_gpio_update_dual_edge_pos(pctrl, g);
raw_spin_unlock_irqrestore(&pctrl->lock, flags);
@@ -1303,6 +1313,43 @@ static int msm_gpio_irq_set_affinity(struct irq_data *d,
return -EINVAL;
}
static int msm_gpio_irq_set_irqchip_state(struct irq_data *d,
enum irqchip_irq_state which, bool val)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
const struct msm_pingroup *g = &pctrl->soc->groups[d->hwirq];
if (which != IRQCHIP_STATE_PENDING)
return -EINVAL;
if (test_bit(d->hwirq, pctrl->skip_wake_irqs))
return -EINVAL;
msm_writel_intr_status(val, pctrl, g);
return 0;
}
static int msm_gpio_irq_get_irqchip_state(struct irq_data *d,
enum irqchip_irq_state which, bool *val)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
const struct msm_pingroup *g = &pctrl->soc->groups[d->hwirq];
if (which != IRQCHIP_STATE_PENDING)
return -EINVAL;
if (test_bit(d->hwirq, pctrl->skip_wake_irqs))
return -EINVAL;
g = &pctrl->soc->groups[d->hwirq];
*val = msm_readl_intr_status(pctrl, g);
return 0;
}
static int msm_gpio_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu_info)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
@@ -1391,6 +1438,8 @@ static const struct irq_chip msm_gpio_irq_chip = {
.irq_request_resources = msm_gpio_irq_reqres,
.irq_release_resources = msm_gpio_irq_relres,
.irq_set_affinity = msm_gpio_irq_set_affinity,
.irq_set_irqchip_state = msm_gpio_irq_set_irqchip_state,
.irq_get_irqchip_state = msm_gpio_irq_get_irqchip_state,
.irq_set_vcpu_affinity = msm_gpio_irq_set_vcpu_affinity,
.flags = (IRQCHIP_MASK_ON_SUSPEND |
IRQCHIP_SET_TYPE_MASKED |

1
drivers/pinctrl/qcom/pinctrl-spmi-gpio.c
View File

@@ -1262,6 +1262,7 @@ static const struct of_device_id pmic_gpio_of_match[] = {
{ .compatible = "qcom,pmc8380-gpio", .data = (void *) 10 },
{ .compatible = "qcom,pmcx0102-gpio", .data = (void *)14 },
{ .compatible = "qcom,pmd8028-gpio", .data = (void *) 4 },
{ .compatible = "qcom,pmg1110-gpio", .data = (void *) 4 },
{ .compatible = "qcom,pmh0101-gpio", .data = (void *)18 },
{ .compatible = "qcom,pmh0104-gpio", .data = (void *)8 },
{ .compatible = "qcom,pmh0110-gpio", .data = (void *)14 },

4
drivers/pinctrl/qcom/pinctrl-x1e80100.c
View File

@@ -1836,9 +1836,7 @@ static const struct msm_pinctrl_soc_data x1e80100_pinctrl = {
.ngroups = ARRAY_SIZE(x1e80100_groups),
.ngpios = 239,
.wakeirq_map = x1e80100_pdc_map,
/* TODO: Enabling PDC currently breaks GPIO interrupts */
.nwakeirq_map = 0,
/* .nwakeirq_map = ARRAY_SIZE(x1e80100_pdc_map), */
.nwakeirq_map = ARRAY_SIZE(x1e80100_pdc_map),
.egpio_func = 9,
};

3
drivers/pinctrl/qcom/tlmm-test.c
View File

@@ -273,7 +273,6 @@ static void tlmm_test_low(struct kunit *test)
int i;
priv->intr_op = TLMM_TEST_COUNT | TLMM_TEST_OUTPUT_HIGH;
atomic_set(&priv->intr_op_remain, 9);
tlmm_output_high();
@@ -298,7 +297,6 @@ static void tlmm_test_high(struct kunit *test)
int i;
priv->intr_op = TLMM_TEST_COUNT | TLMM_TEST_OUTPUT_LOW;
atomic_set(&priv->intr_op_remain, 9);
tlmm_output_low();
@@ -521,7 +519,6 @@ static void tlmm_test_rising_while_disabled(struct kunit *test)
unsigned int before_edge;
priv->intr_op = TLMM_TEST_COUNT;
atomic_set(&priv->thread_op_remain, 10);
tlmm_output_low();