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drm/nouveau/gr/gf100-: make global pagepool actually global

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This was thought to be per-channel initially - it's not.  The backing
pages for the VMM mappings are shared for all channels.

- switches to more straight-forward patch interfaces
- prepares for sub-context support

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
This commit is contained in:
Ben Skeggs
2022-06-01 20:48:05 +10:00
parent ca081fff6e
commit d05095b53c
9 changed files with 71 additions and 50 deletions
Download Patch File Download Diff File Expand all files Collapse all files

32
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c
View File

@@ -991,6 +991,18 @@ gf100_grctx_pack_tpc[] = {
* PGRAPH context implementation
******************************************************************************/
void
gf100_grctx_patch_wr32(struct gf100_gr_chan *chan, u32 addr, u32 data)
{
if (unlikely(!chan->mmio)) {
nvkm_wr32(chan->gr->base.engine.subdev.device, addr, data);
return;
}
nvkm_wo32(chan->mmio, chan->mmio_nr++ * 4, addr);
nvkm_wo32(chan->mmio, chan->mmio_nr++ * 4, data);
}
int
gf100_grctx_mmio_data(struct gf100_grctx *info, u32 size, u32 align, bool priv)
{
@@ -1050,15 +1062,12 @@ gf100_grctx_generate_bundle(struct gf100_grctx *info)
}
void
gf100_grctx_generate_pagepool(struct gf100_grctx *info)
gf100_grctx_generate_pagepool(struct gf100_gr_chan *chan, u64 addr)
{
const struct gf100_grctx_func *grctx = info->gr->func->grctx;
const int s = 8;
const int b = mmio_vram(info, grctx->pagepool_size, (1 << s), true);
mmio_refn(info, 0x40800c, 0x00000000, s, b);
mmio_wr32(info, 0x408010, 0x80000000);
mmio_refn(info, 0x419004, 0x00000000, s, b);
mmio_wr32(info, 0x419008, 0x00000000);
gf100_grctx_patch_wr32(chan, 0x40800c, addr >> 8);
gf100_grctx_patch_wr32(chan, 0x408010, 0x80000000);
gf100_grctx_patch_wr32(chan, 0x419004, addr >> 8);
gf100_grctx_patch_wr32(chan, 0x419008, 0x00000000);
}
void
@@ -1362,8 +1371,9 @@ gf100_grctx_generate_floorsweep(struct gf100_gr *gr)
}
void
gf100_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info)
gf100_grctx_generate_main(struct gf100_gr_chan *chan, struct gf100_grctx *info)
{
struct gf100_gr *gr = chan->gr;
struct nvkm_device *device = gr->base.engine.subdev.device;
const struct gf100_grctx_func *grctx = gr->func->grctx;
u32 idle_timeout;
@@ -1385,7 +1395,7 @@ gf100_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info)
idle_timeout = nvkm_mask(device, 0x404154, 0xffffffff, 0x00000000);
grctx->pagepool(info);
grctx->pagepool(chan, chan->pagepool->addr);
grctx->bundle(info);
grctx->attrib(info);
if (grctx->patch_ltc)
@@ -1521,7 +1531,7 @@ gf100_grctx_generate(struct gf100_gr *gr, struct gf100_gr_chan *chan, struct nvk
);
}
grctx->main(gr, &info);
grctx->main(chan, &info);
/* Trigger a context unload by unsetting the "next channel valid" bit
* and faking a context switch interrupt.

15
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.h
View File

@@ -14,6 +14,7 @@ struct gf100_grctx {
int gf100_grctx_mmio_data(struct gf100_grctx *, u32 size, u32 align, bool priv);
void gf100_grctx_mmio_item(struct gf100_grctx *, u32 addr, u32 data, int s, int);
void gf100_grctx_patch_wr32(struct gf100_gr_chan *, u32 addr, u32 data);
#define mmio_vram(a,b,c,d) gf100_grctx_mmio_data((a), (b), (c), (d))
#define mmio_refn(a,b,c,d,e) gf100_grctx_mmio_item((a), (b), (c), (d), (e))
@@ -23,7 +24,7 @@ void gf100_grctx_mmio_item(struct gf100_grctx *, u32 addr, u32 data, int s, int)
struct gf100_grctx_func {
void (*unkn88c)(struct gf100_gr *, bool on);
/* main context generation function */
void (*main)(struct gf100_gr *, struct gf100_grctx *);
void (*main)(struct gf100_gr_chan *, struct gf100_grctx *);
/* context-specific modify-on-first-load list generation function */
void (*unkn)(struct gf100_gr *);
/* mmio context data */
@@ -43,7 +44,7 @@ struct gf100_grctx_func {
u32 bundle_min_gpm_fifo_depth;
u32 bundle_token_limit;
/* pagepool */
void (*pagepool)(struct gf100_grctx *);
void (*pagepool)(struct gf100_gr_chan *, u64 addr);
u32 pagepool_size;
/* attribute(/alpha) circular buffer */
void (*attrib)(struct gf100_grctx *);
@@ -82,9 +83,9 @@ struct gf100_grctx_func {
extern const struct gf100_grctx_func gf100_grctx;
int gf100_grctx_generate(struct gf100_gr *, struct gf100_gr_chan *, struct nvkm_gpuobj *inst);
void gf100_grctx_generate_main(struct gf100_gr *, struct gf100_grctx *);
void gf100_grctx_generate_main(struct gf100_gr_chan *, struct gf100_grctx *);
void gf100_grctx_generate_bundle(struct gf100_grctx *);
void gf100_grctx_generate_pagepool(struct gf100_grctx *);
void gf100_grctx_generate_pagepool(struct gf100_gr_chan *, u64);
void gf100_grctx_generate_attrib(struct gf100_grctx *);
void gf100_grctx_generate_unkn(struct gf100_gr *);
void gf100_grctx_generate_floorsweep(struct gf100_gr *);
@@ -116,7 +117,7 @@ void gk104_grctx_generate_gpc_tpc_nr(struct gf100_gr *);
extern const struct gf100_grctx_func gk20a_grctx;
void gk104_grctx_generate_bundle(struct gf100_grctx *);
void gk104_grctx_generate_pagepool(struct gf100_grctx *);
void gk104_grctx_generate_pagepool(struct gf100_gr_chan *, u64);
void gk104_grctx_generate_patch_ltc(struct gf100_grctx *);
void gk104_grctx_generate_unkn(struct gf100_gr *);
void gk104_grctx_generate_r418800(struct gf100_gr *);
@@ -129,7 +130,7 @@ extern const struct gf100_grctx_func gk208_grctx;
extern const struct gf100_grctx_func gm107_grctx;
void gm107_grctx_generate_bundle(struct gf100_grctx *);
void gm107_grctx_generate_pagepool(struct gf100_grctx *);
void gm107_grctx_generate_pagepool(struct gf100_gr_chan *, u64);
void gm107_grctx_generate_attrib(struct gf100_grctx *);
void gm107_grctx_generate_sm_id(struct gf100_gr *, int, int, int);
@@ -143,7 +144,7 @@ void gm200_grctx_generate_r419a3c(struct gf100_gr *);
extern const struct gf100_grctx_func gm20b_grctx;
extern const struct gf100_grctx_func gp100_grctx;
void gp100_grctx_generate_pagepool(struct gf100_grctx *);
void gp100_grctx_generate_pagepool(struct gf100_gr_chan *, u64);
void gp100_grctx_generate_smid_config(struct gf100_gr *);
extern const struct gf100_grctx_func gp102_grctx;

12
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c
View File

@@ -888,16 +888,10 @@ gk104_grctx_generate_bundle(struct gf100_grctx *info)
}
void
gk104_grctx_generate_pagepool(struct gf100_grctx *info)
gk104_grctx_generate_pagepool(struct gf100_gr_chan *chan, u64 addr)
{
const struct gf100_grctx_func *grctx = info->gr->func->grctx;
const int s = 8;
const int b = mmio_vram(info, grctx->pagepool_size, (1 << s), true);
mmio_refn(info, 0x40800c, 0x00000000, s, b);
mmio_wr32(info, 0x408010, 0x80000000);
mmio_refn(info, 0x419004, 0x00000000, s, b);
mmio_wr32(info, 0x419008, 0x00000000);
mmio_wr32(info, 0x4064cc, 0x80000000);
gf100_grctx_generate_pagepool(chan, addr);
gf100_grctx_patch_wr32(chan, 0x4064cc, 0x80000000);
}
void

5
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk20a.c
View File

@@ -25,8 +25,9 @@
#include <subdev/mc.h>
static void
gk20a_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info)
gk20a_grctx_generate_main(struct gf100_gr_chan *chan, struct gf100_grctx *info)
{
struct gf100_gr *gr = chan->gr;
struct nvkm_device *device = gr->base.engine.subdev.device;
const struct gf100_grctx_func *grctx = gr->func->grctx;
u32 idle_timeout;
@@ -60,7 +61,7 @@ gk20a_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info)
gf100_gr_wait_idle(gr);
gf100_gr_icmd(gr, gr->bundle);
grctx->pagepool(info);
grctx->pagepool(chan, chan->pagepool->addr);
grctx->bundle(info);
}

13
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c
View File

@@ -892,17 +892,10 @@ gm107_grctx_generate_bundle(struct gf100_grctx *info)
}
void
gm107_grctx_generate_pagepool(struct gf100_grctx *info)
gm107_grctx_generate_pagepool(struct gf100_gr_chan *chan, u64 addr)
{
const struct gf100_grctx_func *grctx = info->gr->func->grctx;
const int s = 8;
const int b = mmio_vram(info, grctx->pagepool_size, (1 << s), true);
mmio_refn(info, 0x40800c, 0x00000000, s, b);
mmio_wr32(info, 0x408010, 0x80000000);
mmio_refn(info, 0x419004, 0x00000000, s, b);
mmio_wr32(info, 0x419008, 0x00000000);
mmio_wr32(info, 0x4064cc, 0x80000000);
mmio_wr32(info, 0x418e30, 0x80000000); /* guess at it being related */
gk104_grctx_generate_pagepool(chan, addr);
gf100_grctx_patch_wr32(chan, 0x418e30, 0x80000000);
}
void

5
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm20b.c
View File

@@ -22,8 +22,9 @@
#include "ctxgf100.h"
static void
gm20b_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info)
gm20b_grctx_generate_main(struct gf100_gr_chan *chan, struct gf100_grctx *info)
{
struct gf100_gr *gr = chan->gr;
struct nvkm_device *device = gr->base.engine.subdev.device;
const struct gf100_grctx_func *grctx = gr->func->grctx;
u32 idle_timeout;
@@ -63,7 +64,7 @@ gm20b_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info)
gf100_gr_wait_idle(gr);
gf100_gr_icmd(gr, gr->bundle);
grctx->pagepool(info);
grctx->pagepool(chan, chan->pagepool->addr);
grctx->bundle(info);
}

13
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgp100.c
View File

@@ -30,15 +30,12 @@
******************************************************************************/
void
gp100_grctx_generate_pagepool(struct gf100_grctx *info)
gp100_grctx_generate_pagepool(struct gf100_gr_chan *chan, u64 addr)
{
const struct gf100_grctx_func *grctx = info->gr->func->grctx;
const int s = 8;
const int b = mmio_vram(info, grctx->pagepool_size, (1 << s), true);
mmio_refn(info, 0x40800c, 0x00000000, s, b);
mmio_wr32(info, 0x408010, 0x8007d800);
mmio_refn(info, 0x419004, 0x00000000, s, b);
mmio_wr32(info, 0x419008, 0x00000000);
gf100_grctx_patch_wr32(chan, 0x40800c, addr >> 8);
gf100_grctx_patch_wr32(chan, 0x408010, 0x8007d800);
gf100_grctx_patch_wr32(chan, 0x419004, addr >> 8);
gf100_grctx_patch_wr32(chan, 0x419008, 0x00000000);
}
static void

22
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c
View File

@@ -364,6 +364,8 @@ gf100_gr_chan_dtor(struct nvkm_object *object)
nvkm_vmm_put(chan->vmm, &chan->mmio_vma);
nvkm_memory_unref(&chan->mmio);
nvkm_vmm_put(chan->vmm, &chan->pagepool);
nvkm_vmm_unref(&chan->vmm);
return chan;
}
@@ -394,6 +396,15 @@ gf100_gr_chan_new(struct nvkm_gr *base, struct nvkm_fifo_chan *fifoch,
chan->vmm = nvkm_vmm_ref(fifoch->vmm);
*pobject = &chan->object;
/* Map pagepool. */
ret = nvkm_vmm_get(chan->vmm, 12, nvkm_memory_size(gr->pagepool), &chan->pagepool);
if (ret)
return ret;
ret = nvkm_memory_map(gr->pagepool, 0, chan->vmm, chan->pagepool, &args, sizeof(args));
if (ret)
return ret;
/* Generate golden context image. */
mutex_lock(&gr->fecs.mutex);
if (gr->data == NULL) {
@@ -449,6 +460,7 @@ gf100_gr_chan_new(struct nvkm_gr *base, struct nvkm_fifo_chan *fifoch,
/* finally, fill in the mmio list and point the context at it */
nvkm_kmap(chan->mmio);
gr->func->grctx->pagepool(chan, chan->pagepool->addr);
for (i = 0; mmio->addr && i < ARRAY_SIZE(gr->mmio_list); i++) {
u32 addr = mmio->addr;
u32 data = mmio->data;
@@ -1938,7 +1950,7 @@ gf100_gr_oneinit(struct nvkm_gr *base)
struct gf100_gr *gr = gf100_gr(base);
struct nvkm_subdev *subdev = &gr->base.engine.subdev;
struct nvkm_device *device = subdev->device;
int i, j;
int ret, i, j;
nvkm_pmu_pgob(device->pmu, false);
@@ -1964,6 +1976,12 @@ gf100_gr_oneinit(struct nvkm_gr *base)
}
}
/* Allocate global context buffers. */
ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, gr->func->grctx->pagepool_size,
0x100, false, &gr->pagepool);
if (ret)
return ret;
memset(gr->tile, 0xff, sizeof(gr->tile));
gr->func->oneinit_tiles(gr);
gr->func->oneinit_sm_id(gr);
@@ -2033,6 +2051,8 @@ gf100_gr_dtor(struct nvkm_gr *base)
kfree(gr->data);
nvkm_memory_unref(&gr->pagepool);
nvkm_falcon_dtor(&gr->gpccs.falcon);
nvkm_falcon_dtor(&gr->fecs.falcon);

4
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h
View File

@@ -121,6 +121,8 @@ struct gf100_gr {
u8 ppc_tpc_min;
u8 ppc_tpc_max;
struct nvkm_memory *pagepool;
u8 screen_tile_row_offset;
u8 tile[TPC_MAX];
@@ -258,6 +260,8 @@ struct gf100_gr_chan {
struct gf100_gr *gr;
struct nvkm_vmm *vmm;
struct nvkm_vma *pagepool;
struct nvkm_memory *mmio;
struct nvkm_vma *mmio_vma;
int mmio_nr;