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arm64: dts: qcom: msm8953: add MDSS

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Add the MDSS, MDP and DSI nodes that are found on msm8953 SoC.

Signed-off-by: Vladimir Lypak <vladimir.lypak@gmail.com>
Signed-off-by: Luca Weiss <luca@z3ntu.xyz>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221016161554.673006-4-luca@z3ntu.xyz
This commit is contained in:
Vladimir Lypak
2022-10-16 18:15:53 +02:00
committed by Bjorn Andersson
parent c0b9575a36
commit cf6c35d1bc
1 changed files with 208 additions and 0 deletions
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208
arch/arm64/boot/dts/qcom/msm8953.dtsi
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@@ -726,6 +726,214 @@ tcsr_phy_clk_scheme_sel: syscon@193f044 {
reg = <0x193f044 0x4>;
};
mdss: mdss@1a00000 {
compatible = "qcom,mdss";
reg = <0x1a00000 0x1000>,
<0x1ab0000 0x1040>;
reg-names = "mdss_phys",
"vbif_phys";
power-domains = <&gcc MDSS_GDSC>;
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <1>;
clocks = <&gcc GCC_MDSS_AHB_CLK>,
<&gcc GCC_MDSS_AXI_CLK>,
<&gcc GCC_MDSS_VSYNC_CLK>,
<&gcc GCC_MDSS_MDP_CLK>;
clock-names = "iface",
"bus",
"vsync",
"core";
#address-cells = <1>;
#size-cells = <1>;
ranges;
status = "disabled";
mdp: mdp@1a01000 {
compatible = "qcom,msm8953-mdp5", "qcom,mdp5";
reg = <0x1a01000 0x89000>;
reg-names = "mdp_phys";
interrupt-parent = <&mdss>;
interrupts = <0>;
power-domains = <&gcc MDSS_GDSC>;
clocks = <&gcc GCC_MDSS_AHB_CLK>,
<&gcc GCC_MDSS_AXI_CLK>,
<&gcc GCC_MDSS_MDP_CLK>,
<&gcc GCC_MDSS_VSYNC_CLK>;
clock-names = "iface",
"bus",
"core",
"vsync";
iommus = <&apps_iommu 0x15>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
mdp5_intf1_out: endpoint {
remote-endpoint = <&dsi0_in>;
};
};
port@1 {
reg = <1>;
mdp5_intf2_out: endpoint {
remote-endpoint = <&dsi1_in>;
};
};
};
};
dsi0: dsi@1a94000 {
compatible = "qcom,mdss-dsi-ctrl";
reg = <0x1a94000 0x400>;
reg-names = "dsi_ctrl";
interrupt-parent = <&mdss>;
interrupts = <4>;
assigned-clocks = <&gcc BYTE0_CLK_SRC>,
<&gcc PCLK0_CLK_SRC>;
assigned-clock-parents = <&dsi0_phy 0>,
<&dsi0_phy 1>;
clocks = <&gcc GCC_MDSS_MDP_CLK>,
<&gcc GCC_MDSS_AHB_CLK>,
<&gcc GCC_MDSS_AXI_CLK>,
<&gcc GCC_MDSS_BYTE0_CLK>,
<&gcc GCC_MDSS_PCLK0_CLK>,
<&gcc GCC_MDSS_ESC0_CLK>;
clock-names = "mdp_core",
"iface",
"bus",
"byte",
"pixel",
"core";
phys = <&dsi0_phy>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dsi0_in: endpoint {
remote-endpoint = <&mdp5_intf1_out>;
};
};
port@1 {
reg = <1>;
dsi0_out: endpoint {
};
};
};
};
dsi0_phy: phy@1a94400 {
compatible = "qcom,dsi-phy-14nm-8953";
reg = <0x1a94400 0x100>,
<0x1a94500 0x300>,
<0x1a94800 0x188>;
reg-names = "dsi_phy",
"dsi_phy_lane",
"dsi_pll";
#clock-cells = <1>;
#phy-cells = <0>;
clocks = <&gcc GCC_MDSS_AHB_CLK>, <&xo_board>;
clock-names = "iface", "ref";
status = "disabled";
};
dsi1: dsi@1a96000 {
compatible = "qcom,mdss-dsi-ctrl";
reg = <0x1a96000 0x400>;
reg-names = "dsi_ctrl";
interrupt-parent = <&mdss>;
interrupts = <5>;
assigned-clocks = <&gcc BYTE1_CLK_SRC>,
<&gcc PCLK1_CLK_SRC>;
assigned-clock-parents = <&dsi1_phy 0>,
<&dsi1_phy 1>;
clocks = <&gcc GCC_MDSS_MDP_CLK>,
<&gcc GCC_MDSS_AHB_CLK>,
<&gcc GCC_MDSS_AXI_CLK>,
<&gcc GCC_MDSS_BYTE1_CLK>,
<&gcc GCC_MDSS_PCLK1_CLK>,
<&gcc GCC_MDSS_ESC1_CLK>;
clock-names = "mdp_core",
"iface",
"bus",
"byte",
"pixel",
"core";
phys = <&dsi1_phy>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dsi1_in: endpoint {
remote-endpoint = <&mdp5_intf2_out>;
};
};
port@1 {
reg = <1>;
dsi1_out: endpoint {
};
};
};
};
dsi1_phy: phy@1a96400 {
compatible = "qcom,dsi-phy-14nm-8953";
reg = <0x1a96400 0x100>,
<0x1a96500 0x300>,
<0x1a96800 0x188>;
reg-names = "dsi_phy",
"dsi_phy_lane",
"dsi_pll";
#clock-cells = <1>;
#phy-cells = <0>;
clocks = <&gcc GCC_MDSS_AHB_CLK>, <&xo_board>;
clock-names = "iface", "ref";
status = "disabled";
};
};
apps_iommu: iommu@1e00000 {
compatible = "qcom,msm8953-iommu", "qcom,msm-iommu-v1";
ranges = <0 0x1e20000 0x20000>;