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drm/amd/powerplay: enable APCC DFLL for sienna_cichlid

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Enable APCC DFLL for sienna_cichlid.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Likun Gao
2020-03-24 15:15:10 +08:00
committed by Alex Deucher
parent 3fc006f551
commit cf06331fed
1 changed files with 2 additions and 0 deletions
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2
drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
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@@ -162,6 +162,7 @@ static struct smu_11_0_cmn2aisc_mapping sienna_cichlid_feature_mask_map[SMU_FEAT
FEA_MAP(TEMP_DEPENDENT_VMIN),
FEA_MAP(MMHUB_PG),
FEA_MAP(ATHUB_PG),
FEA_MAP(APCC_DFLL),
};
static struct smu_11_0_cmn2aisc_mapping sienna_cichlid_table_map[SMU_TABLE_COUNT] = {
@@ -306,6 +307,7 @@ sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu,
| FEATURE_MASK(FEATURE_PPT_BIT)
| FEATURE_MASK(FEATURE_TDC_BIT)
| FEATURE_MASK(FEATURE_BACO_BIT)
| FEATURE_MASK(FEATURE_APCC_DFLL_BIT)
| FEATURE_MASK(FEATURE_FAN_CONTROL_BIT)
| FEATURE_MASK(FEATURE_THERMAL_BIT);