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clk: qcom: clk-rcg2: document calc_rate function

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Update calc_rate docs to reflect, that pre_div
is not pure divisor, but a register value, and requires conversion.

Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com>
Link: https://lore.kernel.org/r/20241118-starqltechn_integration_upstream-v8-1-ac8e36a3aa65@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Dzmitry Sankouski
2024-11-18 13:15:19 +03:00
committed by Bjorn Andersson
parent d26c4ad3fa
commit cef0523dd2
1 changed files with 12 additions and 3 deletions
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15
drivers/clk/qcom/clk-rcg2.c
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@@ -148,12 +148,21 @@ static int clk_rcg2_set_parent(struct clk_hw *hw, u8 index)
return update_config(rcg);
}
/*
* Calculate m/n:d rate
/**
* calc_rate() - Calculate rate based on m/n:d values
*
* @rate: Parent rate.
* @m: Multiplier.
* @n: Divisor.
* @mode: Use zero to ignore m/n calculation.
* @hid_div: Pre divisor register value. Pre divisor value
* relates to hid_div as pre_div = (hid_div + 1) / 2.
*
* Return calculated rate according to formula:
*
* parent_rate m
* rate = ----------- x ---
* hid_div n
* pre_div n
*/
static unsigned long
calc_rate(unsigned long rate, u32 m, u32 n, u32 mode, u32 hid_div)