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thermal/drivers/qcom: Fix missing spmi adc tm5 gen3 file
Add missing file resulting from a manual application of the change
below after fixing a conflict in the Makefile.
Fixes: 948ee3a74f ("thermal/drivers/qcom: add support for PMIC5 Gen3 ADC thermal monitoring")
Signed-off-by: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://patch.msgid.link/20260811145427.3089426-1-daniel.lezcano@kernel.org
This commit is contained in:
Jishnu Prakash
committed by
Daniel Lezcano
Daniel Lezcano
parent
ccda015d76
commit
cebe359188
@@ -0,0 +1,434 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
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*/
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#include <linux/auxiliary_bus.h>
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#include <linux/bitfield.h>
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#include <linux/bits.h>
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#include <linux/cleanup.h>
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#include <linux/container_of.h>
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#include <linux/device/devres.h>
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#include <linux/dev_printk.h>
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#include <linux/err.h>
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#include <linux/iio/adc/qcom-adc5-gen3-common.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/thermal.h>
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#include <linux/types.h>
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#include <linux/unaligned.h>
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#include "../thermal_hwmon.h"
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#define ADC_TM5_GEN3_CONFIG_REGS 12
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struct device;
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struct adc_tm5_gen3_chip;
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/**
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* struct adc_tm5_gen3_channel_props - ADC_TM channel structure
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* @common_props: structure with common ADC channel properties.
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* @chip: ADC TM device.
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* @tzd: pointer to thermal device corresponding to TM channel.
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* @sdam_index: SDAM on which this TM channel lies.
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* @timer: time period of recurring TM measurement.
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* @tm_chan_index: TM channel number used.
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* @high_thr_en: TM high threshold crossing detection enabled.
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* @low_thr_en: TM low threshold crossing detection enabled.
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*/
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struct adc_tm5_gen3_channel_props {
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struct adc5_channel_common_prop common_props;
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struct adc_tm5_gen3_chip *chip;
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struct thermal_zone_device *tzd;
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unsigned int sdam_index;
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unsigned int timer;
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unsigned int tm_chan_index;
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bool high_thr_en;
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bool low_thr_en;
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};
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/**
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* struct adc_tm5_gen3_chip - ADC Thermal Monitoring device structure
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* @dev_data: Top-level ADC device data.
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* @chan_props: Array of ADC_TM channel structures.
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* @dev: SPMI ADC5 Gen3 device.
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* @nchannels: number of TM channels allocated
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*/
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struct adc_tm5_gen3_chip {
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struct adc5_device_data *dev_data;
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struct adc_tm5_gen3_channel_props *chan_props;
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struct device *dev;
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unsigned int nchannels;
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};
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DEFINE_GUARD(adc5_gen3, struct adc_tm5_gen3_chip *,
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adc5_gen3_mutex_lock(_T->dev), adc5_gen3_mutex_unlock(_T->dev))
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static int get_sdam_from_irq(struct adc_tm5_gen3_chip *adc_tm5, int irq)
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{
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for (int i = 0; i < adc_tm5->dev_data->num_sdams; i++) {
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if (adc_tm5->dev_data->base[i].irq == irq)
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return i;
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}
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return -ENOENT;
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}
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static irqreturn_t adctm5_gen3_isr(int irq, void *dev_id)
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{
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struct adc_tm5_gen3_chip *adc_tm5 = dev_id;
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int ret, sdam_num;
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u8 tm_status[2];
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u8 status, val;
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sdam_num = get_sdam_from_irq(adc_tm5, irq);
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if (sdam_num < 0)
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return IRQ_NONE;
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ret = adc5_gen3_read(adc_tm5->dev_data, sdam_num, ADC5_GEN3_STATUS1,
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&status, sizeof(status));
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if (ret)
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return IRQ_NONE;
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if (status & ADC5_GEN3_STATUS1_CONV_FAULT) {
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val = ADC5_GEN3_CONV_ERR_CLR_REQ;
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adc5_gen3_status_clear(adc_tm5->dev_data, sdam_num,
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ADC5_GEN3_CONV_ERR_CLR, &val, 1);
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return IRQ_HANDLED;
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}
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ret = adc5_gen3_read(adc_tm5->dev_data, sdam_num, ADC5_GEN3_TM_HIGH_STS,
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tm_status, sizeof(tm_status));
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if (ret)
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return IRQ_NONE;
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if (tm_status[0] || tm_status[1])
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return IRQ_WAKE_THREAD;
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return IRQ_NONE;
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}
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static irqreturn_t adctm5_gen3_isr_thread(int irq, void *dev_id)
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{
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struct adc_tm5_gen3_chip *adc_tm5 = dev_id;
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u8 tm_status[2];
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int sdam_index;
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sdam_index = get_sdam_from_irq(adc_tm5, irq);
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if (sdam_index < 0)
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return IRQ_NONE;
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scoped_guard(adc5_gen3, adc_tm5) {
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int ret;
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ret = adc5_gen3_read(adc_tm5->dev_data, sdam_index, ADC5_GEN3_TM_HIGH_STS,
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tm_status, sizeof(tm_status));
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if (ret)
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return IRQ_NONE;
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ret = adc5_gen3_status_clear(adc_tm5->dev_data, sdam_index,
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ADC5_GEN3_TM_HIGH_STS_CLR, tm_status,
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sizeof(tm_status));
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if (ret)
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return IRQ_NONE;
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}
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for (int i = 0; i < adc_tm5->nchannels; i++) {
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struct adc_tm5_gen3_channel_props *chan_prop = &adc_tm5->chan_props[i];
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int offset = chan_prop->tm_chan_index;
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bool upper_set, lower_set;
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if (chan_prop->sdam_index != sdam_index)
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continue;
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upper_set = ((tm_status[0] & BIT(offset)) && chan_prop->high_thr_en);
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lower_set = ((tm_status[1] & BIT(offset)) && chan_prop->low_thr_en);
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if (!(upper_set || lower_set))
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continue;
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thermal_zone_device_update(chan_prop->tzd, THERMAL_TRIP_VIOLATED);
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}
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return IRQ_HANDLED;
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}
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static int adc_tm5_gen3_get_temp(struct thermal_zone_device *tz, int *temp)
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{
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struct adc_tm5_gen3_channel_props *prop = thermal_zone_device_priv(tz);
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struct adc_tm5_gen3_chip *adc_tm5;
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if (!prop || !prop->chip)
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return -EINVAL;
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adc_tm5 = prop->chip;
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return adc5_gen3_get_scaled_reading(adc_tm5->dev, &prop->common_props, temp);
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}
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static int adc_tm5_gen3_disable_channel(struct adc_tm5_gen3_channel_props *prop)
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{
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struct adc_tm5_gen3_chip *adc_tm5 = prop->chip;
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int ret;
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u8 val;
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prop->high_thr_en = false;
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prop->low_thr_en = false;
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ret = adc5_gen3_poll_wait_hs(adc_tm5->dev_data, prop->sdam_index);
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if (ret)
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return ret;
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val = BIT(prop->tm_chan_index);
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ret = adc5_gen3_write(adc_tm5->dev_data, prop->sdam_index,
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ADC5_GEN3_TM_HIGH_STS_CLR, &val, sizeof(val));
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if (ret)
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return ret;
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ret = adc5_gen3_write(adc_tm5->dev_data, prop->sdam_index,
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ADC5_GEN3_TM_LOW_STS_CLR, &val, sizeof(val));
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if (ret)
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return ret;
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val = MEAS_INT_DISABLE;
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ret = adc5_gen3_write(adc_tm5->dev_data, prop->sdam_index,
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ADC5_GEN3_TIMER_SEL, &val, sizeof(val));
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if (ret)
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return ret;
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/* To indicate there is an actual conversion request */
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val = ADC5_GEN3_CHAN_CONV_REQ | prop->tm_chan_index;
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ret = adc5_gen3_write(adc_tm5->dev_data, prop->sdam_index,
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ADC5_GEN3_PERPH_CH, &val, sizeof(val));
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if (ret)
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return ret;
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val = ADC5_GEN3_CONV_REQ_REQ;
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return adc5_gen3_write(adc_tm5->dev_data, prop->sdam_index,
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ADC5_GEN3_CONV_REQ, &val, sizeof(val));
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}
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static int adc_tm5_gen3_configure(struct adc_tm5_gen3_channel_props *prop,
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int low_temp, int high_temp)
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{
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struct adc_tm5_gen3_chip *adc_tm5 = prop->chip;
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u8 buf[ADC_TM5_GEN3_CONFIG_REGS];
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u8 conv_req;
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u16 adc_code;
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int ret;
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ret = adc5_gen3_poll_wait_hs(adc_tm5->dev_data, prop->sdam_index);
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if (ret < 0)
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return ret;
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ret = adc5_gen3_read(adc_tm5->dev_data, prop->sdam_index,
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ADC5_GEN3_SID, buf, sizeof(buf));
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if (ret < 0)
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return ret;
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/* Write SID */
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buf[0] = FIELD_PREP(ADC5_GEN3_SID_MASK, prop->common_props.sid);
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/* Select TM channel and indicate there is an actual conversion request */
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buf[1] = ADC5_GEN3_CHAN_CONV_REQ | prop->tm_chan_index;
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buf[2] = prop->timer;
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/* Digital param selection */
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adc5_gen3_update_dig_param(&prop->common_props, &buf[3]);
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/* Update fast average sample value */
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buf[4] = FIELD_PREP(ADC5_GEN3_FAST_AVG_CTL_SAMPLES_MASK,
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prop->common_props.avg_samples) | ADC5_GEN3_FAST_AVG_CTL_EN;
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/* Select ADC channel */
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buf[5] = prop->common_props.channel;
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/* Select HW settle delay for channel */
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buf[6] = FIELD_PREP(ADC5_GEN3_HW_SETTLE_DELAY_MASK,
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prop->common_props.hw_settle_time_us);
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buf[7] = 0;
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/* High temperature corresponds to low voltage threshold */
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prop->low_thr_en = (high_temp != INT_MAX);
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if (prop->low_thr_en) {
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adc_code = qcom_adc_tm5_gen2_temp_res_scale(high_temp);
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put_unaligned_le16(adc_code, &buf[8]);
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buf[7] |= ADC5_GEN3_LOW_THR_INT_EN;
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}
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/* Low temperature corresponds to high voltage threshold */
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prop->high_thr_en = (low_temp != -INT_MAX);
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if (prop->high_thr_en) {
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adc_code = qcom_adc_tm5_gen2_temp_res_scale(low_temp);
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put_unaligned_le16(adc_code, &buf[10]);
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buf[7] |= ADC5_GEN3_HIGH_THR_INT_EN;
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}
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ret = adc5_gen3_write(adc_tm5->dev_data, prop->sdam_index, ADC5_GEN3_SID,
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buf, sizeof(buf));
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if (ret < 0)
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return ret;
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conv_req = ADC5_GEN3_CONV_REQ_REQ;
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return adc5_gen3_write(adc_tm5->dev_data, prop->sdam_index,
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ADC5_GEN3_CONV_REQ, &conv_req, sizeof(conv_req));
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}
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static int adc_tm5_gen3_set_trip_temp(struct thermal_zone_device *tz,
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int low_temp, int high_temp)
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{
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struct adc_tm5_gen3_channel_props *prop = thermal_zone_device_priv(tz);
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struct adc_tm5_gen3_chip *adc_tm5;
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if (!prop || !prop->chip)
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return -EINVAL;
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adc_tm5 = prop->chip;
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dev_dbg(adc_tm5->dev, "channel:%s, low_temp(mdegC):%d, high_temp(mdegC):%d\n",
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prop->common_props.label, low_temp, high_temp);
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guard(adc5_gen3)(adc_tm5);
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return adc_tm5_gen3_configure(prop, low_temp, high_temp);
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}
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static const struct thermal_zone_device_ops adc_tm_ops = {
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.get_temp = adc_tm5_gen3_get_temp,
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.set_trips = adc_tm5_gen3_set_trip_temp,
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};
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static int adc_tm5_register_tzd(struct adc_tm5_gen3_chip *adc_tm5)
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{
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struct thermal_zone_device *tzd;
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unsigned int channel;
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int ret;
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for (int i = 0; i < adc_tm5->nchannels; i++) {
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channel = ADC5_GEN3_V_CHAN(adc_tm5->chan_props[i].common_props);
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tzd = devm_thermal_of_zone_register(adc_tm5->dev, channel,
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&adc_tm5->chan_props[i],
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&adc_tm_ops);
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if (IS_ERR(tzd)) {
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if (PTR_ERR(tzd) == -ENODEV) {
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dev_dbg(adc_tm5->dev,
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"thermal sensor on channel %d is not used\n",
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channel);
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continue;
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}
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return PTR_ERR(tzd);
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}
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adc_tm5->chan_props[i].tzd = tzd;
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ret = devm_thermal_add_hwmon_sysfs(adc_tm5->dev, tzd);
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if (ret)
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return ret;
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}
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return 0;
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}
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static void adc5_gen3_disable(void *data)
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{
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struct adc_tm5_gen3_chip *adc_tm5 = data;
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guard(adc5_gen3)(adc_tm5);
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/* Disable all available TM channels */
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for (int i = 0; i < adc_tm5->nchannels; i++)
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adc_tm5_gen3_disable_channel(&adc_tm5->chan_props[i]);
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}
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static int adc_tm5_probe(struct auxiliary_device *aux_dev,
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const struct auxiliary_device_id *id)
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{
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struct adc_tm5_gen3_chip *adc_tm5;
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struct tm5_aux_dev_wrapper *aux_dev_wrapper;
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struct device *dev = &aux_dev->dev;
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int ret;
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adc_tm5 = devm_kzalloc(dev, sizeof(*adc_tm5), GFP_KERNEL);
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if (!adc_tm5)
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return -ENOMEM;
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aux_dev_wrapper = container_of(aux_dev, struct tm5_aux_dev_wrapper, aux_dev);
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adc_tm5->dev = dev;
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adc_tm5->dev_data = aux_dev_wrapper->dev_data;
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adc_tm5->nchannels = aux_dev_wrapper->n_tm_channels;
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adc_tm5->chan_props = devm_kcalloc(dev, aux_dev_wrapper->n_tm_channels,
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sizeof(*adc_tm5->chan_props), GFP_KERNEL);
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if (!adc_tm5->chan_props)
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return -ENOMEM;
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for (int i = 0; i < adc_tm5->nchannels; i++) {
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/*
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* Since the first channel of the first SDAM is reserved for
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* immediate ADC conversions, TM channel count must start from
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* the channel just after it. The variable tm_count is used to
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* calculate SDAM and TM channel index on that SDAM correctly
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* for each TM channel.
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*/
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int tm_count = i + 1;
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adc_tm5->chan_props[i].common_props = aux_dev_wrapper->tm_props[i];
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adc_tm5->chan_props[i].timer = MEAS_INT_1S;
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adc_tm5->chan_props[i].sdam_index = tm_count / 8;
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adc_tm5->chan_props[i].tm_chan_index = tm_count % 8;
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adc_tm5->chan_props[i].chip = adc_tm5;
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}
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/*
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* ADC_TM channels are enabled in the loop in adc_tm5_register_tzd() as
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* part of the set_trips calls during thermal zone registration. This
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* action is to disable them all in case of probe failure.
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*/
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ret = devm_add_action(dev, adc5_gen3_disable, adc_tm5);
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if (ret)
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return ret;
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ret = adc_tm5_register_tzd(adc_tm5);
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if (ret)
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return ret;
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for (int i = 0; i < adc_tm5->dev_data->num_sdams; i++) {
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u32 irq_flags = IRQF_ONESHOT;
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/*
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* First SDAM's interrupt is shared between main ADC driver and
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* auxiliary TM driver, so its flags must include IRQF_SHARED.
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* This is not needed for other SDAMs as they will be used only
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* for TM functionality.
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*/
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if (i == 0)
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irq_flags |= IRQF_SHARED;
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ret = devm_request_threaded_irq(dev,
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adc_tm5->dev_data->base[i].irq,
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adctm5_gen3_isr,
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adctm5_gen3_isr_thread,
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irq_flags,
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adc_tm5->dev_data->base[i].irq_name,
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adc_tm5);
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if (ret < 0)
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return ret;
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||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct auxiliary_device_id adctm5_auxiliary_id_table[] = {
|
||||
{ .name = "qcom_spmi_adc5_gen3.adc5_tm_gen3" },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(auxiliary, adctm5_auxiliary_id_table);
|
||||
|
||||
static struct auxiliary_driver adctm5gen3_auxiliary_driver = {
|
||||
.id_table = adctm5_auxiliary_id_table,
|
||||
.probe = adc_tm5_probe,
|
||||
};
|
||||
module_auxiliary_driver(adctm5gen3_auxiliary_driver);
|
||||
|
||||
MODULE_DESCRIPTION("SPMI PMIC Thermal Monitor ADC driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
MODULE_IMPORT_NS("QCOM_SPMI_ADC5_GEN3");
|
||||
Reference in New Issue
Block a user