mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2026-04-08 12:55:43 -04:00
Merge tag 'samsung-clk-6.10-2' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into clk-samsung
Pull Samsung clk driver updates from Krzysztof Kozlowski: - Allow choice of manual or firmware-driven control over PLLs, needed to fully implement CPU clock controllers on Exynos850 - Correct PLL clock IDs on ExynosAutov9 - Propagate certain clock rates to allow setting proper SPI clock rates on Google GS101 - Add HSI0 and HSI2 clock controllers for Google GS101 - Mark certain Google GS101 clocks critical - Convert old S3C64xx clock controller bindings to DT schema * tag 'samsung-clk-6.10-2' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: clk: samsung: gs101: drop unused HSI2 clock parent data clk: samsung: gs101: mark some apm UASC and XIU clocks critical clk: samsung: gs101: add support for cmu_hsi2 clk: samsung: gs101: add support for cmu_hsi0 dt-bindings: clock: google,gs101-clock: add HSI2 clock management unit dt-bindings: clock: google,gs101-clock: add HSI0 clock management unit clk: samsung: gs101: propagate PERIC1 USI SPI clock rate clk: samsung: gs101: propagate PERIC0 USI SPI clock rate clk: samsung: exynosautov9: fix wrong pll clock id value dt-bindings: clock: samsung,s3c6400-clock: convert to DT Schema clk: samsung: exynos850: Add CMU_CPUCL0 and CMU_CPUCL1 clk: samsung: Implement manual PLL control for ARM64 SoCs
This commit is contained in:
Stephen Boyd
@@ -30,16 +30,18 @@ properties:
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- google,gs101-cmu-top
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- google,gs101-cmu-apm
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- google,gs101-cmu-misc
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- google,gs101-cmu-hsi0
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- google,gs101-cmu-hsi2
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- google,gs101-cmu-peric0
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- google,gs101-cmu-peric1
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clocks:
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minItems: 1
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maxItems: 3
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maxItems: 5
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clock-names:
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minItems: 1
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maxItems: 3
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maxItems: 5
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"#clock-cells":
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const: 1
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@@ -72,6 +74,55 @@ allOf:
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items:
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- const: oscclk
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- if:
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properties:
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compatible:
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contains:
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const: google,gs101-cmu-hsi0
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then:
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properties:
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clocks:
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items:
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- description: External reference clock (24.576 MHz)
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- description: HSI0 bus clock (from CMU_TOP)
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- description: DPGTC (from CMU_TOP)
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- description: USB DRD controller clock (from CMU_TOP)
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- description: USB Display Port debug clock (from CMU_TOP)
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clock-names:
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items:
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- const: oscclk
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- const: bus
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- const: dpgtc
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- const: usb31drd
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- const: usbdpdbg
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- if:
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properties:
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compatible:
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contains:
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enum:
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- google,gs101-cmu-hsi2
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then:
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properties:
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clocks:
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items:
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- description: External reference clock (24.576 MHz)
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- description: High Speed Interface bus clock (from CMU_TOP)
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- description: High Speed Interface pcie clock (from CMU_TOP)
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- description: High Speed Interface ufs clock (from CMU_TOP)
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- description: High Speed Interface mmc clock (from CMU_TOP)
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clock-names:
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items:
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- const: oscclk
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- const: bus
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- const: pcie
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- const: ufs
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- const: mmc
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- if:
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properties:
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compatible:
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@@ -0,0 +1,57 @@
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/samsung,s3c6400-clock.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Samsung S3C6400 SoC clock controller
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maintainers:
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- Krzysztof Kozlowski <krzk@kernel.org>
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description: |
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There are several clocks that are generated outside the SoC. It is expected
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that they are defined using standard clock bindings with following
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clock-output-names and/or provided as clock inputs to this clock controller:
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- "fin_pll" - PLL input clock (xtal/extclk) - required,
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- "xusbxti" - USB xtal - required,
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- "iiscdclk0" - I2S0 codec clock - optional,
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- "iiscdclk1" - I2S1 codec clock - optional,
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- "iiscdclk2" - I2S2 codec clock - optional,
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- "pcmcdclk0" - PCM0 codec clock - optional,
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- "pcmcdclk1" - PCM1 codec clock - optional, only S3C6410.
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All available clocks are defined as preprocessor macros in
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include/dt-bindings/clock/samsung,s3c64xx-clock.h header.
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properties:
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compatible:
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enum:
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- samsung,s3c6400-clock
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- samsung,s3c6410-clock
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reg:
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maxItems: 1
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clocks:
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maxItems: 1
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"#clock-cells":
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const: 1
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required:
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- compatible
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- reg
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- clocks
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- "#clock-cells"
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additionalProperties: false
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examples:
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- |
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clock-controller@7e00f000 {
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compatible = "samsung,s3c6410-clock";
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reg = <0x7e00f000 0x1000>;
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#clock-cells = <1>;
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clocks = <&fin_pll>;
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};
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@@ -1,76 +0,0 @@
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* Samsung S3C64xx Clock Controller
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The S3C64xx clock controller generates and supplies clock to various controllers
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within the SoC. The clock binding described here is applicable to all SoCs in
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the S3C64xx family.
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Required Properties:
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- compatible: should be one of the following.
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- "samsung,s3c6400-clock" - controller compatible with S3C6400 SoC.
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- "samsung,s3c6410-clock" - controller compatible with S3C6410 SoC.
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- reg: physical base address of the controller and length of memory mapped
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region.
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- #clock-cells: should be 1.
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Each clock is assigned an identifier and client nodes can use this identifier
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to specify the clock which they consume. Some of the clocks are available only
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on a particular S3C64xx SoC and this is specified where applicable.
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All available clocks are defined as preprocessor macros in
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dt-bindings/clock/samsung,s3c64xx-clock.h header and can be used in device
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tree sources.
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External clocks:
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There are several clocks that are generated outside the SoC. It is expected
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that they are defined using standard clock bindings with following
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clock-output-names:
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- "fin_pll" - PLL input clock (xtal/extclk) - required,
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- "xusbxti" - USB xtal - required,
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- "iiscdclk0" - I2S0 codec clock - optional,
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- "iiscdclk1" - I2S1 codec clock - optional,
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- "iiscdclk2" - I2S2 codec clock - optional,
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- "pcmcdclk0" - PCM0 codec clock - optional,
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- "pcmcdclk1" - PCM1 codec clock - optional, only S3C6410.
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Example: Clock controller node:
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clock: clock-controller@7e00f000 {
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compatible = "samsung,s3c6410-clock";
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reg = <0x7e00f000 0x1000>;
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#clock-cells = <1>;
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};
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Example: Required external clocks:
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fin_pll: clock-fin-pll {
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compatible = "fixed-clock";
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clock-output-names = "fin_pll";
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clock-frequency = <12000000>;
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#clock-cells = <0>;
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};
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xusbxti: clock-xusbxti {
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compatible = "fixed-clock";
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clock-output-names = "xusbxti";
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clock-frequency = <48000000>;
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#clock-cells = <0>;
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};
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Example: UART controller node that consumes the clock generated by the clock
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controller (refer to the standard clock bindings for information about
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"clocks" and "clock-names" properties):
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uart0: serial@7f005000 {
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compatible = "samsung,s3c6400-uart";
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reg = <0x7f005000 0x100>;
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interrupt-parent = <&vic1>;
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interrupts = <5>;
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clock-names = "uart", "clk_uart_baud2",
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"clk_uart_baud3";
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clocks = <&clock PCLK_UART0>, <&clocks PCLK_UART0>,
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<&clock SCLK_UART>;
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};
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@@ -17,10 +17,17 @@
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#include "clk-exynos-arm64.h"
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/* PLL register bits */
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#define PLL_CON1_MANUAL BIT(1)
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/* Gate register bits */
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#define GATE_MANUAL BIT(20)
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#define GATE_ENABLE_HWACG BIT(28)
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/* PLL_CONx_PLL register offsets range */
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#define PLL_CON_OFF_START 0x100
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#define PLL_CON_OFF_END 0x600
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/* Gate register offsets range */
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#define GATE_OFF_START 0x2000
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#define GATE_OFF_END 0x2fff
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@@ -38,17 +45,36 @@ struct exynos_arm64_cmu_data {
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struct samsung_clk_provider *ctx;
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};
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/* Check if the register offset is a GATE register */
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static bool is_gate_reg(unsigned long off)
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{
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return off >= GATE_OFF_START && off <= GATE_OFF_END;
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}
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/* Check if the register offset is a PLL_CONx register */
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static bool is_pll_conx_reg(unsigned long off)
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{
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return off >= PLL_CON_OFF_START && off <= PLL_CON_OFF_END;
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}
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/* Check if the register offset is a PLL_CON1 register */
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static bool is_pll_con1_reg(unsigned long off)
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{
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return is_pll_conx_reg(off) && (off & 0xf) == 0x4 && !(off & 0x10);
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}
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/**
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* exynos_arm64_init_clocks - Set clocks initial configuration
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* @np: CMU device tree node with "reg" property (CMU addr)
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* @reg_offs: Register offsets array for clocks to init
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* @reg_offs_len: Number of register offsets in reg_offs array
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* @np: CMU device tree node with "reg" property (CMU addr)
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* @cmu: CMU data
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*
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* Set manual control mode for all gate clocks.
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* Set manual control mode for all gate and PLL clocks.
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*/
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static void __init exynos_arm64_init_clocks(struct device_node *np,
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const unsigned long *reg_offs, size_t reg_offs_len)
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const struct samsung_cmu_info *cmu)
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{
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const unsigned long *reg_offs = cmu->clk_regs;
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size_t reg_offs_len = cmu->nr_clk_regs;
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void __iomem *reg_base;
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size_t i;
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@@ -60,14 +86,14 @@ static void __init exynos_arm64_init_clocks(struct device_node *np,
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void __iomem *reg = reg_base + reg_offs[i];
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u32 val;
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/* Modify only gate clock registers */
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if (reg_offs[i] < GATE_OFF_START || reg_offs[i] > GATE_OFF_END)
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continue;
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val = readl(reg);
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val |= GATE_MANUAL;
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val &= ~GATE_ENABLE_HWACG;
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writel(val, reg);
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if (cmu->manual_plls && is_pll_con1_reg(reg_offs[i])) {
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writel(PLL_CON1_MANUAL, reg);
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} else if (is_gate_reg(reg_offs[i])) {
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val = readl(reg);
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val |= GATE_MANUAL;
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val &= ~GATE_ENABLE_HWACG;
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writel(val, reg);
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}
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}
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iounmap(reg_base);
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@@ -177,7 +203,7 @@ void __init exynos_arm64_register_cmu(struct device *dev,
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pr_err("%s: could not enable bus clock %s; err = %d\n",
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__func__, cmu->clk_name, err);
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exynos_arm64_init_clocks(np, cmu->clk_regs, cmu->nr_clk_regs);
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exynos_arm64_init_clocks(np, cmu);
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samsung_cmu_register_one(np, cmu);
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}
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@@ -224,7 +250,7 @@ int __init exynos_arm64_register_cmu_pm(struct platform_device *pdev,
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__func__, cmu->clk_name, ret);
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if (set_manual)
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exynos_arm64_init_clocks(np, cmu->clk_regs, cmu->nr_clk_regs);
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exynos_arm64_init_clocks(np, cmu);
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reg_base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(reg_base))
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@@ -14,13 +14,16 @@
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#include <dt-bindings/clock/exynos850.h>
|
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|
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#include "clk.h"
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#include "clk-cpu.h"
|
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#include "clk-exynos-arm64.h"
|
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|
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/* NOTE: Must be equal to the last clock ID increased by one */
|
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#define CLKS_NR_TOP (CLK_DOUT_G3D_SWITCH + 1)
|
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#define CLKS_NR_TOP (CLK_DOUT_CPUCL1_SWITCH + 1)
|
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#define CLKS_NR_APM (CLK_GOUT_SYSREG_APM_PCLK + 1)
|
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#define CLKS_NR_AUD (CLK_GOUT_AUD_CMU_AUD_PCLK + 1)
|
||||
#define CLKS_NR_CMGP (CLK_GOUT_SYSREG_CMGP_PCLK + 1)
|
||||
#define CLKS_NR_CPUCL0 (CLK_CLUSTER0_SCLK + 1)
|
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#define CLKS_NR_CPUCL1 (CLK_CLUSTER1_SCLK + 1)
|
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#define CLKS_NR_G3D (CLK_GOUT_G3D_SYSREG_PCLK + 1)
|
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#define CLKS_NR_HSI (CLK_GOUT_HSI_CMU_HSI_PCLK + 1)
|
||||
#define CLKS_NR_IS (CLK_GOUT_IS_SYSREG_PCLK + 1)
|
||||
@@ -47,6 +50,10 @@
|
||||
#define CLK_CON_MUX_MUX_CLKCMU_CORE_CCI 0x1018
|
||||
#define CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD 0x101c
|
||||
#define CLK_CON_MUX_MUX_CLKCMU_CORE_SSS 0x1020
|
||||
#define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG 0x1024
|
||||
#define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH 0x1028
|
||||
#define CLK_CON_MUX_MUX_CLKCMU_CPUCL1_DBG 0x102c
|
||||
#define CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH 0x1030
|
||||
#define CLK_CON_MUX_MUX_CLKCMU_DPU 0x1034
|
||||
#define CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH 0x1038
|
||||
#define CLK_CON_MUX_MUX_CLKCMU_HSI_BUS 0x103c
|
||||
@@ -69,6 +76,10 @@
|
||||
#define CLK_CON_DIV_CLKCMU_CORE_CCI 0x1824
|
||||
#define CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD 0x1828
|
||||
#define CLK_CON_DIV_CLKCMU_CORE_SSS 0x182c
|
||||
#define CLK_CON_DIV_CLKCMU_CPUCL0_DBG 0x1830
|
||||
#define CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH 0x1834
|
||||
#define CLK_CON_DIV_CLKCMU_CPUCL1_DBG 0x1838
|
||||
#define CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH 0x183c
|
||||
#define CLK_CON_DIV_CLKCMU_DPU 0x1840
|
||||
#define CLK_CON_DIV_CLKCMU_G3D_SWITCH 0x1844
|
||||
#define CLK_CON_DIV_CLKCMU_HSI_BUS 0x1848
|
||||
@@ -97,6 +108,10 @@
|
||||
#define CLK_CON_GAT_GATE_CLKCMU_CORE_CCI 0x2020
|
||||
#define CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD 0x2024
|
||||
#define CLK_CON_GAT_GATE_CLKCMU_CORE_SSS 0x2028
|
||||
#define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG 0x202c
|
||||
#define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH 0x2030
|
||||
#define CLK_CON_GAT_GATE_CLKCMU_CPUCL1_DBG 0x2034
|
||||
#define CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH 0x2038
|
||||
#define CLK_CON_GAT_GATE_CLKCMU_DPU 0x203c
|
||||
#define CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH 0x2040
|
||||
#define CLK_CON_GAT_GATE_CLKCMU_HSI_BUS 0x2044
|
||||
@@ -130,6 +145,10 @@ static const unsigned long top_clk_regs[] __initconst = {
|
||||
CLK_CON_MUX_MUX_CLKCMU_CORE_CCI,
|
||||
CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD,
|
||||
CLK_CON_MUX_MUX_CLKCMU_CORE_SSS,
|
||||
CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG,
|
||||
CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH,
|
||||
CLK_CON_MUX_MUX_CLKCMU_CPUCL1_DBG,
|
||||
CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH,
|
||||
CLK_CON_MUX_MUX_CLKCMU_DPU,
|
||||
CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH,
|
||||
CLK_CON_MUX_MUX_CLKCMU_HSI_BUS,
|
||||
@@ -152,6 +171,10 @@ static const unsigned long top_clk_regs[] __initconst = {
|
||||
CLK_CON_DIV_CLKCMU_CORE_CCI,
|
||||
CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD,
|
||||
CLK_CON_DIV_CLKCMU_CORE_SSS,
|
||||
CLK_CON_DIV_CLKCMU_CPUCL0_DBG,
|
||||
CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH,
|
||||
CLK_CON_DIV_CLKCMU_CPUCL1_DBG,
|
||||
CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH,
|
||||
CLK_CON_DIV_CLKCMU_DPU,
|
||||
CLK_CON_DIV_CLKCMU_G3D_SWITCH,
|
||||
CLK_CON_DIV_CLKCMU_HSI_BUS,
|
||||
@@ -180,6 +203,10 @@ static const unsigned long top_clk_regs[] __initconst = {
|
||||
CLK_CON_GAT_GATE_CLKCMU_CORE_CCI,
|
||||
CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD,
|
||||
CLK_CON_GAT_GATE_CLKCMU_CORE_SSS,
|
||||
CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG,
|
||||
CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH,
|
||||
CLK_CON_GAT_GATE_CLKCMU_CPUCL1_DBG,
|
||||
CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH,
|
||||
CLK_CON_GAT_GATE_CLKCMU_DPU,
|
||||
CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH,
|
||||
CLK_CON_GAT_GATE_CLKCMU_HSI_BUS,
|
||||
@@ -234,6 +261,14 @@ PNAME(mout_core_mmc_embd_p) = { "oscclk", "dout_shared0_div2",
|
||||
"oscclk", "oscclk" };
|
||||
PNAME(mout_core_sss_p) = { "dout_shared0_div3", "dout_shared1_div3",
|
||||
"dout_shared0_div4", "dout_shared1_div4" };
|
||||
/* List of parent clocks for Muxes in CMU_TOP: for CMU_CPUCL0 */
|
||||
PNAME(mout_cpucl0_switch_p) = { "fout_shared0_pll", "fout_shared1_pll",
|
||||
"dout_shared0_div2", "dout_shared1_div2" };
|
||||
PNAME(mout_cpucl0_dbg_p) = { "dout_shared0_div4", "dout_shared1_div4" };
|
||||
/* List of parent clocks for Muxes in CMU_TOP: for CMU_CPUCL1 */
|
||||
PNAME(mout_cpucl1_switch_p) = { "fout_shared0_pll", "fout_shared1_pll",
|
||||
"dout_shared0_div2", "dout_shared1_div2" };
|
||||
PNAME(mout_cpucl1_dbg_p) = { "dout_shared0_div4", "dout_shared1_div4" };
|
||||
/* List of parent clocks for Muxes in CMU_TOP: for CMU_G3D */
|
||||
PNAME(mout_g3d_switch_p) = { "dout_shared0_div2", "dout_shared1_div2",
|
||||
"dout_shared0_div3", "dout_shared1_div3" };
|
||||
@@ -300,6 +335,18 @@ static const struct samsung_mux_clock top_mux_clks[] __initconst = {
|
||||
MUX(CLK_MOUT_CORE_SSS, "mout_core_sss", mout_core_sss_p,
|
||||
CLK_CON_MUX_MUX_CLKCMU_CORE_SSS, 0, 2),
|
||||
|
||||
/* CPUCL0 */
|
||||
MUX(CLK_MOUT_CPUCL0_DBG, "mout_cpucl0_dbg", mout_cpucl0_dbg_p,
|
||||
CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG, 0, 1),
|
||||
MUX(CLK_MOUT_CPUCL0_SWITCH, "mout_cpucl0_switch", mout_cpucl0_switch_p,
|
||||
CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH, 0, 2),
|
||||
|
||||
/* CPUCL1 */
|
||||
MUX(CLK_MOUT_CPUCL1_DBG, "mout_cpucl1_dbg", mout_cpucl1_dbg_p,
|
||||
CLK_CON_MUX_MUX_CLKCMU_CPUCL1_DBG, 0, 1),
|
||||
MUX(CLK_MOUT_CPUCL1_SWITCH, "mout_cpucl1_switch", mout_cpucl1_switch_p,
|
||||
CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH, 0, 2),
|
||||
|
||||
/* DPU */
|
||||
MUX(CLK_MOUT_DPU, "mout_dpu", mout_dpu_p,
|
||||
CLK_CON_MUX_MUX_CLKCMU_DPU, 0, 2),
|
||||
@@ -378,6 +425,18 @@ static const struct samsung_div_clock top_div_clks[] __initconst = {
|
||||
DIV(CLK_DOUT_CORE_SSS, "dout_core_sss", "gout_core_sss",
|
||||
CLK_CON_DIV_CLKCMU_CORE_SSS, 0, 4),
|
||||
|
||||
/* CPUCL0 */
|
||||
DIV(CLK_DOUT_CPUCL0_DBG, "dout_cpucl0_dbg", "gout_cpucl0_dbg",
|
||||
CLK_CON_DIV_CLKCMU_CPUCL0_DBG, 0, 3),
|
||||
DIV(CLK_DOUT_CPUCL0_SWITCH, "dout_cpucl0_switch", "gout_cpucl0_switch",
|
||||
CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH, 0, 3),
|
||||
|
||||
/* CPUCL1 */
|
||||
DIV(CLK_DOUT_CPUCL1_DBG, "dout_cpucl1_dbg", "gout_cpucl1_dbg",
|
||||
CLK_CON_DIV_CLKCMU_CPUCL1_DBG, 0, 3),
|
||||
DIV(CLK_DOUT_CPUCL1_SWITCH, "dout_cpucl1_switch", "gout_cpucl1_switch",
|
||||
CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH, 0, 3),
|
||||
|
||||
/* DPU */
|
||||
DIV(CLK_DOUT_DPU, "dout_dpu", "gout_dpu",
|
||||
CLK_CON_DIV_CLKCMU_DPU, 0, 4),
|
||||
@@ -442,6 +501,18 @@ static const struct samsung_gate_clock top_gate_clks[] __initconst = {
|
||||
GATE(CLK_GOUT_AUD, "gout_aud", "mout_aud",
|
||||
CLK_CON_GAT_GATE_CLKCMU_AUD, 21, 0, 0),
|
||||
|
||||
/* CPUCL0 */
|
||||
GATE(CLK_GOUT_CPUCL0_DBG, "gout_cpucl0_dbg", "mout_cpucl0_dbg",
|
||||
CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG, 21, 0, 0),
|
||||
GATE(CLK_GOUT_CPUCL0_SWITCH, "gout_cpucl0_switch", "mout_cpucl0_switch",
|
||||
CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH, 21, 0, 0),
|
||||
|
||||
/* CPUCL1 */
|
||||
GATE(CLK_GOUT_CPUCL1_DBG, "gout_cpucl1_dbg", "mout_cpucl1_dbg",
|
||||
CLK_CON_GAT_GATE_CLKCMU_CPUCL1_DBG, 21, 0, 0),
|
||||
GATE(CLK_GOUT_CPUCL1_SWITCH, "gout_cpucl1_switch", "mout_cpucl1_switch",
|
||||
CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH, 21, 0, 0),
|
||||
|
||||
/* DPU */
|
||||
GATE(CLK_GOUT_DPU, "gout_dpu", "mout_dpu",
|
||||
CLK_CON_GAT_GATE_CLKCMU_DPU, 21, 0, 0),
|
||||
@@ -1030,6 +1101,373 @@ static const struct samsung_cmu_info cmgp_cmu_info __initconst = {
|
||||
.clk_name = "gout_clkcmu_cmgp_bus",
|
||||
};
|
||||
|
||||
/* ---- CMU_CPUCL0 ---------------------------------------------------------- */
|
||||
|
||||
/* Register Offset definitions for CMU_CPUCL0 (0x10900000) */
|
||||
#define PLL_LOCKTIME_PLL_CPUCL0 0x0000
|
||||
#define PLL_CON0_PLL_CPUCL0 0x0100
|
||||
#define PLL_CON1_PLL_CPUCL0 0x0104
|
||||
#define PLL_CON3_PLL_CPUCL0 0x010c
|
||||
#define PLL_CON0_MUX_CLKCMU_CPUCL0_DBG_USER 0x0600
|
||||
#define PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER 0x0610
|
||||
#define CLK_CON_MUX_MUX_CLK_CPUCL0_PLL 0x100c
|
||||
#define CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK 0x1800
|
||||
#define CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK 0x1808
|
||||
#define CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLKDBG 0x180c
|
||||
#define CLK_CON_DIV_DIV_CLK_CLUSTER0_PERIPHCLK 0x1810
|
||||
#define CLK_CON_DIV_DIV_CLK_CPUCL0_CMUREF 0x1814
|
||||
#define CLK_CON_DIV_DIV_CLK_CPUCL0_CPU 0x1818
|
||||
#define CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK 0x181c
|
||||
#define CLK_CON_GAT_CLK_CPUCL0_CLUSTER0_ATCLK 0x2000
|
||||
#define CLK_CON_GAT_CLK_CPUCL0_CLUSTER0_PCLK 0x2004
|
||||
#define CLK_CON_GAT_CLK_CPUCL0_CLUSTER0_PERIPHCLK 0x2008
|
||||
#define CLK_CON_GAT_CLK_CPUCL0_CLUSTER0_SCLK 0x200c
|
||||
#define CLK_CON_GAT_CLK_CPUCL0_CMU_CPUCL0_PCLK 0x2010
|
||||
#define CLK_CON_GAT_GATE_CLK_CPUCL0_CPU 0x2020
|
||||
|
||||
static const unsigned long cpucl0_clk_regs[] __initconst = {
|
||||
PLL_LOCKTIME_PLL_CPUCL0,
|
||||
PLL_CON0_PLL_CPUCL0,
|
||||
PLL_CON1_PLL_CPUCL0,
|
||||
PLL_CON3_PLL_CPUCL0,
|
||||
PLL_CON0_MUX_CLKCMU_CPUCL0_DBG_USER,
|
||||
PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER,
|
||||
CLK_CON_MUX_MUX_CLK_CPUCL0_PLL,
|
||||
CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK,
|
||||
CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK,
|
||||
CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLKDBG,
|
||||
CLK_CON_DIV_DIV_CLK_CLUSTER0_PERIPHCLK,
|
||||
CLK_CON_DIV_DIV_CLK_CPUCL0_CMUREF,
|
||||
CLK_CON_DIV_DIV_CLK_CPUCL0_CPU,
|
||||
CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK,
|
||||
CLK_CON_GAT_CLK_CPUCL0_CLUSTER0_ATCLK,
|
||||
CLK_CON_GAT_CLK_CPUCL0_CLUSTER0_PCLK,
|
||||
CLK_CON_GAT_CLK_CPUCL0_CLUSTER0_PERIPHCLK,
|
||||
CLK_CON_GAT_CLK_CPUCL0_CLUSTER0_SCLK,
|
||||
CLK_CON_GAT_CLK_CPUCL0_CMU_CPUCL0_PCLK,
|
||||
CLK_CON_GAT_GATE_CLK_CPUCL0_CPU,
|
||||
};
|
||||
|
||||
/* List of parent clocks for Muxes in CMU_CPUCL0 */
|
||||
PNAME(mout_pll_cpucl0_p) = { "oscclk", "fout_cpucl0_pll" };
|
||||
PNAME(mout_cpucl0_switch_user_p) = { "oscclk", "dout_cpucl0_switch" };
|
||||
PNAME(mout_cpucl0_dbg_user_p) = { "oscclk", "dout_cpucl0_dbg" };
|
||||
PNAME(mout_cpucl0_pll_p) = { "mout_pll_cpucl0",
|
||||
"mout_cpucl0_switch_user" };
|
||||
|
||||
static const struct samsung_pll_rate_table cpu_pll_rates[] __initconst = {
|
||||
PLL_35XX_RATE(26 * MHZ, 2210000000U, 255, 3, 0),
|
||||
PLL_35XX_RATE(26 * MHZ, 2106000000U, 243, 3, 0),
|
||||
PLL_35XX_RATE(26 * MHZ, 2002000000U, 231, 3, 0),
|
||||
PLL_35XX_RATE(26 * MHZ, 1846000000U, 213, 3, 0),
|
||||
PLL_35XX_RATE(26 * MHZ, 1742000000U, 201, 3, 0),
|
||||
PLL_35XX_RATE(26 * MHZ, 1586000000U, 183, 3, 0),
|
||||
PLL_35XX_RATE(26 * MHZ, 1456000000U, 168, 3, 0),
|
||||
PLL_35XX_RATE(26 * MHZ, 1300000000U, 150, 3, 0),
|
||||
PLL_35XX_RATE(26 * MHZ, 1157000000U, 267, 3, 1),
|
||||
PLL_35XX_RATE(26 * MHZ, 1053000000U, 243, 3, 1),
|
||||
PLL_35XX_RATE(26 * MHZ, 949000000U, 219, 3, 1),
|
||||
PLL_35XX_RATE(26 * MHZ, 806000000U, 186, 3, 1),
|
||||
PLL_35XX_RATE(26 * MHZ, 650000000U, 150, 3, 1),
|
||||
PLL_35XX_RATE(26 * MHZ, 546000000U, 252, 3, 2),
|
||||
PLL_35XX_RATE(26 * MHZ, 442000000U, 204, 3, 2),
|
||||
PLL_35XX_RATE(26 * MHZ, 351000000U, 162, 3, 2),
|
||||
PLL_35XX_RATE(26 * MHZ, 247000000U, 114, 3, 2),
|
||||
PLL_35XX_RATE(26 * MHZ, 182000000U, 168, 3, 3),
|
||||
PLL_35XX_RATE(26 * MHZ, 130000000U, 120, 3, 3),
|
||||
};
|
||||
|
||||
static const struct samsung_pll_clock cpucl0_pll_clks[] __initconst = {
|
||||
PLL(pll_0822x, CLK_FOUT_CPUCL0_PLL, "fout_cpucl0_pll", "oscclk",
|
||||
PLL_LOCKTIME_PLL_CPUCL0, PLL_CON3_PLL_CPUCL0, cpu_pll_rates),
|
||||
};
|
||||
|
||||
static const struct samsung_mux_clock cpucl0_mux_clks[] __initconst = {
|
||||
MUX_F(CLK_MOUT_PLL_CPUCL0, "mout_pll_cpucl0", mout_pll_cpucl0_p,
|
||||
PLL_CON0_PLL_CPUCL0, 4, 1,
|
||||
CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0),
|
||||
MUX_F(CLK_MOUT_CPUCL0_SWITCH_USER, "mout_cpucl0_switch_user",
|
||||
mout_cpucl0_switch_user_p,
|
||||
PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER, 4, 1,
|
||||
CLK_SET_RATE_PARENT, 0),
|
||||
MUX(CLK_MOUT_CPUCL0_DBG_USER, "mout_cpucl0_dbg_user",
|
||||
mout_cpucl0_dbg_user_p,
|
||||
PLL_CON0_MUX_CLKCMU_CPUCL0_DBG_USER, 4, 1),
|
||||
MUX_F(CLK_MOUT_CPUCL0_PLL, "mout_cpucl0_pll", mout_cpucl0_pll_p,
|
||||
CLK_CON_MUX_MUX_CLK_CPUCL0_PLL, 0, 1, CLK_SET_RATE_PARENT, 0),
|
||||
};
|
||||
|
||||
static const struct samsung_div_clock cpucl0_div_clks[] __initconst = {
|
||||
DIV_F(CLK_DOUT_CPUCL0_CPU, "dout_cpucl0_cpu", "mout_cpucl0_pll",
|
||||
CLK_CON_DIV_DIV_CLK_CPUCL0_CPU, 0, 1,
|
||||
CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
|
||||
DIV_F(CLK_DOUT_CPUCL0_CMUREF, "dout_cpucl0_cmuref", "dout_cpucl0_cpu",
|
||||
CLK_CON_DIV_DIV_CLK_CPUCL0_CMUREF, 0, 3,
|
||||
CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
|
||||
DIV_F(CLK_DOUT_CPUCL0_PCLK, "dout_cpucl0_pclk", "dout_cpucl0_cpu",
|
||||
CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK, 0, 4,
|
||||
CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
|
||||
|
||||
/* EMBEDDED_CMU_CPUCL0 */
|
||||
DIV_F(CLK_DOUT_CLUSTER0_ACLK, "dout_cluster0_aclk", "gout_cluster0_cpu",
|
||||
CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK, 0, 4,
|
||||
CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
|
||||
DIV_F(CLK_DOUT_CLUSTER0_ATCLK, "dout_cluster0_atclk",
|
||||
"gout_cluster0_cpu", CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK, 0, 4,
|
||||
CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
|
||||
DIV_F(CLK_DOUT_CLUSTER0_PCLKDBG, "dout_cluster0_pclkdbg",
|
||||
"gout_cluster0_cpu", CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLKDBG, 0, 4,
|
||||
CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
|
||||
DIV_F(CLK_DOUT_CLUSTER0_PERIPHCLK, "dout_cluster0_periphclk",
|
||||
"gout_cluster0_cpu", CLK_CON_DIV_DIV_CLK_CLUSTER0_PERIPHCLK, 0, 4,
|
||||
CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
|
||||
};
|
||||
|
||||
static const struct samsung_gate_clock cpucl0_gate_clks[] __initconst = {
|
||||
GATE(CLK_GOUT_CPUCL0_CMU_CPUCL0_PCLK, "gout_cpucl0_cmu_cpucl0_pclk",
|
||||
"dout_cpucl0_pclk",
|
||||
CLK_CON_GAT_CLK_CPUCL0_CMU_CPUCL0_PCLK, 21, CLK_IGNORE_UNUSED, 0),
|
||||
|
||||
/* EMBEDDED_CMU_CPUCL0 */
|
||||
GATE(CLK_GOUT_CLUSTER0_CPU, "gout_cluster0_cpu", "dout_cpucl0_cpu",
|
||||
CLK_CON_GAT_GATE_CLK_CPUCL0_CPU, 21, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(CLK_GOUT_CLUSTER0_SCLK, "gout_cluster0_sclk", "gout_cluster0_cpu",
|
||||
CLK_CON_GAT_CLK_CPUCL0_CLUSTER0_SCLK, 21, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(CLK_GOUT_CLUSTER0_ATCLK, "gout_cluster0_atclk",
|
||||
"dout_cluster0_atclk",
|
||||
CLK_CON_GAT_CLK_CPUCL0_CLUSTER0_ATCLK, 21, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(CLK_GOUT_CLUSTER0_PERIPHCLK, "gout_cluster0_periphclk",
|
||||
"dout_cluster0_periphclk",
|
||||
CLK_CON_GAT_CLK_CPUCL0_CLUSTER0_PERIPHCLK, 21,
|
||||
CLK_IGNORE_UNUSED, 0),
|
||||
GATE(CLK_GOUT_CLUSTER0_PCLK, "gout_cluster0_pclk",
|
||||
"dout_cluster0_pclkdbg",
|
||||
CLK_CON_GAT_CLK_CPUCL0_CLUSTER0_PCLK, 21, CLK_IGNORE_UNUSED, 0),
|
||||
};
|
||||
|
||||
/*
|
||||
* Each parameter is going to be written into the corresponding DIV register. So
|
||||
* the actual divider value for each parameter will be 1/(param+1). All these
|
||||
* parameters must be in the range of 0..15, as the divider range for all of
|
||||
* these DIV clocks is 1..16. The default values for these dividers is
|
||||
* (1, 3, 3, 1).
|
||||
*/
|
||||
#define E850_CPU_DIV0(aclk, atclk, pclkdbg, periphclk) \
|
||||
(((aclk) << 16) | ((atclk) << 12) | ((pclkdbg) << 8) | \
|
||||
((periphclk) << 4))
|
||||
|
||||
static const struct exynos_cpuclk_cfg_data exynos850_cluster_clk_d[] __initconst
|
||||
= {
|
||||
{ 2210000, E850_CPU_DIV0(1, 3, 3, 1) },
|
||||
{ 2106000, E850_CPU_DIV0(1, 3, 3, 1) },
|
||||
{ 2002000, E850_CPU_DIV0(1, 3, 3, 1) },
|
||||
{ 1846000, E850_CPU_DIV0(1, 3, 3, 1) },
|
||||
{ 1742000, E850_CPU_DIV0(1, 3, 3, 1) },
|
||||
{ 1586000, E850_CPU_DIV0(1, 3, 3, 1) },
|
||||
{ 1456000, E850_CPU_DIV0(1, 3, 3, 1) },
|
||||
{ 1300000, E850_CPU_DIV0(1, 3, 3, 1) },
|
||||
{ 1157000, E850_CPU_DIV0(1, 3, 3, 1) },
|
||||
{ 1053000, E850_CPU_DIV0(1, 3, 3, 1) },
|
||||
{ 949000, E850_CPU_DIV0(1, 3, 3, 1) },
|
||||
{ 806000, E850_CPU_DIV0(1, 3, 3, 1) },
|
||||
{ 650000, E850_CPU_DIV0(1, 3, 3, 1) },
|
||||
{ 546000, E850_CPU_DIV0(1, 3, 3, 1) },
|
||||
{ 442000, E850_CPU_DIV0(1, 3, 3, 1) },
|
||||
{ 351000, E850_CPU_DIV0(1, 3, 3, 1) },
|
||||
{ 247000, E850_CPU_DIV0(1, 3, 3, 1) },
|
||||
{ 182000, E850_CPU_DIV0(1, 3, 3, 1) },
|
||||
{ 130000, E850_CPU_DIV0(1, 3, 3, 1) },
|
||||
{ 0 }
|
||||
};
|
||||
|
||||
static const struct samsung_cpu_clock cpucl0_cpu_clks[] __initconst = {
|
||||
CPU_CLK(CLK_CLUSTER0_SCLK, "cluster0_clk", CLK_MOUT_PLL_CPUCL0,
|
||||
CLK_MOUT_CPUCL0_SWITCH_USER, 0, 0x0, CPUCLK_LAYOUT_E850_CL0,
|
||||
exynos850_cluster_clk_d),
|
||||
};
|
||||
|
||||
static const struct samsung_cmu_info cpucl0_cmu_info __initconst = {
|
||||
.pll_clks = cpucl0_pll_clks,
|
||||
.nr_pll_clks = ARRAY_SIZE(cpucl0_pll_clks),
|
||||
.mux_clks = cpucl0_mux_clks,
|
||||
.nr_mux_clks = ARRAY_SIZE(cpucl0_mux_clks),
|
||||
.div_clks = cpucl0_div_clks,
|
||||
.nr_div_clks = ARRAY_SIZE(cpucl0_div_clks),
|
||||
.gate_clks = cpucl0_gate_clks,
|
||||
.nr_gate_clks = ARRAY_SIZE(cpucl0_gate_clks),
|
||||
.cpu_clks = cpucl0_cpu_clks,
|
||||
.nr_cpu_clks = ARRAY_SIZE(cpucl0_cpu_clks),
|
||||
.nr_clk_ids = CLKS_NR_CPUCL0,
|
||||
.clk_regs = cpucl0_clk_regs,
|
||||
.nr_clk_regs = ARRAY_SIZE(cpucl0_clk_regs),
|
||||
.clk_name = "dout_cpucl0_switch",
|
||||
.manual_plls = true,
|
||||
};
|
||||
|
||||
static void __init exynos850_cmu_cpucl0_init(struct device_node *np)
|
||||
{
|
||||
exynos_arm64_register_cmu(NULL, np, &cpucl0_cmu_info);
|
||||
}
|
||||
|
||||
/* Register CMU_CPUCL0 early, as CPU clocks should be available ASAP */
|
||||
CLK_OF_DECLARE(exynos850_cmu_cpucl0, "samsung,exynos850-cmu-cpucl0",
|
||||
exynos850_cmu_cpucl0_init);
|
||||
|
||||
/* ---- CMU_CPUCL1 ---------------------------------------------------------- */
|
||||
|
||||
/* Register Offset definitions for CMU_CPUCL1 (0x10800000) */
|
||||
#define PLL_LOCKTIME_PLL_CPUCL1 0x0000
|
||||
#define PLL_CON0_PLL_CPUCL1 0x0100
|
||||
#define PLL_CON1_PLL_CPUCL1 0x0104
|
||||
#define PLL_CON3_PLL_CPUCL1 0x010c
|
||||
#define PLL_CON0_MUX_CLKCMU_CPUCL1_DBG_USER 0x0600
|
||||
#define PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER 0x0610
|
||||
#define CLK_CON_MUX_MUX_CLK_CPUCL1_PLL 0x1000
|
||||
#define CLK_CON_DIV_DIV_CLK_CLUSTER1_ACLK 0x1800
|
||||
#define CLK_CON_DIV_DIV_CLK_CLUSTER1_ATCLK 0x1808
|
||||
#define CLK_CON_DIV_DIV_CLK_CLUSTER1_PCLKDBG 0x180c
|
||||
#define CLK_CON_DIV_DIV_CLK_CLUSTER1_PERIPHCLK 0x1810
|
||||
#define CLK_CON_DIV_DIV_CLK_CPUCL1_CMUREF 0x1814
|
||||
#define CLK_CON_DIV_DIV_CLK_CPUCL1_CPU 0x1818
|
||||
#define CLK_CON_DIV_DIV_CLK_CPUCL1_PCLK 0x181c
|
||||
#define CLK_CON_GAT_CLK_CPUCL1_CLUSTER1_ATCLK 0x2000
|
||||
#define CLK_CON_GAT_CLK_CPUCL1_CLUSTER1_PCLK 0x2004
|
||||
#define CLK_CON_GAT_CLK_CPUCL1_CLUSTER1_PERIPHCLK 0x2008
|
||||
#define CLK_CON_GAT_CLK_CPUCL1_CLUSTER1_SCLK 0x200c
|
||||
#define CLK_CON_GAT_CLK_CPUCL1_CMU_CPUCL1_PCLK 0x2010
|
||||
#define CLK_CON_GAT_GATE_CLK_CPUCL1_CPU 0x2020
|
||||
|
||||
static const unsigned long cpucl1_clk_regs[] __initconst = {
|
||||
PLL_LOCKTIME_PLL_CPUCL1,
|
||||
PLL_CON0_PLL_CPUCL1,
|
||||
PLL_CON1_PLL_CPUCL1,
|
||||
PLL_CON3_PLL_CPUCL1,
|
||||
PLL_CON0_MUX_CLKCMU_CPUCL1_DBG_USER,
|
||||
PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER,
|
||||
CLK_CON_MUX_MUX_CLK_CPUCL1_PLL,
|
||||
CLK_CON_DIV_DIV_CLK_CLUSTER1_ACLK,
|
||||
CLK_CON_DIV_DIV_CLK_CLUSTER1_ATCLK,
|
||||
CLK_CON_DIV_DIV_CLK_CLUSTER1_PCLKDBG,
|
||||
CLK_CON_DIV_DIV_CLK_CLUSTER1_PERIPHCLK,
|
||||
CLK_CON_DIV_DIV_CLK_CPUCL1_CMUREF,
|
||||
CLK_CON_DIV_DIV_CLK_CPUCL1_CPU,
|
||||
CLK_CON_DIV_DIV_CLK_CPUCL1_PCLK,
|
||||
CLK_CON_GAT_CLK_CPUCL1_CLUSTER1_ATCLK,
|
||||
CLK_CON_GAT_CLK_CPUCL1_CLUSTER1_PCLK,
|
||||
CLK_CON_GAT_CLK_CPUCL1_CLUSTER1_PERIPHCLK,
|
||||
CLK_CON_GAT_CLK_CPUCL1_CLUSTER1_SCLK,
|
||||
CLK_CON_GAT_CLK_CPUCL1_CMU_CPUCL1_PCLK,
|
||||
CLK_CON_GAT_GATE_CLK_CPUCL1_CPU,
|
||||
};
|
||||
|
||||
/* List of parent clocks for Muxes in CMU_CPUCL0 */
|
||||
PNAME(mout_pll_cpucl1_p) = { "oscclk", "fout_cpucl1_pll" };
|
||||
PNAME(mout_cpucl1_switch_user_p) = { "oscclk", "dout_cpucl1_switch" };
|
||||
PNAME(mout_cpucl1_dbg_user_p) = { "oscclk", "dout_cpucl1_dbg" };
|
||||
PNAME(mout_cpucl1_pll_p) = { "mout_pll_cpucl1",
|
||||
"mout_cpucl1_switch_user" };
|
||||
|
||||
static const struct samsung_pll_clock cpucl1_pll_clks[] __initconst = {
|
||||
PLL(pll_0822x, CLK_FOUT_CPUCL1_PLL, "fout_cpucl1_pll", "oscclk",
|
||||
PLL_LOCKTIME_PLL_CPUCL1, PLL_CON3_PLL_CPUCL1, cpu_pll_rates),
|
||||
};
|
||||
|
||||
static const struct samsung_mux_clock cpucl1_mux_clks[] __initconst = {
|
||||
MUX_F(CLK_MOUT_PLL_CPUCL1, "mout_pll_cpucl1", mout_pll_cpucl1_p,
|
||||
PLL_CON0_PLL_CPUCL1, 4, 1,
|
||||
CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0),
|
||||
MUX_F(CLK_MOUT_CPUCL1_SWITCH_USER, "mout_cpucl1_switch_user",
|
||||
mout_cpucl1_switch_user_p,
|
||||
PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER, 4, 1,
|
||||
CLK_SET_RATE_PARENT, 0),
|
||||
MUX(CLK_MOUT_CPUCL1_DBG_USER, "mout_cpucl1_dbg_user",
|
||||
mout_cpucl1_dbg_user_p,
|
||||
PLL_CON0_MUX_CLKCMU_CPUCL1_DBG_USER, 4, 1),
|
||||
MUX_F(CLK_MOUT_CPUCL1_PLL, "mout_cpucl1_pll", mout_cpucl1_pll_p,
|
||||
CLK_CON_MUX_MUX_CLK_CPUCL1_PLL, 0, 1, CLK_SET_RATE_PARENT, 0),
|
||||
};
|
||||
|
||||
static const struct samsung_div_clock cpucl1_div_clks[] __initconst = {
|
||||
DIV_F(CLK_DOUT_CPUCL1_CPU, "dout_cpucl1_cpu", "mout_cpucl1_pll",
|
||||
CLK_CON_DIV_DIV_CLK_CPUCL1_CPU, 0, 1,
|
||||
CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
|
||||
DIV_F(CLK_DOUT_CPUCL1_CMUREF, "dout_cpucl1_cmuref", "dout_cpucl1_cpu",
|
||||
CLK_CON_DIV_DIV_CLK_CPUCL1_CMUREF, 0, 3,
|
||||
CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
|
||||
DIV_F(CLK_DOUT_CPUCL1_PCLK, "dout_cpucl1_pclk", "dout_cpucl1_cpu",
|
||||
CLK_CON_DIV_DIV_CLK_CPUCL1_PCLK, 0, 4,
|
||||
CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
|
||||
|
||||
/* EMBEDDED_CMU_CPUCL1 */
|
||||
DIV_F(CLK_DOUT_CLUSTER1_ACLK, "dout_cluster1_aclk", "gout_cluster1_cpu",
|
||||
CLK_CON_DIV_DIV_CLK_CLUSTER1_ACLK, 0, 4,
|
||||
CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
|
||||
DIV_F(CLK_DOUT_CLUSTER1_ATCLK, "dout_cluster1_atclk",
|
||||
"gout_cluster1_cpu", CLK_CON_DIV_DIV_CLK_CLUSTER1_ATCLK, 0, 4,
|
||||
CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
|
||||
DIV_F(CLK_DOUT_CLUSTER1_PCLKDBG, "dout_cluster1_pclkdbg",
|
||||
"gout_cluster1_cpu", CLK_CON_DIV_DIV_CLK_CLUSTER1_PCLKDBG, 0, 4,
|
||||
CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
|
||||
DIV_F(CLK_DOUT_CLUSTER1_PERIPHCLK, "dout_cluster1_periphclk",
|
||||
"gout_cluster1_cpu", CLK_CON_DIV_DIV_CLK_CLUSTER1_PERIPHCLK, 0, 4,
|
||||
CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
|
||||
};
|
||||
|
||||
static const struct samsung_gate_clock cpucl1_gate_clks[] __initconst = {
|
||||
GATE(CLK_GOUT_CPUCL1_CMU_CPUCL1_PCLK, "gout_cpucl1_cmu_cpucl1_pclk",
|
||||
"dout_cpucl1_pclk",
|
||||
CLK_CON_GAT_CLK_CPUCL1_CMU_CPUCL1_PCLK, 21, CLK_IGNORE_UNUSED, 0),
|
||||
|
||||
/* EMBEDDED_CMU_CPUCL1 */
|
||||
GATE(CLK_GOUT_CLUSTER1_CPU, "gout_cluster1_cpu", "dout_cpucl1_cpu",
|
||||
CLK_CON_GAT_GATE_CLK_CPUCL1_CPU, 21, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(CLK_GOUT_CLUSTER1_SCLK, "gout_cluster1_sclk", "gout_cluster1_cpu",
|
||||
CLK_CON_GAT_CLK_CPUCL1_CLUSTER1_SCLK, 21, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(CLK_GOUT_CLUSTER1_ATCLK, "gout_cluster1_atclk",
|
||||
"dout_cluster1_atclk",
|
||||
CLK_CON_GAT_CLK_CPUCL1_CLUSTER1_ATCLK, 21, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(CLK_GOUT_CLUSTER1_PERIPHCLK, "gout_cluster1_periphclk",
|
||||
"dout_cluster1_periphclk",
|
||||
CLK_CON_GAT_CLK_CPUCL1_CLUSTER1_PERIPHCLK, 21,
|
||||
CLK_IGNORE_UNUSED, 0),
|
||||
GATE(CLK_GOUT_CLUSTER1_PCLK, "gout_cluster1_pclk",
|
||||
"dout_cluster1_pclkdbg",
|
||||
CLK_CON_GAT_CLK_CPUCL1_CLUSTER1_PCLK, 21, CLK_IGNORE_UNUSED, 0),
|
||||
};
|
||||
|
||||
static const struct samsung_cpu_clock cpucl1_cpu_clks[] __initconst = {
|
||||
CPU_CLK(CLK_CLUSTER1_SCLK, "cluster1_clk", CLK_MOUT_PLL_CPUCL1,
|
||||
CLK_MOUT_CPUCL1_SWITCH_USER, 0, 0x0, CPUCLK_LAYOUT_E850_CL1,
|
||||
exynos850_cluster_clk_d),
|
||||
};
|
||||
|
||||
static const struct samsung_cmu_info cpucl1_cmu_info __initconst = {
|
||||
.pll_clks = cpucl1_pll_clks,
|
||||
.nr_pll_clks = ARRAY_SIZE(cpucl1_pll_clks),
|
||||
.mux_clks = cpucl1_mux_clks,
|
||||
.nr_mux_clks = ARRAY_SIZE(cpucl1_mux_clks),
|
||||
.div_clks = cpucl1_div_clks,
|
||||
.nr_div_clks = ARRAY_SIZE(cpucl1_div_clks),
|
||||
.gate_clks = cpucl1_gate_clks,
|
||||
.nr_gate_clks = ARRAY_SIZE(cpucl1_gate_clks),
|
||||
.cpu_clks = cpucl1_cpu_clks,
|
||||
.nr_cpu_clks = ARRAY_SIZE(cpucl1_cpu_clks),
|
||||
.nr_clk_ids = CLKS_NR_CPUCL1,
|
||||
.clk_regs = cpucl1_clk_regs,
|
||||
.nr_clk_regs = ARRAY_SIZE(cpucl1_clk_regs),
|
||||
.clk_name = "dout_cpucl1_switch",
|
||||
.manual_plls = true,
|
||||
};
|
||||
|
||||
static void __init exynos850_cmu_cpucl1_init(struct device_node *np)
|
||||
{
|
||||
exynos_arm64_register_cmu(NULL, np, &cpucl1_cmu_info);
|
||||
}
|
||||
|
||||
/* Register CMU_CPUCL1 early, as CPU clocks should be available ASAP */
|
||||
CLK_OF_DECLARE(exynos850_cmu_cpucl1, "samsung,exynos850-cmu-cpucl1",
|
||||
exynos850_cmu_cpucl1_init);
|
||||
|
||||
/* ---- CMU_G3D ------------------------------------------------------------- */
|
||||
|
||||
/* Register Offset definitions for CMU_G3D (0x11400000) */
|
||||
|
||||
@@ -352,13 +352,13 @@ static const struct samsung_pll_clock top_pll_clks[] __initconst = {
|
||||
/* CMU_TOP_PURECLKCOMP */
|
||||
PLL(pll_0822x, FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk",
|
||||
PLL_LOCKTIME_PLL_SHARED0, PLL_CON3_PLL_SHARED0, NULL),
|
||||
PLL(pll_0822x, FOUT_SHARED0_PLL, "fout_shared1_pll", "oscclk",
|
||||
PLL(pll_0822x, FOUT_SHARED1_PLL, "fout_shared1_pll", "oscclk",
|
||||
PLL_LOCKTIME_PLL_SHARED1, PLL_CON3_PLL_SHARED1, NULL),
|
||||
PLL(pll_0822x, FOUT_SHARED0_PLL, "fout_shared2_pll", "oscclk",
|
||||
PLL(pll_0822x, FOUT_SHARED2_PLL, "fout_shared2_pll", "oscclk",
|
||||
PLL_LOCKTIME_PLL_SHARED2, PLL_CON3_PLL_SHARED2, NULL),
|
||||
PLL(pll_0822x, FOUT_SHARED0_PLL, "fout_shared3_pll", "oscclk",
|
||||
PLL(pll_0822x, FOUT_SHARED3_PLL, "fout_shared3_pll", "oscclk",
|
||||
PLL_LOCKTIME_PLL_SHARED3, PLL_CON3_PLL_SHARED3, NULL),
|
||||
PLL(pll_0822x, FOUT_SHARED0_PLL, "fout_shared4_pll", "oscclk",
|
||||
PLL(pll_0822x, FOUT_SHARED4_PLL, "fout_shared4_pll", "oscclk",
|
||||
PLL_LOCKTIME_PLL_SHARED4, PLL_CON3_PLL_SHARED4, NULL),
|
||||
};
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -133,7 +133,7 @@ struct samsung_mux_clock {
|
||||
.name = cname, \
|
||||
.parent_names = pnames, \
|
||||
.num_parents = ARRAY_SIZE(pnames), \
|
||||
.flags = (f) | CLK_SET_RATE_NO_REPARENT, \
|
||||
.flags = f, \
|
||||
.offset = o, \
|
||||
.shift = s, \
|
||||
.width = w, \
|
||||
@@ -141,9 +141,16 @@ struct samsung_mux_clock {
|
||||
}
|
||||
|
||||
#define MUX(_id, cname, pnames, o, s, w) \
|
||||
__MUX(_id, cname, pnames, o, s, w, 0, 0)
|
||||
__MUX(_id, cname, pnames, o, s, w, CLK_SET_RATE_NO_REPARENT, 0)
|
||||
|
||||
#define MUX_F(_id, cname, pnames, o, s, w, f, mf) \
|
||||
__MUX(_id, cname, pnames, o, s, w, (f) | CLK_SET_RATE_NO_REPARENT, mf)
|
||||
|
||||
/* Used by MUX clocks where reparenting on clock rate change is allowed. */
|
||||
#define nMUX(_id, cname, pnames, o, s, w) \
|
||||
__MUX(_id, cname, pnames, o, s, w, 0, 0)
|
||||
|
||||
#define nMUX_F(_id, cname, pnames, o, s, w, f, mf) \
|
||||
__MUX(_id, cname, pnames, o, s, w, f, mf)
|
||||
|
||||
/**
|
||||
@@ -330,6 +337,7 @@ struct samsung_clock_reg_cache {
|
||||
* @suspend_regs: list of clock registers to set before suspend
|
||||
* @nr_suspend_regs: count of clock registers in @suspend_regs
|
||||
* @clk_name: name of the parent clock needed for CMU register access
|
||||
* @manual_plls: Enable manual control for PLL clocks
|
||||
*/
|
||||
struct samsung_cmu_info {
|
||||
const struct samsung_pll_clock *pll_clks;
|
||||
@@ -354,6 +362,9 @@ struct samsung_cmu_info {
|
||||
const struct samsung_clk_reg_dump *suspend_regs;
|
||||
unsigned int nr_suspend_regs;
|
||||
const char *clk_name;
|
||||
|
||||
/* ARM64 Exynos CMUs */
|
||||
bool manual_plls;
|
||||
};
|
||||
|
||||
struct samsung_clk_provider *samsung_clk_init(struct device *dev,
|
||||
|
||||
@@ -313,6 +313,122 @@
|
||||
#define CLK_APM_PLL_DIV4_APM 70
|
||||
#define CLK_APM_PLL_DIV16_APM 71
|
||||
|
||||
/* CMU_HSI0 */
|
||||
#define CLK_FOUT_USB_PLL 1
|
||||
#define CLK_MOUT_PLL_USB 2
|
||||
#define CLK_MOUT_HSI0_ALT_USER 3
|
||||
#define CLK_MOUT_HSI0_BUS_USER 4
|
||||
#define CLK_MOUT_HSI0_DPGTC_USER 5
|
||||
#define CLK_MOUT_HSI0_TCXO_USER 6
|
||||
#define CLK_MOUT_HSI0_USB20_USER 7
|
||||
#define CLK_MOUT_HSI0_USB31DRD_USER 8
|
||||
#define CLK_MOUT_HSI0_USBDPDBG_USER 9
|
||||
#define CLK_MOUT_HSI0_BUS 10
|
||||
#define CLK_MOUT_HSI0_USB20_REF 11
|
||||
#define CLK_MOUT_HSI0_USB31DRD 12
|
||||
#define CLK_DOUT_HSI0_USB31DRD 13
|
||||
#define CLK_GOUT_HSI0_PCLK 14
|
||||
#define CLK_GOUT_HSI0_USB31DRD_I_USB31DRD_SUSPEND_CLK_26 15
|
||||
#define CLK_GOUT_HSI0_CLK_HSI0_ALT 16
|
||||
#define CLK_GOUT_HSI0_DP_LINK_I_DP_GTC_CLK 17
|
||||
#define CLK_GOUT_HSI0_DP_LINK_I_PCLK 18
|
||||
#define CLK_GOUT_HSI0_D_TZPC_HSI0_PCLK 19
|
||||
#define CLK_GOUT_HSI0_ETR_MIU_I_ACLK 20
|
||||
#define CLK_GOUT_HSI0_ETR_MIU_I_PCLK 21
|
||||
#define CLK_GOUT_HSI0_GPC_HSI0_PCLK 22
|
||||
#define CLK_GOUT_HSI0_LHM_AXI_G_ETR_HSI0_I_CLK 23
|
||||
#define CLK_GOUT_HSI0_LHM_AXI_P_AOCHSI0_I_CLK 24
|
||||
#define CLK_GOUT_HSI0_LHM_AXI_P_HSI0_I_CLK 25
|
||||
#define CLK_GOUT_HSI0_LHS_ACEL_D_HSI0_I_CLK 26
|
||||
#define CLK_GOUT_HSI0_LHS_AXI_D_HSI0AOC_I_CLK 27
|
||||
#define CLK_GOUT_HSI0_PPMU_HSI0_AOC_ACLK 28
|
||||
#define CLK_GOUT_HSI0_PPMU_HSI0_AOC_PCLK 29
|
||||
#define CLK_GOUT_HSI0_PPMU_HSI0_BUS0_ACLK 30
|
||||
#define CLK_GOUT_HSI0_PPMU_HSI0_BUS0_PCLK 31
|
||||
#define CLK_GOUT_HSI0_CLK_HSI0_BUS_CLK 32
|
||||
#define CLK_GOUT_HSI0_SSMT_USB_ACLK 33
|
||||
#define CLK_GOUT_HSI0_SSMT_USB_PCLK 34
|
||||
#define CLK_GOUT_HSI0_SYSMMU_USB_CLK_S2 35
|
||||
#define CLK_GOUT_HSI0_SYSREG_HSI0_PCLK 36
|
||||
#define CLK_GOUT_HSI0_UASC_HSI0_CTRL_ACLK 37
|
||||
#define CLK_GOUT_HSI0_UASC_HSI0_CTRL_PCLK 38
|
||||
#define CLK_GOUT_HSI0_UASC_HSI0_LINK_ACLK 39
|
||||
#define CLK_GOUT_HSI0_UASC_HSI0_LINK_PCLK 40
|
||||
#define CLK_GOUT_HSI0_USB31DRD_ACLK_PHYCTRL 41
|
||||
#define CLK_GOUT_HSI0_USB31DRD_BUS_CLK_EARLY 42
|
||||
#define CLK_GOUT_HSI0_USB31DRD_I_USB20_PHY_REFCLK_26 43
|
||||
#define CLK_GOUT_HSI0_USB31DRD_I_USB31DRD_REF_CLK_40 44
|
||||
#define CLK_GOUT_HSI0_USB31DRD_I_USBDPPHY_REF_SOC_PLL 45
|
||||
#define CLK_GOUT_HSI0_USB31DRD_I_USBDPPHY_SCL_APB_PCLK 46
|
||||
#define CLK_GOUT_HSI0_USB31DRD_I_USBPCS_APB_CLK 47
|
||||
#define CLK_GOUT_HSI0_USB31DRD_USBDPPHY_I_ACLK 48
|
||||
#define CLK_GOUT_HSI0_USB31DRD_USBDPPHY_UDBG_I_APB_PCLK 49
|
||||
#define CLK_GOUT_HSI0_XIU_D0_HSI0_ACLK 50
|
||||
#define CLK_GOUT_HSI0_XIU_D1_HSI0_ACLK 51
|
||||
#define CLK_GOUT_HSI0_XIU_P_HSI0_ACLK 52
|
||||
|
||||
/* CMU_HSI2 */
|
||||
#define CLK_MOUT_HSI2_BUS_USER 1
|
||||
#define CLK_MOUT_HSI2_MMC_CARD_USER 2
|
||||
#define CLK_MOUT_HSI2_PCIE_USER 3
|
||||
#define CLK_MOUT_HSI2_UFS_EMBD_USER 4
|
||||
#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_003_PHY_REFCLK_IN 5
|
||||
#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_004_PHY_REFCLK_IN 6
|
||||
#define CLK_GOUT_HSI2_SSMT_PCIE_IA_GEN4A_1_ACLK 7
|
||||
#define CLK_GOUT_HSI2_SSMT_PCIE_IA_GEN4A_1_PCLK 8
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#define CLK_GOUT_HSI2_SSMT_PCIE_IA_GEN4B_1_ACLK 9
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#define CLK_GOUT_HSI2_SSMT_PCIE_IA_GEN4B_1_PCLK 10
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#define CLK_GOUT_HSI2_D_TZPC_HSI2_PCLK 11
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#define CLK_GOUT_HSI2_GPC_HSI2_PCLK 12
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#define CLK_GOUT_HSI2_GPIO_HSI2_PCLK 13
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#define CLK_GOUT_HSI2_HSI2_CMU_HSI2_PCLK 14
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#define CLK_GOUT_HSI2_LHM_AXI_P_HSI2_I_CLK 15
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#define CLK_GOUT_HSI2_LHS_ACEL_D_HSI2_I_CLK 16
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#define CLK_GOUT_HSI2_MMC_CARD_I_ACLK 17
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#define CLK_GOUT_HSI2_MMC_CARD_SDCLKIN 18
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#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_003_DBI_ACLK_UG 19
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#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_003_MSTR_ACLK_UG 20
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#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_003_SLV_ACLK_UG 21
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#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_003_I_DRIVER_APB_CLK 22
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#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_004_DBI_ACLK_UG 23
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#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_004_MSTR_ACLK_UG 24
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#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_004_SLV_ACLK_UG 25
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#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_004_I_DRIVER_APB_CLK 26
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#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCS_PMA_PHY_UDBG_I_APB_PCLK 27
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#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCS_PMA_PIPE_PAL_PCIE_I_APB_PCLK 28
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#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCS_PMA_PCIEPHY210X2_QCH_I_APB_PCLK 29
|
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#define CLK_GOUT_HSI2_PCIE_IA_GEN4A_1_I_CLK 30
|
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#define CLK_GOUT_HSI2_PCIE_IA_GEN4B_1_I_CLK 31
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#define CLK_GOUT_HSI2_PPMU_HSI2_ACLK 32
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#define CLK_GOUT_HSI2_PPMU_HSI2_PCLK 33
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#define CLK_GOUT_HSI2_QE_MMC_CARD_HSI2_ACLK 34
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#define CLK_GOUT_HSI2_QE_MMC_CARD_HSI2_PCLK 35
|
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#define CLK_GOUT_HSI2_QE_PCIE_GEN4A_HSI2_ACLK 36
|
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#define CLK_GOUT_HSI2_QE_PCIE_GEN4A_HSI2_PCLK 37
|
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#define CLK_GOUT_HSI2_QE_PCIE_GEN4B_HSI2_ACLK 38
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#define CLK_GOUT_HSI2_QE_PCIE_GEN4B_HSI2_PCLK 39
|
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#define CLK_GOUT_HSI2_QE_UFS_EMBD_HSI2_ACLK 40
|
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#define CLK_GOUT_HSI2_QE_UFS_EMBD_HSI2_PCLK 41
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#define CLK_GOUT_HSI2_CLK_HSI2_BUS_CLK 42
|
||||
#define CLK_GOUT_HSI2_CLK_HSI2_OSCCLK_CLK 43
|
||||
#define CLK_GOUT_HSI2_SSMT_HSI2_ACLK 44
|
||||
#define CLK_GOUT_HSI2_SSMT_HSI2_PCLK 45
|
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#define CLK_GOUT_HSI2_SYSMMU_HSI2_CLK_S2 46
|
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#define CLK_GOUT_HSI2_SYSREG_HSI2_PCLK 47
|
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#define CLK_GOUT_HSI2_UASC_PCIE_GEN4A_DBI_1_ACLK 48
|
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#define CLK_GOUT_HSI2_UASC_PCIE_GEN4A_DBI_1_PCLK 49
|
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#define CLK_GOUT_HSI2_UASC_PCIE_GEN4A_SLV_1_ACLK 50
|
||||
#define CLK_GOUT_HSI2_UASC_PCIE_GEN4A_SLV_1_PCLK 51
|
||||
#define CLK_GOUT_HSI2_UASC_PCIE_GEN4B_DBI_1_ACLK 52
|
||||
#define CLK_GOUT_HSI2_UASC_PCIE_GEN4B_DBI_1_PCLK 53
|
||||
#define CLK_GOUT_HSI2_UASC_PCIE_GEN4B_SLV_1_ACLK 54
|
||||
#define CLK_GOUT_HSI2_UASC_PCIE_GEN4B_SLV_1_PCLK 55
|
||||
#define CLK_GOUT_HSI2_UFS_EMBD_I_ACLK 56
|
||||
#define CLK_GOUT_HSI2_UFS_EMBD_I_CLK_UNIPRO 57
|
||||
#define CLK_GOUT_HSI2_UFS_EMBD_I_FMP_CLK 58
|
||||
#define CLK_GOUT_HSI2_XIU_D_HSI2_ACLK 59
|
||||
#define CLK_GOUT_HSI2_XIU_P_HSI2_ACLK 60
|
||||
|
||||
/* CMU_MISC */
|
||||
#define CLK_MOUT_MISC_BUS_USER 1
|
||||
#define CLK_MOUT_MISC_SSS_USER 2
|
||||
|
||||
Reference in New Issue
Block a user