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arm64: dts: broadcom: rp1: add csi nodes

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The RaspberryPi 5 has 2 PiSP Camera front end controller on the RP1
chipset.

Add the relevant nodes to the devicetree.

Signed-off-by: Gregor Herburger <gregor.herburger@linutronix.de>
Link: https://lore.kernel.org/r/20260226-raspi-dts-updates-v1-2-60832d20ff04@linutronix.de
Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
This commit is contained in:
Gregor Herburger
2026-02-26 09:55:55 +01:00
committed by Florian Fainelli
parent 531f5a9739
commit cdf38d5997
1 changed files with 28 additions and 0 deletions
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28
arch/arm64/boot/dts/broadcom/rp1-common.dtsi
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@@ -133,6 +133,34 @@ rp1_eth: ethernet@40100000 {
#size-cells = <0>;
};
rp1_csi0: csi@40110000 {
compatible = "raspberrypi,rp1-cfe";
reg = <0x0 0x40110000 0x0 0x100>, // CSI2 DMA address
<0x0 0x40114000 0x0 0x100>, // PHY/CSI Host address
<0x0 0x40120000 0x0 0x100>, // MIPI CFG address
<0x0 0x40124000 0x0 0x1000>; // PiSP FE address
interrupts = <47 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rp1_clocks RP1_CLK_MIPI0_CFG>;
assigned-clocks = <&rp1_clocks RP1_CLK_MIPI0_CFG>;
assigned-clock-rates = <25000000>;
status = "disabled";
};
rp1_csi1: csi@40128000 {
compatible = "raspberrypi,rp1-cfe";
reg = <0x0 0x40128000 0x0 0x100>, // CSI2 DMA address
<0x0 0x4012c000 0x0 0x100>, // PHY/CSI Host address
<0x0 0x40138000 0x0 0x100>, // MIPI CFG address
<0x0 0x4013c000 0x0 0x1000>; // PiSP FE address
interrupts = <48 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rp1_clocks RP1_CLK_MIPI1_CFG>;
assigned-clocks = <&rp1_clocks RP1_CLK_MIPI1_CFG>;
assigned-clock-rates = <25000000>;
status = "disabled";
};
rp1_usb0: usb@40200000 {
compatible = "snps,dwc3";
reg = <0x00 0x40200000 0x0 0x100000>;