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x86/cpuid: Move CPUID(0x2) APIs into <cpuid/api.h>

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Move all of the CPUID(0x2) APIs at <cpuid/leaf_0x2_api.h> into
<cpuid/api.h>, in order centralize all CPUID APIs into the latter.

While at it, separate the different CPUID leaf parsing APIs using
header comments like "CPUID(0xN) parsing: ".

Suggested-by: Ingo Molnar <mingo@kernel.org>
Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Andrew Cooper <andrew.cooper3@citrix.com>
Cc: John Ogness <john.ogness@linutronix.de>
Cc: x86-cpuid@lists.linux.dev
Link: https://lore.kernel.org/r/20250508150240.172915-2-darwi@linutronix.de
This commit is contained in:
Ahmed S. Darwish
2025-05-08 17:02:30 +02:00
committed by Ingo Molnar
parent baad9190e6
commit cdc8be31cb
4 changed files with 75 additions and 77 deletions
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1
arch/x86/include/asm/cpuid.h
View File

@@ -4,6 +4,5 @@
#define _ASM_X86_CPUID_H
#include <asm/cpuid/api.h>
#include <asm/cpuid/leaf_0x2_api.h>
#endif /* _ASM_X86_CPUID_H */

75
arch/x86/include/asm/cpuid/api.h
View File

@@ -160,6 +160,10 @@ static inline void __cpuid_read_reg(u32 leaf, u32 subleaf,
__cpuid_read_reg(leaf, 0, regidx, (u32 *)(reg)); \
}
/*
* Hypervisor-related APIs:
*/
static __always_inline bool cpuid_function_is_indexed(u32 function)
{
switch (function) {
@@ -208,7 +212,76 @@ static inline u32 hypervisor_cpuid_base(const char *sig, u32 leaves)
}
/*
* CPUID(0x80000006) parsing helpers
* CPUID(0x2) parsing:
*/
/**
* cpuid_get_leaf_0x2_regs() - Return sanitized leaf 0x2 register output
* @regs: Output parameter
*
* Query CPUID leaf 0x2 and store its output in @regs. Force set any
* invalid 1-byte descriptor returned by the hardware to zero (the NULL
* cache/TLB descriptor) before returning it to the caller.
*
* Use for_each_leaf_0x2_entry() to iterate over the register output in
* parsed form.
*/
static inline void cpuid_get_leaf_0x2_regs(union leaf_0x2_regs *regs)
{
cpuid_leaf(0x2, regs);
/*
* All Intel CPUs must report an iteration count of 1. In case
* of bogus hardware, treat all returned descriptors as NULL.
*/
if (regs->desc[0] != 0x01) {
for (int i = 0; i < 4; i++)
regs->regv[i] = 0;
return;
}
/*
* The most significant bit (MSB) of each register must be clear.
* If a register is invalid, replace its descriptors with NULL.
*/
for (int i = 0; i < 4; i++) {
if (regs->reg[i].invalid)
regs->regv[i] = 0;
}
}
/**
* for_each_leaf_0x2_entry() - Iterator for parsed leaf 0x2 descriptors
* @regs: Leaf 0x2 register output, returned by cpuid_get_leaf_0x2_regs()
* @__ptr: u8 pointer, for macro internal use only
* @entry: Pointer to parsed descriptor information at each iteration
*
* Loop over the 1-byte descriptors in the passed leaf 0x2 output registers
* @regs. Provide the parsed information for each descriptor through @entry.
*
* To handle cache-specific descriptors, switch on @entry->c_type. For TLB
* descriptors, switch on @entry->t_type.
*
* Example usage for cache descriptors::
*
* const struct leaf_0x2_table *entry;
* union leaf_0x2_regs regs;
* u8 *ptr;
*
* cpuid_get_leaf_0x2_regs(&regs);
* for_each_leaf_0x2_entry(regs, ptr, entry) {
* switch (entry->c_type) {
* ...
* }
* }
*/
#define for_each_leaf_0x2_entry(regs, __ptr, entry) \
for (__ptr = &(regs).desc[1]; \
__ptr < &(regs).desc[16] && (entry = &cpuid_0x2_table[*__ptr]); \
__ptr++)
/*
* CPUID(0x80000006) parsing:
*/
static inline bool cpuid_amd_hygon_has_l3_cache(void)

73
arch/x86/include/asm/cpuid/leaf_0x2_api.h
View File

@@ -1,73 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _ASM_X86_CPUID_LEAF_0x2_API_H
#define _ASM_X86_CPUID_LEAF_0x2_API_H
#include <asm/cpuid/api.h>
#include <asm/cpuid/types.h>
/**
* cpuid_get_leaf_0x2_regs() - Return sanitized leaf 0x2 register output
* @regs: Output parameter
*
* Query CPUID leaf 0x2 and store its output in @regs. Force set any
* invalid 1-byte descriptor returned by the hardware to zero (the NULL
* cache/TLB descriptor) before returning it to the caller.
*
* Use for_each_leaf_0x2_entry() to iterate over the register output in
* parsed form.
*/
static inline void cpuid_get_leaf_0x2_regs(union leaf_0x2_regs *regs)
{
cpuid_leaf(0x2, regs);
/*
* All Intel CPUs must report an iteration count of 1. In case
* of bogus hardware, treat all returned descriptors as NULL.
*/
if (regs->desc[0] != 0x01) {
for (int i = 0; i < 4; i++)
regs->regv[i] = 0;
return;
}
/*
* The most significant bit (MSB) of each register must be clear.
* If a register is invalid, replace its descriptors with NULL.
*/
for (int i = 0; i < 4; i++) {
if (regs->reg[i].invalid)
regs->regv[i] = 0;
}
}
/**
* for_each_leaf_0x2_entry() - Iterator for parsed leaf 0x2 descriptors
* @regs: Leaf 0x2 register output, returned by cpuid_get_leaf_0x2_regs()
* @__ptr: u8 pointer, for macro internal use only
* @entry: Pointer to parsed descriptor information at each iteration
*
* Loop over the 1-byte descriptors in the passed leaf 0x2 output registers
* @regs. Provide the parsed information for each descriptor through @entry.
*
* To handle cache-specific descriptors, switch on @entry->c_type. For TLB
* descriptors, switch on @entry->t_type.
*
* Example usage for cache descriptors::
*
* const struct leaf_0x2_table *entry;
* union leaf_0x2_regs regs;
* u8 *ptr;
*
* cpuid_get_leaf_0x2_regs(&regs);
* for_each_leaf_0x2_entry(regs, ptr, entry) {
* switch (entry->c_type) {
* ...
* }
* }
*/
#define for_each_leaf_0x2_entry(regs, __ptr, entry) \
for (__ptr = &(regs).desc[1]; \
__ptr < &(regs).desc[16] && (entry = &cpuid_0x2_table[*__ptr]); \
__ptr++)
#endif /* _ASM_X86_CPUID_LEAF_0x2_API_H */

3
arch/x86/include/asm/cpuid/types.h
View File

@@ -31,8 +31,7 @@ enum cpuid_regs_idx {
#define CPUID_LEAF_TILE 0x1d
/*
* Types for CPUID(0x2) parsing
* Check <asm/cpuid/leaf_0x2_api.h>
* Types for CPUID(0x2) parsing:
*/
struct leaf_0x2_reg {