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https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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hinic3: HW initialization
Add the hardware resource data structures, functions for HW initialization, configuration and releasement. Co-developed-by: Zhu Yikai <zhuyikai1@h-partners.com> Signed-off-by: Zhu Yikai <zhuyikai1@h-partners.com> Signed-off-by: Fan Gong <gongfan1@huawei.com> Link: https://patch.msgid.link/e3381375e3d4a89e11d4816a0a20a1db4df93b66.1757653621.git.zhuyikai1@h-partners.com Signed-off-by: Paolo Abeni <pabeni@redhat.com>
This commit is contained in:
Fan Gong
@@ -7,15 +7,61 @@
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#include "hinic3_mbox.h"
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#include "hinic3_mgmt.h"
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#define HINIC3_HWDEV_WQ_NAME "hinic3_hardware"
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#define HINIC3_WQ_MAX_REQ 10
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enum hinic3_hwdev_init_state {
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HINIC3_HWDEV_MBOX_INITED = 2,
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HINIC3_HWDEV_CMDQ_INITED = 3,
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};
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int hinic3_init_hwdev(struct pci_dev *pdev)
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{
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/* Completed by later submission due to LoC limit. */
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return -EFAULT;
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struct hinic3_pcidev *pci_adapter = pci_get_drvdata(pdev);
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struct hinic3_hwdev *hwdev;
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int err;
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hwdev = kzalloc(sizeof(*hwdev), GFP_KERNEL);
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if (!hwdev)
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return -ENOMEM;
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pci_adapter->hwdev = hwdev;
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hwdev->adapter = pci_adapter;
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hwdev->pdev = pci_adapter->pdev;
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hwdev->dev = &pci_adapter->pdev->dev;
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hwdev->func_state = 0;
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spin_lock_init(&hwdev->channel_lock);
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err = hinic3_init_hwif(hwdev);
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if (err) {
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dev_err(hwdev->dev, "Failed to init hwif\n");
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goto err_free_hwdev;
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}
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hwdev->workq = alloc_workqueue(HINIC3_HWDEV_WQ_NAME, WQ_MEM_RECLAIM,
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HINIC3_WQ_MAX_REQ);
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if (!hwdev->workq) {
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dev_err(hwdev->dev, "Failed to alloc hardware workq\n");
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err = -ENOMEM;
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goto err_free_hwif;
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}
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return 0;
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err_free_hwif:
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hinic3_free_hwif(hwdev);
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err_free_hwdev:
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pci_adapter->hwdev = NULL;
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kfree(hwdev);
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return err;
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}
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void hinic3_free_hwdev(struct hinic3_hwdev *hwdev)
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{
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/* Completed by later submission due to LoC limit. */
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destroy_workqueue(hwdev->workq);
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hinic3_free_hwif(hwdev);
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kfree(hwdev);
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}
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void hinic3_set_api_stop(struct hinic3_hwdev *hwdev)
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@@ -10,6 +10,10 @@
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#include "hinic3_hwdev.h"
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#include "hinic3_hwif.h"
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#define HINIC3_HWIF_READY_TIMEOUT 10000
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#define HINIC3_DB_AND_OUTBOUND_EN_TIMEOUT 60000
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#define HINIC3_PCIE_LINK_DOWN 0xFFFFFFFF
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/* config BAR4/5 4MB, DB & DWQE both 2MB */
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#define HINIC3_DB_DWQE_SIZE 0x00400000
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@@ -18,6 +22,41 @@
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#define HINIC3_DWQE_OFFSET 0x00000800
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#define HINIC3_DB_MAX_AREAS (HINIC3_DB_DWQE_SIZE / HINIC3_DB_PAGE_SIZE)
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#define HINIC3_MAX_MSIX_ENTRY 2048
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#define HINIC3_AF0_FUNC_GLOBAL_IDX_MASK GENMASK(11, 0)
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#define HINIC3_AF0_P2P_IDX_MASK GENMASK(16, 12)
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#define HINIC3_AF0_PCI_INTF_IDX_MASK GENMASK(19, 17)
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#define HINIC3_AF0_FUNC_TYPE_MASK BIT(28)
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#define HINIC3_AF0_GET(val, member) \
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FIELD_GET(HINIC3_AF0_##member##_MASK, val)
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#define HINIC3_AF1_AEQS_PER_FUNC_MASK GENMASK(9, 8)
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#define HINIC3_AF1_MGMT_INIT_STATUS_MASK BIT(30)
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#define HINIC3_AF1_GET(val, member) \
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FIELD_GET(HINIC3_AF1_##member##_MASK, val)
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#define HINIC3_AF2_CEQS_PER_FUNC_MASK GENMASK(8, 0)
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#define HINIC3_AF2_IRQS_PER_FUNC_MASK GENMASK(26, 16)
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#define HINIC3_AF2_GET(val, member) \
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FIELD_GET(HINIC3_AF2_##member##_MASK, val)
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#define HINIC3_AF4_DOORBELL_CTRL_MASK BIT(0)
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#define HINIC3_AF4_GET(val, member) \
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FIELD_GET(HINIC3_AF4_##member##_MASK, val)
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#define HINIC3_AF4_SET(val, member) \
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FIELD_PREP(HINIC3_AF4_##member##_MASK, val)
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#define HINIC3_AF5_OUTBOUND_CTRL_MASK BIT(0)
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#define HINIC3_AF5_GET(val, member) \
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FIELD_GET(HINIC3_AF5_##member##_MASK, val)
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#define HINIC3_AF6_PF_STATUS_MASK GENMASK(15, 0)
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#define HINIC3_AF6_FUNC_MAX_SQ_MASK GENMASK(31, 23)
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#define HINIC3_AF6_MSIX_FLEX_EN_MASK BIT(22)
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#define HINIC3_AF6_GET(val, member) \
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FIELD_GET(HINIC3_AF6_##member##_MASK, val)
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#define HINIC3_GET_REG_ADDR(reg) ((reg) & (HINIC3_REGS_FLAG_MASK))
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static void __iomem *hinic3_reg_addr(struct hinic3_hwif *hwif, u32 reg)
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@@ -39,6 +78,116 @@ void hinic3_hwif_write_reg(struct hinic3_hwif *hwif, u32 reg, u32 val)
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iowrite32be(val, addr);
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}
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static enum hinic3_wait_return check_hwif_ready_handler(void *priv_data)
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{
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struct hinic3_hwdev *hwdev = priv_data;
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u32 attr1;
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attr1 = hinic3_hwif_read_reg(hwdev->hwif, HINIC3_CSR_FUNC_ATTR1_ADDR);
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return HINIC3_AF1_GET(attr1, MGMT_INIT_STATUS) ?
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HINIC3_WAIT_PROCESS_CPL : HINIC3_WAIT_PROCESS_WAITING;
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}
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static int wait_hwif_ready(struct hinic3_hwdev *hwdev)
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{
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return hinic3_wait_for_timeout(hwdev, check_hwif_ready_handler,
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HINIC3_HWIF_READY_TIMEOUT,
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USEC_PER_MSEC);
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}
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/* Set attr struct from HW attr values. */
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static void set_hwif_attr(struct hinic3_func_attr *attr, u32 attr0, u32 attr1,
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u32 attr2, u32 attr3, u32 attr6)
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{
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attr->func_global_idx = HINIC3_AF0_GET(attr0, FUNC_GLOBAL_IDX);
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attr->port_to_port_idx = HINIC3_AF0_GET(attr0, P2P_IDX);
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attr->pci_intf_idx = HINIC3_AF0_GET(attr0, PCI_INTF_IDX);
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attr->func_type = HINIC3_AF0_GET(attr0, FUNC_TYPE);
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attr->num_aeqs = BIT(HINIC3_AF1_GET(attr1, AEQS_PER_FUNC));
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attr->num_ceqs = HINIC3_AF2_GET(attr2, CEQS_PER_FUNC);
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attr->num_irqs = HINIC3_AF2_GET(attr2, IRQS_PER_FUNC);
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if (attr->num_irqs > HINIC3_MAX_MSIX_ENTRY)
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attr->num_irqs = HINIC3_MAX_MSIX_ENTRY;
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attr->num_sq = HINIC3_AF6_GET(attr6, FUNC_MAX_SQ);
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attr->msix_flex_en = HINIC3_AF6_GET(attr6, MSIX_FLEX_EN);
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}
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/* Read attributes from HW and set attribute struct. */
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static int init_hwif_attr(struct hinic3_hwdev *hwdev)
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{
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u32 attr0, attr1, attr2, attr3, attr6;
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struct hinic3_hwif *hwif;
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hwif = hwdev->hwif;
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attr0 = hinic3_hwif_read_reg(hwif, HINIC3_CSR_FUNC_ATTR0_ADDR);
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if (attr0 == HINIC3_PCIE_LINK_DOWN)
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return -EFAULT;
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attr1 = hinic3_hwif_read_reg(hwif, HINIC3_CSR_FUNC_ATTR1_ADDR);
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if (attr1 == HINIC3_PCIE_LINK_DOWN)
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return -EFAULT;
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attr2 = hinic3_hwif_read_reg(hwif, HINIC3_CSR_FUNC_ATTR2_ADDR);
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if (attr2 == HINIC3_PCIE_LINK_DOWN)
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return -EFAULT;
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attr3 = hinic3_hwif_read_reg(hwif, HINIC3_CSR_FUNC_ATTR3_ADDR);
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if (attr3 == HINIC3_PCIE_LINK_DOWN)
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return -EFAULT;
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attr6 = hinic3_hwif_read_reg(hwif, HINIC3_CSR_FUNC_ATTR6_ADDR);
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if (attr6 == HINIC3_PCIE_LINK_DOWN)
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return -EFAULT;
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set_hwif_attr(&hwif->attr, attr0, attr1, attr2, attr3, attr6);
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return 0;
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}
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static enum hinic3_doorbell_ctrl hinic3_get_doorbell_ctrl_status(struct hinic3_hwif *hwif)
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{
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u32 attr4 = hinic3_hwif_read_reg(hwif, HINIC3_CSR_FUNC_ATTR4_ADDR);
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return HINIC3_AF4_GET(attr4, DOORBELL_CTRL);
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}
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static enum hinic3_outbound_ctrl hinic3_get_outbound_ctrl_status(struct hinic3_hwif *hwif)
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{
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u32 attr5 = hinic3_hwif_read_reg(hwif, HINIC3_CSR_FUNC_ATTR5_ADDR);
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return HINIC3_AF5_GET(attr5, OUTBOUND_CTRL);
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}
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static int db_area_idx_init(struct hinic3_hwif *hwif, u64 db_base_phy,
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u8 __iomem *db_base, u64 db_dwqe_len)
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{
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struct hinic3_db_area *db_area = &hwif->db_area;
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u32 db_max_areas;
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hwif->db_base_phy = db_base_phy;
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hwif->db_base = db_base;
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hwif->db_dwqe_len = db_dwqe_len;
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db_max_areas = db_dwqe_len > HINIC3_DB_DWQE_SIZE ?
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HINIC3_DB_MAX_AREAS : db_dwqe_len / HINIC3_DB_PAGE_SIZE;
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db_area->db_bitmap_array = bitmap_zalloc(db_max_areas, GFP_KERNEL);
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if (!db_area->db_bitmap_array)
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return -ENOMEM;
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db_area->db_max_areas = db_max_areas;
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spin_lock_init(&db_area->idx_lock);
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return 0;
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}
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static void db_area_idx_free(struct hinic3_db_area *db_area)
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{
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bitmap_free(db_area->db_bitmap_array);
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}
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static int get_db_idx(struct hinic3_hwif *hwif, u32 *idx)
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{
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struct hinic3_db_area *db_area = &hwif->db_area;
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@@ -125,6 +274,15 @@ void hinic3_set_msix_state(struct hinic3_hwdev *hwdev, u16 msix_idx,
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hinic3_hwif_write_reg(hwif, addr, mask_bits);
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}
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static void disable_all_msix(struct hinic3_hwdev *hwdev)
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{
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u16 num_irqs = hwdev->hwif->attr.num_irqs;
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u16 i;
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for (i = 0; i < num_irqs; i++)
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hinic3_set_msix_state(hwdev, i, HINIC3_MSIX_DISABLE);
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}
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void hinic3_msix_intr_clear_resend_bit(struct hinic3_hwdev *hwdev, u16 msix_idx,
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u8 clear_resend_en)
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{
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@@ -161,6 +319,91 @@ void hinic3_set_msix_auto_mask_state(struct hinic3_hwdev *hwdev, u16 msix_idx,
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hinic3_hwif_write_reg(hwif, addr, mask_bits);
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}
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static enum hinic3_wait_return check_db_outbound_enable_handler(void *priv_data)
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{
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enum hinic3_outbound_ctrl outbound_ctrl;
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struct hinic3_hwif *hwif = priv_data;
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enum hinic3_doorbell_ctrl db_ctrl;
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db_ctrl = hinic3_get_doorbell_ctrl_status(hwif);
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outbound_ctrl = hinic3_get_outbound_ctrl_status(hwif);
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if (outbound_ctrl == ENABLE_OUTBOUND && db_ctrl == ENABLE_DOORBELL)
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return HINIC3_WAIT_PROCESS_CPL;
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return HINIC3_WAIT_PROCESS_WAITING;
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}
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static int wait_until_doorbell_and_outbound_enabled(struct hinic3_hwif *hwif)
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{
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return hinic3_wait_for_timeout(hwif, check_db_outbound_enable_handler,
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HINIC3_DB_AND_OUTBOUND_EN_TIMEOUT,
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USEC_PER_MSEC);
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}
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int hinic3_init_hwif(struct hinic3_hwdev *hwdev)
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{
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struct hinic3_pcidev *pci_adapter = hwdev->adapter;
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struct hinic3_hwif *hwif;
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u32 attr1, attr4, attr5;
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int err;
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hwif = kzalloc(sizeof(*hwif), GFP_KERNEL);
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if (!hwif)
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return -ENOMEM;
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hwdev->hwif = hwif;
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hwif->cfg_regs_base = (u8 __iomem *)pci_adapter->cfg_reg_base +
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HINIC3_VF_CFG_REG_OFFSET;
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err = db_area_idx_init(hwif, pci_adapter->db_base_phy,
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pci_adapter->db_base,
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pci_adapter->db_dwqe_len);
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if (err) {
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dev_err(hwdev->dev, "Failed to init db area.\n");
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goto err_free_hwif;
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}
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err = wait_hwif_ready(hwdev);
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if (err) {
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attr1 = hinic3_hwif_read_reg(hwif, HINIC3_CSR_FUNC_ATTR1_ADDR);
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dev_err(hwdev->dev, "Chip status is not ready, attr1:0x%x\n",
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attr1);
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goto err_free_db_area_idx;
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}
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err = init_hwif_attr(hwdev);
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if (err) {
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dev_err(hwdev->dev, "Init hwif attr failed\n");
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goto err_free_db_area_idx;
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}
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err = wait_until_doorbell_and_outbound_enabled(hwif);
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if (err) {
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attr4 = hinic3_hwif_read_reg(hwif, HINIC3_CSR_FUNC_ATTR4_ADDR);
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attr5 = hinic3_hwif_read_reg(hwif, HINIC3_CSR_FUNC_ATTR5_ADDR);
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dev_err(hwdev->dev, "HW doorbell/outbound is disabled, attr4 0x%x attr5 0x%x\n",
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attr4, attr5);
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goto err_free_db_area_idx;
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}
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disable_all_msix(hwdev);
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return 0;
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err_free_db_area_idx:
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db_area_idx_free(&hwif->db_area);
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err_free_hwif:
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kfree(hwif);
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return err;
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}
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void hinic3_free_hwif(struct hinic3_hwdev *hwdev)
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{
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db_area_idx_free(&hwdev->hwif->db_area);
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kfree(hwdev->hwif);
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}
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u16 hinic3_global_func_id(struct hinic3_hwdev *hwdev)
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{
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return hwdev->hwif->attr.func_global_idx;
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@@ -45,6 +45,16 @@ struct hinic3_hwif {
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struct hinic3_func_attr attr;
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};
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enum hinic3_outbound_ctrl {
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ENABLE_OUTBOUND = 0x0,
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DISABLE_OUTBOUND = 0x1,
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};
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enum hinic3_doorbell_ctrl {
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ENABLE_DOORBELL = 0,
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DISABLE_DOORBELL = 1,
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};
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enum hinic3_msix_state {
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HINIC3_MSIX_ENABLE,
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HINIC3_MSIX_DISABLE,
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@@ -62,6 +72,9 @@ int hinic3_alloc_db_addr(struct hinic3_hwdev *hwdev, void __iomem **db_base,
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void __iomem **dwqe_base);
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void hinic3_free_db_addr(struct hinic3_hwdev *hwdev, const u8 __iomem *db_base);
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int hinic3_init_hwif(struct hinic3_hwdev *hwdev);
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void hinic3_free_hwif(struct hinic3_hwdev *hwdev);
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void hinic3_set_msix_state(struct hinic3_hwdev *hwdev, u16 msix_idx,
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enum hinic3_msix_state flag);
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void hinic3_msix_intr_clear_resend_bit(struct hinic3_hwdev *hwdev, u16 msix_idx,
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@@ -8,6 +8,7 @@
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#include "hinic3_hwdev.h"
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#include "hinic3_lld.h"
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#include "hinic3_mgmt.h"
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#include "hinic3_pci_id_tbl.h"
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#define HINIC3_VF_PCI_CFG_REG_BAR 0
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#define HINIC3_PCI_INTR_REG_BAR 2
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@@ -377,7 +378,7 @@ static void hinic3_remove(struct pci_dev *pdev)
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}
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static const struct pci_device_id hinic3_pci_table[] = {
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/* Completed by later submission due to LoC limit. */
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{PCI_VDEVICE(HUAWEI, PCI_DEV_ID_HINIC3_VF), 0},
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{0, 0}
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};
|
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9
drivers/net/ethernet/huawei/hinic3/hinic3_pci_id_tbl.h
Normal file
9
drivers/net/ethernet/huawei/hinic3/hinic3_pci_id_tbl.h
Normal file
@@ -0,0 +1,9 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/* Copyright (c) Huawei Technologies Co., Ltd. 2025. All rights reserved. */
|
||||
|
||||
#ifndef _HINIC3_PCI_ID_TBL_H_
|
||||
#define _HINIC3_PCI_ID_TBL_H_
|
||||
|
||||
#define PCI_DEV_ID_HINIC3_VF 0x375F
|
||||
|
||||
#endif
|
||||
Reference in New Issue
Block a user