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drm/i915: pass dev_priv explicitly to DSPSTRIDE

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Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the DSPSTRIDE register macro.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/4067b3009076492d05e80ae994f9a7bd29b56b2e.1716469091.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
This commit is contained in:
Jani Nikula
2024-05-23 15:59:33 +03:00
parent 26d0ecc758
commit cd962cdb33
5 changed files with 9 additions and 9 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/gpu/drm/i915/display/i9xx_plane.c
View File

@@ -423,7 +423,7 @@ static void i9xx_plane_update_noarm(struct intel_plane *plane,
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
intel_de_write_fw(dev_priv, DSPSTRIDE(i9xx_plane),
intel_de_write_fw(dev_priv, DSPSTRIDE(dev_priv, i9xx_plane),
plane_state->view.color_plane[0].mapping_stride);
if (DISPLAY_VER(dev_priv) < 4) {
@@ -1055,7 +1055,7 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc,
fb->width = REG_FIELD_GET(PIPESRC_WIDTH_MASK, val) + 1;
fb->height = REG_FIELD_GET(PIPESRC_HEIGHT_MASK, val) + 1;
val = intel_de_read(dev_priv, DSPSTRIDE(i9xx_plane));
val = intel_de_read(dev_priv, DSPSTRIDE(dev_priv, i9xx_plane));
fb->pitches[0] = val & 0xffffffc0;
aligned_height = intel_fb_align_height(fb, 0, fb->height);

2
drivers/gpu/drm/i915/display/i9xx_plane_regs.h
View File

@@ -50,7 +50,7 @@
#define DSPLINOFF(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPALINOFF)
#define _DSPASTRIDE 0x70188
#define DSPSTRIDE(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASTRIDE)
#define DSPSTRIDE(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPASTRIDE)
#define _DSPAPOS 0x7018C /* pre-g4x */
#define DSPPOS(plane) _MMIO_PIPE2(dev_priv, plane, _DSPAPOS)

4
drivers/gpu/drm/i915/gvt/cmd_parser.c
View File

@@ -1316,7 +1316,7 @@ static int gen8_decode_mi_display_flip(struct parser_exec_state *s,
if (info->plane == PLANE_A) {
info->ctrl_reg = DSPCNTR(dev_priv, info->pipe);
info->stride_reg = DSPSTRIDE(info->pipe);
info->stride_reg = DSPSTRIDE(dev_priv, info->pipe);
info->surf_reg = DSPSURF(info->pipe);
} else if (info->plane == PLANE_B) {
info->ctrl_reg = SPRCTL(info->pipe);
@@ -1382,7 +1382,7 @@ static int skl_decode_mi_display_flip(struct parser_exec_state *s,
info->async_flip = ((dword2 & GENMASK(1, 0)) == 0x1);
info->ctrl_reg = DSPCNTR(dev_priv, info->pipe);
info->stride_reg = DSPSTRIDE(info->pipe);
info->stride_reg = DSPSTRIDE(dev_priv, info->pipe);
info->surf_reg = DSPSURF(info->pipe);
return 0;

2
drivers/gpu/drm/i915/gvt/fb_decoder.c
View File

@@ -155,7 +155,7 @@ static u32 intel_vgpu_get_stride(struct intel_vgpu *vgpu, int pipe,
{
struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
u32 stride_reg = vgpu_vreg_t(vgpu, DSPSTRIDE(pipe)) & stride_mask;
u32 stride_reg = vgpu_vreg_t(vgpu, DSPSTRIDE(dev_priv, pipe)) & stride_mask;
u32 stride = stride_reg;
if (GRAPHICS_VER(dev_priv) >= 9) {

6
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
View File

@@ -167,7 +167,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
MMIO_D(_MMIO(0x7009c));
MMIO_D(DSPCNTR(dev_priv, PIPE_A));
MMIO_D(DSPADDR(dev_priv, PIPE_A));
MMIO_D(DSPSTRIDE(PIPE_A));
MMIO_D(DSPSTRIDE(dev_priv, PIPE_A));
MMIO_D(DSPPOS(PIPE_A));
MMIO_D(DSPSIZE(PIPE_A));
MMIO_D(DSPSURF(PIPE_A));
@@ -176,7 +176,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
MMIO_D(REG_50080(PIPE_A, PLANE_PRIMARY));
MMIO_D(DSPCNTR(dev_priv, PIPE_B));
MMIO_D(DSPADDR(dev_priv, PIPE_B));
MMIO_D(DSPSTRIDE(PIPE_B));
MMIO_D(DSPSTRIDE(dev_priv, PIPE_B));
MMIO_D(DSPPOS(PIPE_B));
MMIO_D(DSPSIZE(PIPE_B));
MMIO_D(DSPSURF(PIPE_B));
@@ -185,7 +185,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
MMIO_D(REG_50080(PIPE_B, PLANE_PRIMARY));
MMIO_D(DSPCNTR(dev_priv, PIPE_C));
MMIO_D(DSPADDR(dev_priv, PIPE_C));
MMIO_D(DSPSTRIDE(PIPE_C));
MMIO_D(DSPSTRIDE(dev_priv, PIPE_C));
MMIO_D(DSPPOS(PIPE_C));
MMIO_D(DSPSIZE(PIPE_C));
MMIO_D(DSPSURF(PIPE_C));