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ARM: dts: ls1021a: Add memory controller

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The LS1021A has a memory controller that supports EDAC. This commit
adds an entry for it.

Signed-off-by: Patrick Havelange <patrick.havelange@essensium.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Patrick Havelange
2018-12-11 16:48:34 +01:00
committed by Shawn Guo
parent 02f95c3551
commit cd8281acdf
1 changed files with 7 additions and 0 deletions
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7
arch/arm/boot/dts/ls1021a.dtsi
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@@ -125,6 +125,13 @@ soc {
interrupt-parent = <&gic>;
ranges;
ddr: memory-controller@1080000 {
compatible = "fsl,qoriq-memory-controller";
reg = <0x0 0x1080000 0x0 0x1000>;
interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
big-endian;
};
gic: interrupt-controller@1400000 {
compatible = "arm,gic-400", "arm,cortex-a7-gic";
#interrupt-cells = <3>;