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Merge tag 'clk-eyeq7h-7.3' of ssh://github.com/benoitmonin/linux into clk-mobileye
Pull Mobileye clk driver updates from Benoît Monin: - Add support for Mobileye EyeQ7H This patchset brings the support of the Other Logic Blocks (OLB) found in the first Mobileye SoC based on the RISC-V architecture, the EyeQ7H. Despite the change from MIPS to RISC-V, the Other Logic Blocks provide similar clock and reset functions to the controllers of the chip. This series introduces the device tree bindings of the SoC and the necessary changes to the clock and reset eyeq drivers. Signed-off-by: Benoît Monin <benoit.monin@bootlin.com> * tag 'clk-eyeq7h-7.3' of ssh://github.com/benoitmonin/linux: clk: eyeq: Add EyeQ7H compatibles clk: eyeq: Drop PLL, dividers, and fixed factors structs clk: eyeq: Convert clocks declaration to eqc_clock clk: eyeq: Introduce a generic clock type clk: eyeq: Prefix the PLL registers with the PLL type clk: fixed-factor: Export __clk_hw_register_fixed_factor() clk: fixed-factor: Rework initialization with parent clocks reset: eyeq: Add EyeQ7H compatibles dt-bindings: soc: mobileye: Add EyeQ7H OLB
This commit is contained in:
Stephen Boyd
@@ -0,0 +1,192 @@
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/soc/mobileye/mobileye,eyeq7h-olb.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Mobileye EyeQ7H SoC system controller
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maintainers:
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- Benoît Monin <benoit.monin@bootlin.com>
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- Grégory Clement <gregory.clement@bootlin.com>
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- Théo Lebrun <theo.lebrun@bootlin.com>
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- Vladimir Kondratiev <vladimir.kondratiev@mobileye.com>
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description:
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OLB ("Other Logic Block") is a hardware system controller grouping
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smaller blocks. Clocks and resets are generated by those blocks and
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used by internal controllers of the SoC. The EyeQ7H SoC hosts 14
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different OLB.
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properties:
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compatible:
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items:
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- enum:
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- mobileye,eyeq7h-acc0-olb
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- mobileye,eyeq7h-acc1-olb
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- mobileye,eyeq7h-ddr0-olb
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- mobileye,eyeq7h-ddr1-olb
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- mobileye,eyeq7h-east-olb
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- mobileye,eyeq7h-mips0-olb
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- mobileye,eyeq7h-mips1-olb
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- mobileye,eyeq7h-mips2-olb
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- mobileye,eyeq7h-periph-east-olb
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- mobileye,eyeq7h-periph-west-olb
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- mobileye,eyeq7h-south-olb
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- mobileye,eyeq7h-west-olb
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- mobileye,eyeq7h-xnn0-olb
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- mobileye,eyeq7h-xnn1-olb
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- const: syscon
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reg:
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maxItems: 1
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'#reset-cells':
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description:
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First cell is domain and optional if compatible has a single reset domain.
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Second cell is reset index inside that domain.
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enum: [ 1, 2 ]
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'#clock-cells':
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const: 1
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clocks:
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minItems: 1
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maxItems: 2
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clock-names:
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minItems: 1
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maxItems: 2
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required:
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- compatible
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- reg
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- '#clock-cells'
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- clocks
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- clock-names
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allOf:
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- if:
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properties:
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compatible:
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contains:
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enum:
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- mobileye,eyeq7h-ddr0-olb
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- mobileye,eyeq7h-ddr1-olb
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- mobileye,eyeq7h-mips0-olb
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- mobileye,eyeq7h-mips1-olb
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- mobileye,eyeq7h-mips2-olb
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- mobileye,eyeq7h-periph-east-olb
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- mobileye,eyeq7h-south-olb
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then:
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properties:
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clocks:
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items:
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- description: Reference input clock.
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clock-names:
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items:
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- const: ref
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- if:
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properties:
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compatible:
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contains:
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enum:
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- mobileye,eyeq7h-east-olb
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- mobileye,eyeq7h-west-olb
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then:
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properties:
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clocks:
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items:
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- description: Reference input clock from the main oscillator.
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- description: 100MHz reference input clock.
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clock-names:
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items:
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- const: ref
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- const: ref_100p0
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- if:
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properties:
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compatible:
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contains:
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enum:
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- mobileye,eyeq7h-acc0-olb
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- mobileye,eyeq7h-acc1-olb
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- mobileye,eyeq7h-periph-west-olb
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- mobileye,eyeq7h-xnn0-olb
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- mobileye,eyeq7h-xnn1-olb
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then:
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properties:
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clocks:
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items:
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- description: 100MHz reference input clock.
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- description: 106.6MHz reference input clock.
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clock-names:
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items:
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- const: ref_100p0
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- const: ref_106p6
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|
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- if:
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properties:
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compatible:
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contains:
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enum:
|
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- mobileye,eyeq7h-ddr0-olb
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- mobileye,eyeq7h-ddr1-olb
|
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- mobileye,eyeq7h-east-olb
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- mobileye,eyeq7h-periph-east-olb
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- mobileye,eyeq7h-periph-west-olb
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- mobileye,eyeq7h-west-olb
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then:
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properties:
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'#reset-cells':
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const: 1
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required:
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- '#reset-cells'
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|
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- if:
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properties:
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compatible:
|
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contains:
|
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enum:
|
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- mobileye,eyeq7h-acc0-olb
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- mobileye,eyeq7h-acc1-olb
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- mobileye,eyeq7h-south-olb
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- mobileye,eyeq7h-xnn0-olb
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- mobileye,eyeq7h-xnn1-olb
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then:
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properties:
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'#reset-cells':
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const: 2
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required:
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- '#reset-cells'
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|
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- if:
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properties:
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compatible:
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contains:
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enum:
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- mobileye,eyeq7h-mips0-olb
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- mobileye,eyeq7h-mips1-olb
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- mobileye,eyeq7h-mips2-olb
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then:
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properties:
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'#reset-cells': false
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additionalProperties: false
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examples:
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- |
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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system-controller0@45000000 {
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compatible = "mobileye,eyeq7h-acc0-olb", "syscon";
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reg = <0x0 0x45000000 0x0 0x1000>;
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#reset-cells = <2>;
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#clock-cells = <1>;
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clocks = <&olb_south 7>, <&olb_east 5>;
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clock-names = "ref_100p0", "ref_106p6";
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};
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};
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File diff suppressed because it is too large
Load Diff
@@ -36,10 +36,14 @@ static int clk_factor_determine_rate(struct clk_hw *hw,
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struct clk_fixed_factor *fix = to_clk_fixed_factor(hw);
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if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) {
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struct clk_hw *parent_hw = clk_hw_get_parent(hw);
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unsigned long best_parent;
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if (!parent_hw)
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return -EINVAL;
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best_parent = (req->rate / fix->mult) * fix->div;
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req->best_parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw), best_parent);
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req->best_parent_rate = clk_hw_round_rate(parent_hw, best_parent);
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}
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req->rate = (req->best_parent_rate / fix->div) * fix->mult;
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@@ -90,7 +94,7 @@ static void devm_clk_hw_register_fixed_factor_release(struct device *dev, void *
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clk_hw_unregister(&fix->hw);
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}
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static struct clk_hw *
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struct clk_hw *
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__clk_hw_register_fixed_factor(struct device *dev, struct device_node *np,
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const char *name, const char *parent_name,
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const struct clk_hw *parent_hw, const struct clk_parent_data *pdata,
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@@ -124,13 +128,13 @@ __clk_hw_register_fixed_factor(struct device *dev, struct device_node *np,
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init.name = name;
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init.ops = &clk_fixed_factor_ops;
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init.flags = flags;
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if (parent_name)
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init.parent_names = &parent_name;
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else if (parent_hw)
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init.parent_hws = &parent_hw;
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init.parent_names = parent_name ? &parent_name : NULL;
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init.parent_hws = parent_hw ? &parent_hw : NULL;
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init.parent_data = pdata;
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if (parent_name || parent_hw || pdata)
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init.num_parents = 1;
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else
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init.parent_data = pdata;
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init.num_parents = 1;
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init.num_parents = 0;
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hw = &fix->hw;
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if (dev)
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@@ -148,6 +152,7 @@ __clk_hw_register_fixed_factor(struct device *dev, struct device_node *np,
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return hw;
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}
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EXPORT_SYMBOL_GPL(__clk_hw_register_fixed_factor);
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/**
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* devm_clk_hw_register_fixed_factor_index - Register a fixed factor clock with
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@@ -173,52 +178,6 @@ struct clk_hw *devm_clk_hw_register_fixed_factor_index(struct device *dev,
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}
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EXPORT_SYMBOL_GPL(devm_clk_hw_register_fixed_factor_index);
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/**
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* devm_clk_hw_register_fixed_factor_parent_hw - Register a fixed factor clock with
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* pointer to parent clock
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* @dev: device that is registering this clock
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* @name: name of this clock
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* @parent_hw: pointer to parent clk
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* @flags: fixed factor flags
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* @mult: multiplier
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* @div: divider
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*
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* Return: Pointer to fixed factor clk_hw structure that was registered or
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* an error pointer.
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*/
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struct clk_hw *devm_clk_hw_register_fixed_factor_parent_hw(struct device *dev,
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const char *name, const struct clk_hw *parent_hw,
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unsigned long flags, unsigned int mult, unsigned int div)
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{
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const struct clk_parent_data pdata = { .index = -1 };
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return __clk_hw_register_fixed_factor(dev, NULL, name, NULL, parent_hw,
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&pdata, flags, mult, div, 0, 0, true);
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}
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EXPORT_SYMBOL_GPL(devm_clk_hw_register_fixed_factor_parent_hw);
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struct clk_hw *clk_hw_register_fixed_factor_parent_hw(struct device *dev,
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const char *name, const struct clk_hw *parent_hw,
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unsigned long flags, unsigned int mult, unsigned int div)
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{
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const struct clk_parent_data pdata = { .index = -1 };
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return __clk_hw_register_fixed_factor(dev, NULL, name, NULL, parent_hw,
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&pdata, flags, mult, div, 0, 0, false);
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}
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EXPORT_SYMBOL_GPL(clk_hw_register_fixed_factor_parent_hw);
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struct clk_hw *clk_hw_register_fixed_factor(struct device *dev,
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const char *name, const char *parent_name, unsigned long flags,
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unsigned int mult, unsigned int div)
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{
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const struct clk_parent_data pdata = { .index = -1 };
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return __clk_hw_register_fixed_factor(dev, NULL, name, parent_name, NULL,
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&pdata, flags, mult, div, 0, 0, false);
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}
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EXPORT_SYMBOL_GPL(clk_hw_register_fixed_factor);
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struct clk_hw *clk_hw_register_fixed_factor_fwname(struct device *dev,
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struct device_node *np, const char *name, const char *fw_name,
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unsigned long flags, unsigned int mult, unsigned int div)
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@@ -292,17 +251,6 @@ void clk_hw_unregister_fixed_factor(struct clk_hw *hw)
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}
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EXPORT_SYMBOL_GPL(clk_hw_unregister_fixed_factor);
|
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|
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struct clk_hw *devm_clk_hw_register_fixed_factor(struct device *dev,
|
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const char *name, const char *parent_name, unsigned long flags,
|
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unsigned int mult, unsigned int div)
|
||||
{
|
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const struct clk_parent_data pdata = { .index = -1 };
|
||||
|
||||
return __clk_hw_register_fixed_factor(dev, NULL, name, parent_name, NULL,
|
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&pdata, flags, mult, div, 0, 0, true);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(devm_clk_hw_register_fixed_factor);
|
||||
|
||||
struct clk_hw *devm_clk_hw_register_fixed_factor_fwname(struct device *dev,
|
||||
struct device_node *np, const char *name, const char *fw_name,
|
||||
unsigned long flags, unsigned int mult, unsigned int div)
|
||||
|
||||
@@ -1,10 +1,11 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Reset driver for the Mobileye EyeQ5, EyeQ6L and EyeQ6H platforms.
|
||||
* Reset driver for the Mobileye EyeQ5, EyeQ6L, EyeQ6H and EyeQ7H platforms.
|
||||
*
|
||||
* Controllers live in a shared register region called OLB. EyeQ5 and EyeQ6L
|
||||
* have a single OLB instance for a single reset controller. EyeQ6H has seven
|
||||
* OLB instances; three host reset controllers.
|
||||
* OLB instances; three host reset controllers. EyeQ7H has fourteen OLB instances;
|
||||
* eleven host reset controllers.
|
||||
*
|
||||
* Each reset controller has one or more domain. Domains are of a given type
|
||||
* (see enum eqr_domain_type), with a valid offset mask (up to 32 resets per
|
||||
@@ -73,6 +74,43 @@
|
||||
* 9. PMA0 10. PMA1 11. MPC0 12. MPC1
|
||||
* 13. MPC2 14. MPC3 15. PERIPH
|
||||
*
|
||||
* Known resets in EyeQ7H acc domain 0 (type EQR_EYEQ7H_ACRP)
|
||||
* 0. VMP0 1. XVMP1 2. VMP2 3. VMP3
|
||||
* 4. MPC0 5. MPC1 6. PMA0 7. PMA1
|
||||
*
|
||||
* Known resets in EyeQ7H acc domain 1 (type EQR_EYEQ7H_ACC)
|
||||
* 0. NCORE0 1. NCORE1 2. NCORE0_M 3. NCORE1_M
|
||||
* 4. NCORE_NOC 5. VMP_NOC 6. MPC_NOC 7. PMA_NOC
|
||||
*
|
||||
* Known resets in EyeQ7H ddr (type EQR_EYEQ7H_CFG)
|
||||
* 0. APB 1. DMI 2. DFI 3. PHY_SMS
|
||||
* 4. CTL_SMS
|
||||
*
|
||||
* Known resets in EyeQ7H east (type EQR_EYEQ7H_CFG)
|
||||
* 0. ISP 1. VEU 2. LBIST
|
||||
*
|
||||
* Known resets in EyeQ7H periph (type EQR_EYEQ6H_SARCR)
|
||||
* 0. gpio 1.EXT TIMER 2.UART 3. SPI
|
||||
* 4. I2C0 5. I2C1 6.I2C2 7. I2S
|
||||
*
|
||||
* Known resets in EyeQ7H south domain 0 (type EQR_EYEQ7H_CFG)
|
||||
* 0. PCI_PHY 1. PCI_CTL 2. S_NOC 3. GBE_PHY
|
||||
* 4. GBE_CTL
|
||||
*
|
||||
* Known resets in EyeQ7H south domain 1 (type EQR_EYEQ7H_CFG)
|
||||
* 0. XSPI 1. UFS 2. VDIO
|
||||
*
|
||||
* Known resets in EyeQ7H west (type EQR_EYEQ7H_CFG)
|
||||
* 0. GPU 1. CAU 2. LBIST 3. GPU_LBIST
|
||||
*
|
||||
* Known resets in EyeQ7H xnn domain 0 (type EQR_EYEQ7H_ACRP)
|
||||
* 0. XNN0 1. XNN1 2.XNN2
|
||||
*
|
||||
* Known resets in EyeQ7H xnn domain 1 (type EQR_EYEQ7H_ACC)
|
||||
* 0. XNN0 1. XNN1 2. XNN2 3. XNN3
|
||||
* 4. NCORE 5. L2_0 6. L2_1 7. SMS_0
|
||||
* 8. SMS_1
|
||||
*
|
||||
* Abbreviations:
|
||||
* - PMA: Programmable Macro Array
|
||||
* - MPC: Multi-threaded Processing Clusters
|
||||
@@ -113,6 +151,11 @@ enum eqr_domain_type {
|
||||
EQR_EYEQ5_ACRP,
|
||||
EQR_EYEQ5_PCIE,
|
||||
EQR_EYEQ6H_SARCR,
|
||||
EQR_EYEQ7H_ACC,
|
||||
EQR_EYEQ7H_ACRP,
|
||||
EQR_EYEQ7H_CFG,
|
||||
|
||||
EQR_NB_DOM_TYPES /* number of domain types, keep at the end */
|
||||
};
|
||||
|
||||
/*
|
||||
@@ -137,16 +180,34 @@ enum eqr_domain_type {
|
||||
#define EQR_EYEQ6H_SARCR_RST_STATUS (0x008)
|
||||
#define EQR_EYEQ6H_SARCR_CLK_REQUEST (0x00C)
|
||||
|
||||
/*
|
||||
* Domain type EQR_EYEQ7H_ACC register offsets.
|
||||
*/
|
||||
#define EQR_EYEQ7H_ACC_CLK_EN (0x000)
|
||||
#define EQR_EYEQ7H_ACC_RST_EN (0x004)
|
||||
|
||||
/*
|
||||
* Domain type EQR_EYEQ7H_ACRP register masks.
|
||||
* Registers are: base + 4 * offset.
|
||||
*/
|
||||
#define EQR_EYEQ7H_ACRP_PD_REQ BIT(0)
|
||||
#define EQR_EYEQ7H_ACRP_MBIST_CFG GENMASK(3, 1)
|
||||
#define EQR_EYEQ7H_ACRP_ST_POWER_DOWN BIT(13)
|
||||
#define EQR_EYEQ7H_ACRP_ST_ACTIVE BIT(14)
|
||||
|
||||
struct eqr_busy_wait_timings {
|
||||
unsigned long sleep_us;
|
||||
unsigned long timeout_us;
|
||||
};
|
||||
|
||||
static const struct eqr_busy_wait_timings eqr_timings[] = {
|
||||
static const struct eqr_busy_wait_timings eqr_timings[EQR_NB_DOM_TYPES] = {
|
||||
[EQR_EYEQ5_SARCR] = {1, 10},
|
||||
[EQR_EYEQ5_ACRP] = {1, 40 * USEC_PER_MSEC}, /* LBIST implies long timeout. */
|
||||
/* EQR_EYEQ5_PCIE does no busy waiting. */
|
||||
[EQR_EYEQ6H_SARCR] = {1, 400},
|
||||
/* EQR_EYEQ7H_ACC does no busy waiting. */
|
||||
[EQR_EYEQ7H_ACRP] = {1, 40 * USEC_PER_MSEC},
|
||||
/* EQR_EYEQ7H_CFG does no busy waiting. */
|
||||
};
|
||||
|
||||
#define EQR_MAX_DOMAIN_COUNT 3
|
||||
@@ -220,10 +281,6 @@ static int eqr_busy_wait_locked(struct eqr_private *priv, struct device *dev,
|
||||
sleep_us, timeout_us);
|
||||
break;
|
||||
|
||||
case EQR_EYEQ5_PCIE:
|
||||
ret = 0; /* No busy waiting. */
|
||||
break;
|
||||
|
||||
case EQR_EYEQ6H_SARCR:
|
||||
/*
|
||||
* Wait until both bits change:
|
||||
@@ -240,6 +297,23 @@ static int eqr_busy_wait_locked(struct eqr_private *priv, struct device *dev,
|
||||
&rst_status, &clk_status);
|
||||
break;
|
||||
|
||||
case EQR_EYEQ7H_ACRP:
|
||||
reg = base + 4 * offset;
|
||||
if (assert)
|
||||
mask = EQR_EYEQ7H_ACRP_ST_POWER_DOWN;
|
||||
else
|
||||
mask = EQR_EYEQ7H_ACRP_ST_ACTIVE;
|
||||
|
||||
ret = readl_poll_timeout(reg, val, !!(val & mask),
|
||||
sleep_us, timeout_us);
|
||||
break;
|
||||
|
||||
case EQR_EYEQ5_PCIE:
|
||||
case EQR_EYEQ7H_ACC:
|
||||
case EQR_EYEQ7H_CFG:
|
||||
ret = 0; /* No busy waiting. */
|
||||
break;
|
||||
|
||||
default:
|
||||
WARN_ON(1);
|
||||
ret = -EINVAL;
|
||||
@@ -284,6 +358,28 @@ static void eqr_assert_locked(struct eqr_private *priv, u32 domain, u32 offset)
|
||||
writel(val, base + EQR_EYEQ6H_SARCR_CLK_REQUEST);
|
||||
break;
|
||||
|
||||
case EQR_EYEQ7H_ACC:
|
||||
/* RST_REQUEST and CLK_REQUEST must be kept in sync. */
|
||||
val = readl(base + EQR_EYEQ7H_ACC_RST_EN);
|
||||
val &= ~BIT(offset);
|
||||
writel(val, base + EQR_EYEQ7H_ACC_RST_EN);
|
||||
writel(val, base + EQR_EYEQ7H_ACC_CLK_EN);
|
||||
break;
|
||||
|
||||
case EQR_EYEQ7H_ACRP:
|
||||
/* set powerdown and leave MBIST bits at zero */
|
||||
reg = base + 4 * offset;
|
||||
val = readl(reg) & ~EQR_EYEQ7H_ACRP_MBIST_CFG;
|
||||
writel(val | EQR_EYEQ7H_ACRP_PD_REQ, reg);
|
||||
break;
|
||||
|
||||
case EQR_EYEQ7H_CFG:
|
||||
/* clear clock enable and NRESET bits */
|
||||
val = readl(base);
|
||||
val &= ~GENMASK(2 * offset + 1, 2 * offset);
|
||||
writel(val, base);
|
||||
break;
|
||||
|
||||
default:
|
||||
WARN_ON(1);
|
||||
break;
|
||||
@@ -338,6 +434,28 @@ static void eqr_deassert_locked(struct eqr_private *priv, u32 domain,
|
||||
writel(val, base + EQR_EYEQ6H_SARCR_CLK_REQUEST);
|
||||
break;
|
||||
|
||||
case EQR_EYEQ7H_ACC:
|
||||
/* RST_REQUEST and CLK_REQUEST must be kept in sync. */
|
||||
val = readl(base + EQR_EYEQ7H_ACC_RST_EN);
|
||||
val |= BIT(offset);
|
||||
writel(val, base + EQR_EYEQ7H_ACC_RST_EN);
|
||||
writel(val, base + EQR_EYEQ7H_ACC_CLK_EN);
|
||||
break;
|
||||
|
||||
case EQR_EYEQ7H_ACRP:
|
||||
/* clear powerdown and leave MBIST bits at zero */
|
||||
reg = base + 4 * offset;
|
||||
val = readl(reg) & ~EQR_EYEQ7H_ACRP_MBIST_CFG;
|
||||
writel(val & ~EQR_EYEQ7H_ACRP_PD_REQ, reg);
|
||||
break;
|
||||
|
||||
case EQR_EYEQ7H_CFG:
|
||||
/* set clock enable and NRESET bits */
|
||||
val = readl(base);
|
||||
val |= GENMASK(2 * offset + 1, 2 * offset);
|
||||
writel(val, base);
|
||||
break;
|
||||
|
||||
default:
|
||||
WARN_ON(1);
|
||||
break;
|
||||
@@ -384,6 +502,14 @@ static int eqr_status(struct reset_controller_dev *rcdev, unsigned long id)
|
||||
case EQR_EYEQ6H_SARCR:
|
||||
reg = base + EQR_EYEQ6H_SARCR_RST_STATUS;
|
||||
return !(readl(reg) & BIT(offset));
|
||||
case EQR_EYEQ7H_ACC:
|
||||
reg = base + EQR_EYEQ7H_ACC_RST_EN;
|
||||
return !(readl(reg) & BIT(offset));
|
||||
case EQR_EYEQ7H_ACRP:
|
||||
reg = base + 4 * offset;
|
||||
return !(readl(reg) & EQR_EYEQ7H_ACRP_ST_ACTIVE);
|
||||
case EQR_EYEQ7H_CFG:
|
||||
return !(readl(base) & BIT(2 * offset));
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
@@ -557,6 +683,113 @@ static const struct eqr_match_data eqr_eyeq6h_acc_data = {
|
||||
.domains = eqr_eyeq6h_acc_domains,
|
||||
};
|
||||
|
||||
static const struct eqr_domain_descriptor eqr_eyeq7h_acc_domains[] = {
|
||||
{
|
||||
.type = EQR_EYEQ7H_ACRP,
|
||||
.valid_mask = 0xFF,
|
||||
.offset = 0x000,
|
||||
},
|
||||
{
|
||||
.type = EQR_EYEQ7H_ACC,
|
||||
.valid_mask = 0xFF,
|
||||
.offset = 0x060,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct eqr_match_data eqr_eyeq7h_acc_data = {
|
||||
.domain_count = ARRAY_SIZE(eqr_eyeq7h_acc_domains),
|
||||
.domains = eqr_eyeq7h_acc_domains,
|
||||
};
|
||||
|
||||
static const struct eqr_domain_descriptor eqr_eyeq7h_ddr_domains[] = {
|
||||
{
|
||||
.type = EQR_EYEQ7H_CFG,
|
||||
.valid_mask = 0x1F,
|
||||
.offset = 0x008,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct eqr_match_data eqr_eyeq7h_ddr_data = {
|
||||
.domain_count = ARRAY_SIZE(eqr_eyeq7h_ddr_domains),
|
||||
.domains = eqr_eyeq7h_ddr_domains,
|
||||
};
|
||||
|
||||
static const struct eqr_domain_descriptor eqr_eyeq7h_east_domains[] = {
|
||||
{
|
||||
.type = EQR_EYEQ7H_CFG,
|
||||
.valid_mask = 0x7,
|
||||
.offset = 0x060,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct eqr_match_data eqr_eyeq7h_east_data = {
|
||||
.domain_count = ARRAY_SIZE(eqr_eyeq7h_east_domains),
|
||||
.domains = eqr_eyeq7h_east_domains,
|
||||
};
|
||||
|
||||
/* Periph OLBs each have an instance. */
|
||||
static const struct eqr_domain_descriptor eqr_eyeq7h_per_domains[] = {
|
||||
{
|
||||
.type = EQR_EYEQ6H_SARCR,
|
||||
.valid_mask = 0xFF,
|
||||
.offset = 0x030,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct eqr_match_data eqr_eyeq7h_per_data = {
|
||||
.domain_count = ARRAY_SIZE(eqr_eyeq7h_per_domains),
|
||||
.domains = eqr_eyeq7h_per_domains,
|
||||
};
|
||||
|
||||
static const struct eqr_domain_descriptor eqr_eyeq7h_south_domains[] = {
|
||||
{
|
||||
.type = EQR_EYEQ7H_CFG,
|
||||
.valid_mask = 0x1F,
|
||||
.offset = 0x070,
|
||||
},
|
||||
{
|
||||
.type = EQR_EYEQ7H_CFG,
|
||||
.valid_mask = 0x7,
|
||||
.offset = 0x074,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct eqr_match_data eqr_eyeq7h_south_data = {
|
||||
.domain_count = ARRAY_SIZE(eqr_eyeq7h_south_domains),
|
||||
.domains = eqr_eyeq7h_south_domains,
|
||||
};
|
||||
|
||||
static const struct eqr_domain_descriptor eqr_eyeq7h_west_domains[] = {
|
||||
{
|
||||
.type = EQR_EYEQ7H_CFG,
|
||||
.valid_mask = 0xf,
|
||||
.offset = 0x068,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct eqr_match_data eqr_eyeq7h_west_data = {
|
||||
.domain_count = ARRAY_SIZE(eqr_eyeq7h_west_domains),
|
||||
.domains = eqr_eyeq7h_west_domains,
|
||||
};
|
||||
|
||||
static const struct eqr_domain_descriptor eqr_eyeq7h_xnn_domains[] = {
|
||||
{
|
||||
.type = EQR_EYEQ7H_ACRP,
|
||||
.valid_mask = 0x7,
|
||||
.offset = 0x000,
|
||||
},
|
||||
{
|
||||
.type = EQR_EYEQ7H_ACC,
|
||||
.valid_mask = 0x1FF,
|
||||
.offset = 0x060,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct eqr_match_data eqr_eyeq7h_xnn_data = {
|
||||
.domain_count = ARRAY_SIZE(eqr_eyeq7h_xnn_domains),
|
||||
.domains = eqr_eyeq7h_xnn_domains,
|
||||
};
|
||||
|
||||
/*
|
||||
* Table describes OLB system-controller compatibles.
|
||||
* It does not get used to match against devicetree node.
|
||||
@@ -568,15 +801,35 @@ static const struct of_device_id eqr_match_table[] = {
|
||||
{ .compatible = "mobileye,eyeq6h-west-olb", .data = &eqr_eyeq6h_we_data },
|
||||
{ .compatible = "mobileye,eyeq6h-east-olb", .data = &eqr_eyeq6h_we_data },
|
||||
{ .compatible = "mobileye,eyeq6h-acc-olb", .data = &eqr_eyeq6h_acc_data },
|
||||
{ .compatible = "mobileye,eyeq7h-acc0-olb", .data = &eqr_eyeq7h_acc_data },
|
||||
{ .compatible = "mobileye,eyeq7h-acc1-olb", .data = &eqr_eyeq7h_acc_data },
|
||||
{ .compatible = "mobileye,eyeq7h-ddr0-olb", .data = &eqr_eyeq7h_ddr_data },
|
||||
{ .compatible = "mobileye,eyeq7h-ddr1-olb", .data = &eqr_eyeq7h_ddr_data },
|
||||
{ .compatible = "mobileye,eyeq7h-east-olb", .data = &eqr_eyeq7h_east_data },
|
||||
{ .compatible = "mobileye,eyeq7h-periph-east-olb", .data = &eqr_eyeq7h_per_data },
|
||||
{ .compatible = "mobileye,eyeq7h-periph-west-olb", .data = &eqr_eyeq7h_per_data },
|
||||
{ .compatible = "mobileye,eyeq7h-south-olb", .data = &eqr_eyeq7h_south_data },
|
||||
{ .compatible = "mobileye,eyeq7h-west-olb", .data = &eqr_eyeq7h_west_data },
|
||||
{ .compatible = "mobileye,eyeq7h-xnn0-olb", .data = &eqr_eyeq7h_xnn_data },
|
||||
{ .compatible = "mobileye,eyeq7h-xnn1-olb", .data = &eqr_eyeq7h_xnn_data },
|
||||
{}
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, eqr_match_table);
|
||||
|
||||
static const struct auxiliary_device_id eqr_id_table[] = {
|
||||
{ .name = "clk_eyeq.reset" },
|
||||
{ .name = "clk_eyeq.reset_west" },
|
||||
{ .name = "clk_eyeq.reset_east" },
|
||||
{ .name = "clk_eyeq.reset_acc" },
|
||||
{ .name = "clk_eyeq.reset_acc0" },
|
||||
{ .name = "clk_eyeq.reset_acc1" },
|
||||
{ .name = "clk_eyeq.reset_ddr0" },
|
||||
{ .name = "clk_eyeq.reset_ddr1" },
|
||||
{ .name = "clk_eyeq.reset_east" },
|
||||
{ .name = "clk_eyeq.reset_periph_east" },
|
||||
{ .name = "clk_eyeq.reset_periph_west" },
|
||||
{ .name = "clk_eyeq.reset_south" },
|
||||
{ .name = "clk_eyeq.reset_west" },
|
||||
{ .name = "clk_eyeq.reset_xnn0" },
|
||||
{ .name = "clk_eyeq.reset_xnn1" },
|
||||
{}
|
||||
};
|
||||
MODULE_DEVICE_TABLE(auxiliary, eqr_id_table);
|
||||
|
||||
119
include/dt-bindings/clock/mobileye,eyeq7h-clk.h
Normal file
119
include/dt-bindings/clock/mobileye,eyeq7h-clk.h
Normal file
@@ -0,0 +1,119 @@
|
||||
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
||||
/*
|
||||
* Copyright (C) 2025 Mobileye Vision Technologies Ltd.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLOCK_MOBILEYE_EYEQ7H_CLK_H
|
||||
#define _DT_BINDINGS_CLOCK_MOBILEYE_EYEQ7H_CLK_H
|
||||
|
||||
/* ACC0 and ACC1 OLBs PLL and dividers */
|
||||
#define EQ7HC_ACC_PLL_VMP 0
|
||||
#define EQ7HC_ACC_PLL_MPC 1
|
||||
#define EQ7HC_ACC_PLL_PMA 2
|
||||
#define EQ7HC_ACC_PLL_NOC 3
|
||||
#define EQ7HC_ACC_DIV_PMA 4
|
||||
#define EQ7HC_ACC_DIV_NCORE 5
|
||||
#define EQ7HC_ACC_DIV_CFG 6
|
||||
|
||||
/* DDR0 and DDR1 OLBs PLL and dividers */
|
||||
#define EQ7HC_DDR_PLL 0
|
||||
#define EQ7HC_DDR_DIV_APB 1
|
||||
#define EQ7HC_DDR_DIV_PLLREF 2
|
||||
#define EQ7HC_DDR_DIV_DFI 3
|
||||
|
||||
/* east OLB PLL and dividers */
|
||||
#define EQ7HC_EAST_PLL_106P6 0
|
||||
#define EQ7HC_EAST_DIV_REF_106P6 1
|
||||
#define EQ7HC_EAST_PLL_NOC 2
|
||||
#define EQ7HC_EAST_PLL_ISP 3
|
||||
#define EQ7HC_EAST_PLL_VEU 4
|
||||
#define EQ7HC_EAST_DIV_REF_DDR_PHY 5
|
||||
#define EQ7HC_EAST_DIV_CORE 6
|
||||
#define EQ7HC_EAST_DIV_CORE_MBIST 7
|
||||
#define EQ7HC_EAST_DIV_ISRAM_MBIST 8
|
||||
#define EQ7HC_EAST_DIV_CFG 9
|
||||
#define EQ7HC_EAST_DIV_VEU_CORE 10
|
||||
#define EQ7HC_EAST_DIV_VEU_MBIST 11
|
||||
#define EQ7HC_EAST_DIV_VEU_OCP 12
|
||||
#define EQ7HC_EAST_DIV_LBITS 13
|
||||
#define EQ7HC_EAST_DIV_ISP0_CORE 14
|
||||
|
||||
/* MIPS0, MIPS1 and MIPS2 OLBs PLL and dividers */
|
||||
#define EQ7HC_MIPS_PLL_CPU 0
|
||||
#define EQ7HC_MIPS_DIV_CM 1
|
||||
|
||||
/* periph east OLB PLL and dividers */
|
||||
#define EQ7HC_PERIPH_EAST_PLL_PER 0
|
||||
#define EQ7HC_PERIPH_EAST_DIV_PER 1
|
||||
|
||||
/* periph west OLB PLL and dividers */
|
||||
#define EQ7HC_PERIPH_WEST_PLL_PER 0
|
||||
#define EQ7HC_PERIPH_WEST_PLL_I2S 1
|
||||
#define EQ7HC_PERIPH_WEST_DIV_PER 2
|
||||
#define EQ7HC_PERIPH_WEST_DIV_I2S 3
|
||||
|
||||
/* south OLB PLL and dividers */
|
||||
#define EQ7HC_SOUTH_PLL_100P0 0
|
||||
#define EQ7HC_SOUTH_DIV_REF_100P0 1
|
||||
#define EQ7HC_SOUTH_PLL_XSPI 2
|
||||
#define EQ7HC_SOUTH_PLL_VDIO 3
|
||||
#define EQ7HC_SOUTH_PLL_PER 4
|
||||
#define EQ7HC_SOUTH_DIV_VDO_DSI_SYS 5
|
||||
#define EQ7HC_SOUTH_DIV_PMA_CMN_REF 6
|
||||
#define EQ7HC_SOUTH_DIV_REF_UFS 7
|
||||
#define EQ7HC_SOUTH_DIV_XSPI_SYS 8
|
||||
#define EQ7HC_SOUTH_DIV_XSPI_MBIST 9
|
||||
#define EQ7HC_SOUTH_DIV_NOC_S 10
|
||||
#define EQ7HC_SOUTH_DIV_PCIE_SYS 11
|
||||
#define EQ7HC_SOUTH_DIV_PCIE_SYS_MBIST 12
|
||||
#define EQ7HC_SOUTH_DIV_PCIE_GBE_PHY 13
|
||||
#define EQ7HC_SOUTH_DIV_UFS_CORE 14
|
||||
#define EQ7HC_SOUTH_DIV_UFS_SMS 15
|
||||
#define EQ7HC_SOUTH_DIV_UFS_ROM_SMS 16
|
||||
#define EQ7HC_SOUTH_DIV_ETH_SYS 17
|
||||
#define EQ7HC_SOUTH_DIV_ETH_MBIST 18
|
||||
#define EQ7HC_SOUTH_DIV_CFG_S 19
|
||||
#define EQ7HC_SOUTH_DIV_TSU 20
|
||||
#define EQ7HC_SOUTH_DIV_VDIO 21
|
||||
#define EQ7HC_SOUTH_DIV_VDIO_CORE 22
|
||||
#define EQ7HC_SOUTH_DIV_VDIO_CORE_MBIST 23
|
||||
#define EQ7HC_SOUTH_DIV_VDO_CORE_MBIST 24
|
||||
#define EQ7HC_SOUTH_DIV_VDO_P 25
|
||||
#define EQ7HC_SOUTH_DIV_VDIO_CFG 26
|
||||
#define EQ7HC_SOUTH_DIV_VDIO_TXCLKESC 27
|
||||
|
||||
/* west OLB PLL and dividers */
|
||||
#define EQ7HC_WEST_PLL_106P6 0
|
||||
#define EQ7HC_WEST_DIV_REF_106P6 1
|
||||
#define EQ7HC_WEST_PLL_NOC 2
|
||||
#define EQ7HC_WEST_PLL_GPU 3
|
||||
#define EQ7HC_WEST_PLL_SSI 4
|
||||
#define EQ7HC_WEST_DIV_GPU 5
|
||||
#define EQ7HC_WEST_DIV_GPU_MBIST 6
|
||||
#define EQ7HC_WEST_DIV_LBITS 7
|
||||
#define EQ7HC_WEST_DIV_MIPS_TIMER 8
|
||||
#define EQ7HC_WEST_DIV_SSI_CORE 9
|
||||
#define EQ7HC_WEST_DIV_SSI_CORE_MBIST 10
|
||||
#define EQ7HC_WEST_DIV_SSI_ROM 11
|
||||
#define EQ7HC_WEST_DIV_SSI_ROM_MBIST 12
|
||||
#define EQ7HC_WEST_DIV_REF_DDR_PHY 13
|
||||
#define EQ7HC_WEST_DIV_CORE 14
|
||||
#define EQ7HC_WEST_DIV_CORE_MBIST 15
|
||||
#define EQ7HC_WEST_DIV_CFG 16
|
||||
#define EQ7HC_WEST_DIV_CAU 17
|
||||
#define EQ7HC_WEST_DIV_CAU_MBIST 18
|
||||
|
||||
/* XNN0 and XNN1 OLBs PLL and dividers */
|
||||
#define EQ7HC_XNN_PLL_XNN0 0
|
||||
#define EQ7HC_XNN_PLL_XNN1 1
|
||||
#define EQ7HC_XNN_PLL_XNN2 2
|
||||
#define EQ7HC_XNN_PLL_CLSTR 3
|
||||
#define EQ7HC_XNN_DIV_XNN0 4
|
||||
#define EQ7HC_XNN_DIV_XNN1 5
|
||||
#define EQ7HC_XNN_DIV_XNN2 6
|
||||
#define EQ7HC_XNN_DIV_CLSTR 7
|
||||
#define EQ7HC_XNN_DIV_I2 8
|
||||
#define EQ7HC_XNN_DIV_I2_SMS 9
|
||||
#define EQ7HC_XNN_DIV_CFG 10
|
||||
|
||||
#endif
|
||||
@@ -1152,13 +1152,16 @@ struct clk_fixed_factor {
|
||||
#define to_clk_fixed_factor(_hw) container_of(_hw, struct clk_fixed_factor, hw)
|
||||
|
||||
extern const struct clk_ops clk_fixed_factor_ops;
|
||||
struct clk_hw *
|
||||
__clk_hw_register_fixed_factor(struct device *dev, struct device_node *np,
|
||||
const char *name, const char *parent_name,
|
||||
const struct clk_hw *parent_hw, const struct clk_parent_data *pdata,
|
||||
unsigned long flags, unsigned int mult, unsigned int div,
|
||||
unsigned long acc, unsigned int fixflags, bool devm);
|
||||
struct clk *clk_register_fixed_factor(struct device *dev, const char *name,
|
||||
const char *parent_name, unsigned long flags,
|
||||
unsigned int mult, unsigned int div);
|
||||
void clk_unregister_fixed_factor(struct clk *clk);
|
||||
struct clk_hw *clk_hw_register_fixed_factor(struct device *dev,
|
||||
const char *name, const char *parent_name, unsigned long flags,
|
||||
unsigned int mult, unsigned int div);
|
||||
struct clk_hw *clk_hw_register_fixed_factor_fwname(struct device *dev,
|
||||
struct device_node *np, const char *name, const char *fw_name,
|
||||
unsigned long flags, unsigned int mult, unsigned int div);
|
||||
@@ -1170,9 +1173,6 @@ struct clk_hw *clk_hw_register_fixed_factor_index(struct device *dev,
|
||||
const char *name, unsigned int index, unsigned long flags,
|
||||
unsigned int mult, unsigned int div);
|
||||
void clk_hw_unregister_fixed_factor(struct clk_hw *hw);
|
||||
struct clk_hw *devm_clk_hw_register_fixed_factor(struct device *dev,
|
||||
const char *name, const char *parent_name, unsigned long flags,
|
||||
unsigned int mult, unsigned int div);
|
||||
struct clk_hw *devm_clk_hw_register_fixed_factor_fwname(struct device *dev,
|
||||
struct device_node *np, const char *name, const char *fw_name,
|
||||
unsigned long flags, unsigned int mult, unsigned int div);
|
||||
@@ -1184,13 +1184,45 @@ struct clk_hw *devm_clk_hw_register_fixed_factor_index(struct device *dev,
|
||||
const char *name, unsigned int index, unsigned long flags,
|
||||
unsigned int mult, unsigned int div);
|
||||
|
||||
struct clk_hw *devm_clk_hw_register_fixed_factor_parent_hw(struct device *dev,
|
||||
const char *name, const struct clk_hw *parent_hw,
|
||||
unsigned long flags, unsigned int mult, unsigned int div);
|
||||
#define clk_hw_register_fixed_factor(dev, name, parent_name, \
|
||||
flags, mult, div) \
|
||||
__clk_hw_register_fixed_factor((dev), NULL, (name), (parent_name), \
|
||||
NULL, NULL, (flags), (mult), (div), \
|
||||
0, 0, false)
|
||||
#define clk_hw_register_fixed_factor_pdata(dev, np, name, pdata, \
|
||||
flags, mult, div, acc, fixflags) \
|
||||
__clk_hw_register_fixed_factor((dev), (np), (name), NULL, NULL, \
|
||||
(pdata), (flags), (mult), (div), \
|
||||
(acc), (fixflags), false)
|
||||
#define devm_clk_hw_register_fixed_factor(dev, name, parent_name, flags, \
|
||||
mult, div) \
|
||||
__clk_hw_register_fixed_factor((dev), NULL, (name), (parent_name), \
|
||||
NULL, NULL, (flags), (mult), (div), 0, \
|
||||
0, true)
|
||||
/**
|
||||
* devm_clk_hw_register_fixed_factor_parent_hw - Register a fixed factor clock with
|
||||
* pointer to parent clock
|
||||
* @dev: device that is registering this clock
|
||||
* @name: name of this clock
|
||||
* @parent_hw: pointer to parent clk
|
||||
* @flags: fixed factor flags
|
||||
* @mult: multiplier
|
||||
* @div: divider
|
||||
*
|
||||
* Return: Pointer to fixed factor clk_hw structure that was registered or
|
||||
* an error pointer.
|
||||
*/
|
||||
#define devm_clk_hw_register_fixed_factor_parent_hw(dev, name, parent_hw, \
|
||||
flags, mult, div) \
|
||||
__clk_hw_register_fixed_factor((dev), NULL, (name), NULL, \
|
||||
(parent_hw), NULL, (flags), (mult), \
|
||||
(div), 0, 0, true)
|
||||
|
||||
struct clk_hw *clk_hw_register_fixed_factor_parent_hw(struct device *dev,
|
||||
const char *name, const struct clk_hw *parent_hw,
|
||||
unsigned long flags, unsigned int mult, unsigned int div);
|
||||
#define clk_hw_register_fixed_factor_parent_hw(dev, name, parent_hw, flags, \
|
||||
mult, div) \
|
||||
__clk_hw_register_fixed_factor((dev), NULL, (name), NULL, \
|
||||
(parent_hw), NULL, (flags), (mult), \
|
||||
(div), 0, 0, false)
|
||||
/**
|
||||
* struct clk_fractional_divider - adjustable fractional divider clock
|
||||
*
|
||||
|
||||
Reference in New Issue
Block a user