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https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2026-05-10 11:38:27 -04:00
KVM: x86: Unpack F() CPUID feature flag macros to one flag per line of code
Refactor kvm_set_cpu_caps() to express each supported (or not) feature flag on a separate line, modulo a handful of cases where KVM does not, and likely will not, support a sequence of flags. This will allow adding fancier macros with longer, more descriptive names without resulting in absurd line lengths and/or weird code. Isolating each flag also makes it far easier to review changes, reduces code conflicts, and generally makes it easier to resolve conflicts. Lastly, it allows co-locating comments for notable flags, e.g. MONITOR, precisely with the relevant flag. No functional change intended. Suggested-by: Maxim Levitsky <mlevitsk@redhat.com> Link: https://lore.kernel.org/r/20241128013424.4096668-23-seanjc@google.com Signed-off-by: Sean Christopherson <seanjc@google.com>
This commit is contained in:
Sean Christopherson
@@ -683,48 +683,121 @@ void kvm_set_cpu_caps(void)
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sizeof(kvm_cpu_caps) - (NKVMCAPINTS * sizeof(*kvm_cpu_caps)));
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kvm_cpu_cap_mask(CPUID_1_ECX,
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F(XMM3) |
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F(PCLMULQDQ) |
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0 /* DTES64 */ |
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/*
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* NOTE: MONITOR (and MWAIT) are emulated as NOP, but *not*
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* advertised to guests via CPUID!
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*/
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F(XMM3) | F(PCLMULQDQ) | 0 /* DTES64, MONITOR */ |
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0 /* MONITOR */ |
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0 /* DS-CPL, VMX, SMX, EST */ |
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0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
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F(FMA) | F(CX16) | 0 /* xTPR Update */ | F(PDCM) |
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F(PCID) | 0 /* Reserved, DCA */ | F(XMM4_1) |
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F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
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0 /* Reserved*/ | F(AES) | F(XSAVE) | 0 /* OSXSAVE */ | F(AVX) |
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F(F16C) | F(RDRAND)
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0 /* TM2 */ |
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F(SSSE3) |
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0 /* CNXT-ID */ |
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0 /* Reserved */ |
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F(FMA) |
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F(CX16) |
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0 /* xTPR Update */ |
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F(PDCM) |
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F(PCID) |
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0 /* Reserved, DCA */ |
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F(XMM4_1) |
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F(XMM4_2) |
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F(X2APIC) |
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F(MOVBE) |
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F(POPCNT) |
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0 /* Reserved*/ |
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F(AES) |
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F(XSAVE) |
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0 /* OSXSAVE */ |
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F(AVX) |
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F(F16C) |
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F(RDRAND)
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);
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/* KVM emulates x2apic in software irrespective of host support. */
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kvm_cpu_cap_set(X86_FEATURE_X2APIC);
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kvm_cpu_cap_mask(CPUID_1_EDX,
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F(FPU) | F(VME) | F(DE) | F(PSE) |
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F(TSC) | F(MSR) | F(PAE) | F(MCE) |
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F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
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F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
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F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLUSH) |
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0 /* Reserved, DS, ACPI */ | F(MMX) |
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F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
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F(FPU) |
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F(VME) |
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F(DE) |
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F(PSE) |
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F(TSC) |
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F(MSR) |
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F(PAE) |
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F(MCE) |
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F(CX8) |
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F(APIC) |
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0 /* Reserved */ |
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F(SEP) |
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F(MTRR) |
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F(PGE) |
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F(MCA) |
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F(CMOV) |
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F(PAT) |
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F(PSE36) |
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0 /* PSN */ |
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F(CLFLUSH) |
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0 /* Reserved, DS, ACPI */ |
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F(MMX) |
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F(FXSR) |
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F(XMM) |
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F(XMM2) |
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F(SELFSNOOP) |
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0 /* HTT, TM, Reserved, PBE */
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);
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kvm_cpu_cap_mask(CPUID_7_0_EBX,
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F(FSGSBASE) | F(SGX) | F(BMI1) | F(HLE) | F(AVX2) |
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F(FDP_EXCPTN_ONLY) | F(SMEP) | F(BMI2) | F(ERMS) | F(INVPCID) |
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F(RTM) | F(ZERO_FCS_FDS) | 0 /*MPX*/ | F(AVX512F) |
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F(AVX512DQ) | F(RDSEED) | F(ADX) | F(SMAP) | F(AVX512IFMA) |
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F(CLFLUSHOPT) | F(CLWB) | 0 /*INTEL_PT*/ | F(AVX512PF) |
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F(AVX512ER) | F(AVX512CD) | F(SHA_NI) | F(AVX512BW) |
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F(FSGSBASE) |
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F(SGX) |
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F(BMI1) |
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F(HLE) |
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F(AVX2) |
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F(FDP_EXCPTN_ONLY) |
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F(SMEP) |
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F(BMI2) |
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F(ERMS) |
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F(INVPCID) |
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F(RTM) |
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F(ZERO_FCS_FDS) |
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0 /*MPX*/ |
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F(AVX512F) |
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F(AVX512DQ) |
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F(RDSEED) |
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F(ADX) |
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F(SMAP) |
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F(AVX512IFMA) |
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F(CLFLUSHOPT) |
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F(CLWB) |
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0 /*INTEL_PT*/ |
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F(AVX512PF) |
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F(AVX512ER) |
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F(AVX512CD) |
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F(SHA_NI) |
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F(AVX512BW) |
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F(AVX512VL));
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kvm_cpu_cap_mask(CPUID_7_ECX,
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F(AVX512VBMI) | F(LA57) | F(PKU) | 0 /*OSPKE*/ | F(RDPID) |
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F(AVX512_VPOPCNTDQ) | F(UMIP) | F(AVX512_VBMI2) | F(GFNI) |
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F(VAES) | F(VPCLMULQDQ) | F(AVX512_VNNI) | F(AVX512_BITALG) |
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F(CLDEMOTE) | F(MOVDIRI) | F(MOVDIR64B) | 0 /*WAITPKG*/ |
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F(SGX_LC) | F(BUS_LOCK_DETECT)
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F(AVX512VBMI) |
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F(LA57) |
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F(PKU) |
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0 /*OSPKE*/ |
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F(RDPID) |
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F(AVX512_VPOPCNTDQ) |
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F(UMIP) |
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F(AVX512_VBMI2) |
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F(GFNI) |
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F(VAES) |
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F(VPCLMULQDQ) |
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F(AVX512_VNNI) |
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F(AVX512_BITALG) |
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F(CLDEMOTE) |
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F(MOVDIRI) |
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F(MOVDIR64B) |
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0 /*WAITPKG*/ |
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F(SGX_LC) |
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F(BUS_LOCK_DETECT)
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);
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/* Set LA57 based on hardware capability. */
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if (cpuid_ecx(7) & feature_bit(LA57))
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@@ -738,11 +811,22 @@ void kvm_set_cpu_caps(void)
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kvm_cpu_cap_clear(X86_FEATURE_PKU);
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kvm_cpu_cap_mask(CPUID_7_EDX,
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F(AVX512_4VNNIW) | F(AVX512_4FMAPS) | F(SPEC_CTRL) |
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F(SPEC_CTRL_SSBD) | F(ARCH_CAPABILITIES) | F(INTEL_STIBP) |
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F(MD_CLEAR) | F(AVX512_VP2INTERSECT) | F(FSRM) |
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F(SERIALIZE) | F(TSXLDTRK) | F(AVX512_FP16) |
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F(AMX_TILE) | F(AMX_INT8) | F(AMX_BF16) | F(FLUSH_L1D)
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F(AVX512_4VNNIW) |
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F(AVX512_4FMAPS) |
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F(SPEC_CTRL) |
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F(SPEC_CTRL_SSBD) |
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F(ARCH_CAPABILITIES) |
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F(INTEL_STIBP) |
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F(MD_CLEAR) |
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F(AVX512_VP2INTERSECT) |
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F(FSRM) |
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F(SERIALIZE) |
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F(TSXLDTRK) |
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F(AVX512_FP16) |
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F(AMX_TILE) |
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F(AMX_INT8) |
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F(AMX_BF16) |
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F(FLUSH_L1D)
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);
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/* TSC_ADJUST and ARCH_CAPABILITIES are emulated in software. */
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@@ -759,50 +843,110 @@ void kvm_set_cpu_caps(void)
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kvm_cpu_cap_set(X86_FEATURE_SPEC_CTRL_SSBD);
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kvm_cpu_cap_mask(CPUID_7_1_EAX,
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F(SHA512) | F(SM3) | F(SM4) | F(AVX_VNNI) | F(AVX512_BF16) |
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F(CMPCCXADD) | F(FZRM) | F(FSRS) | F(FSRC) | F(AMX_FP16) |
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F(AVX_IFMA) | F(LAM)
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F(SHA512) |
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F(SM3) |
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F(SM4) |
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F(AVX_VNNI) |
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F(AVX512_BF16) |
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F(CMPCCXADD) |
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F(FZRM) |
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F(FSRS) |
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F(FSRC) |
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F(AMX_FP16) |
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F(AVX_IFMA) |
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F(LAM)
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);
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kvm_cpu_cap_init_kvm_defined(CPUID_7_1_EDX,
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F(AVX_VNNI_INT8) | F(AVX_NE_CONVERT) | F(AMX_COMPLEX) |
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F(AVX_VNNI_INT16) | F(PREFETCHITI) | F(AVX10)
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F(AVX_VNNI_INT8) |
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F(AVX_NE_CONVERT) |
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F(AMX_COMPLEX) |
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F(AVX_VNNI_INT16) |
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F(PREFETCHITI) |
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F(AVX10)
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);
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kvm_cpu_cap_init_kvm_defined(CPUID_7_2_EDX,
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F(INTEL_PSFD) | F(IPRED_CTRL) | F(RRSBA_CTRL) | F(DDPD_U) |
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F(BHI_CTRL) | F(MCDT_NO)
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F(INTEL_PSFD) |
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F(IPRED_CTRL) |
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F(RRSBA_CTRL) |
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F(DDPD_U) |
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F(BHI_CTRL) |
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F(MCDT_NO)
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);
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kvm_cpu_cap_mask(CPUID_D_1_EAX,
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F(XSAVEOPT) | F(XSAVEC) | F(XGETBV1) | F(XSAVES) | f_xfd
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F(XSAVEOPT) |
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F(XSAVEC) |
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F(XGETBV1) |
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F(XSAVES) |
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f_xfd
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);
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kvm_cpu_cap_init_kvm_defined(CPUID_12_EAX,
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SF(SGX1) | SF(SGX2) | SF(SGX_EDECCSSA)
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SF(SGX1) |
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SF(SGX2) |
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SF(SGX_EDECCSSA)
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);
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kvm_cpu_cap_init_kvm_defined(CPUID_24_0_EBX,
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F(AVX10_128) | F(AVX10_256) | F(AVX10_512)
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F(AVX10_128) |
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F(AVX10_256) |
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F(AVX10_512)
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);
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kvm_cpu_cap_mask(CPUID_8000_0001_ECX,
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F(LAHF_LM) | F(CMP_LEGACY) | 0 /*SVM*/ | 0 /* ExtApicSpace */ |
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F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
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F(3DNOWPREFETCH) | F(OSVW) | 0 /* IBS */ | F(XOP) |
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0 /* SKINIT, WDT, LWP */ | F(FMA4) | F(TBM) |
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F(TOPOEXT) | 0 /* PERFCTR_CORE */
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F(LAHF_LM) |
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F(CMP_LEGACY) |
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0 /*SVM*/ |
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0 /* ExtApicSpace */ |
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F(CR8_LEGACY) |
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F(ABM) |
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F(SSE4A) |
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F(MISALIGNSSE) |
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F(3DNOWPREFETCH) |
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F(OSVW) |
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0 /* IBS */ |
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F(XOP) |
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0 /* SKINIT, WDT, LWP */ |
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F(FMA4) |
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F(TBM) |
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F(TOPOEXT) |
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0 /* PERFCTR_CORE */
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);
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kvm_cpu_cap_mask(CPUID_8000_0001_EDX,
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F(FPU) | F(VME) | F(DE) | F(PSE) |
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F(TSC) | F(MSR) | F(PAE) | F(MCE) |
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F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
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F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
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F(PAT) | F(PSE36) | 0 /* Reserved */ |
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F(NX) | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
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F(FXSR) | F(FXSR_OPT) | f_gbpages | F(RDTSCP) |
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0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW)
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F(FPU) |
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F(VME) |
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F(DE) |
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F(PSE) |
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F(TSC) |
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F(MSR) |
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F(PAE) |
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F(MCE) |
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F(CX8) |
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F(APIC) |
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0 /* Reserved */ |
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F(SYSCALL) |
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F(MTRR) |
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F(PGE) |
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F(MCA) |
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F(CMOV) |
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F(PAT) |
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F(PSE36) |
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0 /* Reserved */ |
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F(NX) |
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0 /* Reserved */ |
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F(MMXEXT) |
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F(MMX) |
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F(FXSR) |
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F(FXSR_OPT) |
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f_gbpages |
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F(RDTSCP) |
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0 /* Reserved */ |
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f_lm |
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F(3DNOWEXT) |
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F(3DNOW)
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);
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if (!tdp_enabled && IS_ENABLED(CONFIG_X86_64))
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@@ -813,10 +957,18 @@ void kvm_set_cpu_caps(void)
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);
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kvm_cpu_cap_mask(CPUID_8000_0008_EBX,
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F(CLZERO) | F(XSAVEERPTR) |
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F(WBNOINVD) | F(AMD_IBPB) | F(AMD_IBRS) | F(AMD_SSBD) | F(VIRT_SSBD) |
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F(AMD_SSB_NO) | F(AMD_STIBP) | F(AMD_STIBP_ALWAYS_ON) |
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F(AMD_PSFD) | F(AMD_IBPB_RET)
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F(CLZERO) |
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F(XSAVEERPTR) |
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F(WBNOINVD) |
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F(AMD_IBPB) |
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F(AMD_IBRS) |
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F(AMD_SSBD) |
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F(VIRT_SSBD) |
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F(AMD_SSB_NO) |
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F(AMD_STIBP) |
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F(AMD_STIBP_ALWAYS_ON) |
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F(AMD_PSFD) |
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F(AMD_IBPB_RET)
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);
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/*
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@@ -853,12 +1005,20 @@ void kvm_set_cpu_caps(void)
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kvm_cpu_cap_mask(CPUID_8000_000A_EDX, 0);
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kvm_cpu_cap_mask(CPUID_8000_001F_EAX,
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0 /* SME */ | 0 /* SEV */ | 0 /* VM_PAGE_FLUSH */ | 0 /* SEV_ES */ |
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F(SME_COHERENT));
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0 /* SME */ |
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0 /* SEV */ |
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0 /* VM_PAGE_FLUSH */ |
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0 /* SEV_ES */ |
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F(SME_COHERENT)
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);
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kvm_cpu_cap_mask(CPUID_8000_0021_EAX,
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F(NO_NESTED_DATA_BP) | F(LFENCE_RDTSC) | 0 /* SmmPgCfgLock */ |
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F(NULL_SEL_CLR_BASE) | F(AUTOIBRS) | 0 /* PrefetchCtlMsr */ |
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F(NO_NESTED_DATA_BP) |
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F(LFENCE_RDTSC) |
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0 /* SmmPgCfgLock */ |
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F(NULL_SEL_CLR_BASE) |
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F(AUTOIBRS) |
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0 /* PrefetchCtlMsr */ |
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F(WRMSR_XX_BASE_NS)
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);
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@@ -887,9 +1047,16 @@ void kvm_set_cpu_caps(void)
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kvm_cpu_cap_set(X86_FEATURE_NO_SMM_CTL_MSR);
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kvm_cpu_cap_mask(CPUID_C000_0001_EDX,
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F(XSTORE) | F(XSTORE_EN) | F(XCRYPT) | F(XCRYPT_EN) |
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F(ACE2) | F(ACE2_EN) | F(PHE) | F(PHE_EN) |
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F(PMM) | F(PMM_EN)
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F(XSTORE) |
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F(XSTORE_EN) |
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F(XCRYPT) |
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F(XCRYPT_EN) |
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F(ACE2) |
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F(ACE2_EN) |
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F(PHE) |
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F(PHE_EN) |
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F(PMM) |
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F(PMM_EN)
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);
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/*
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