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drm/i915/fbc: keep FBC disabled if selective update is on in xe2lpd
FBC was disabled in case PSR2 selective update in display 12 to 14 as part of a wa. From xe2lpd onwards there is a logic to be implemented to decide between FBC and selective update. Until that logic is implemented keep FBC disabled in case selective update is enabled. v1: updated patch description and some explanation and todo Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com> Reviewed-by: Jouni Högander <jouni.hogander@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20250321094529.197397-2-vinod.govindapillai@intel.com
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@@ -1465,13 +1465,15 @@ static int intel_fbc_check_plane(struct intel_atomic_state *state,
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* Recommendation is to keep this combination disabled
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* Bspec: 50422 HSD: 14010260002
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*
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* In Xe3, PSR2 selective fetch and FBC dirty rect feature cannot
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* coexist. So if PSR2 selective fetch is supported then mark that
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* FBC is not supported.
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* TODO: Need a logic to decide between PSR2 and FBC Dirty rect
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* TODO: Implement a logic to select between PSR2 selective fetch and
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* FBC based on Bspec: 68881 in xe2lpd onwards.
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*
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* As we still see some strange underruns in those platforms while
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* disabling PSR2, keep FBC disabled in case of selective update is on
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* until the selection logic is implemented.
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*/
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if ((IS_DISPLAY_VER(display, 12, 14) || HAS_FBC_DIRTY_RECT(display)) &&
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crtc_state->has_sel_update && !crtc_state->has_panel_replay) {
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if (DISPLAY_VER(display) >= 12 && crtc_state->has_sel_update &&
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!crtc_state->has_panel_replay) {
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plane_state->no_fbc_reason = "PSR2 enabled";
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return 0;
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}
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