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dt-bindings: net: nxp,s32-dwmac: Declare per-queue interrupts

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The DWMAC IP on NXP S32G/R SoCs has connected queue-based IRQ lines,
set them to allow using Multi-IRQ mode.

Reviewed-by: Matthias Brugger <mbrugger@suse.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Jan Petrous (OSS) <jan.petrous@oss.nxp.com>
Link: https://patch.msgid.link/20260313-dwmac_multi_irq-v12-3-b5c9d0aa13d6@oss.nxp.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Jan Petrous (OSS)
2026-03-13 08:13:34 +01:00
committed by Jakub Kicinski
parent a31bbe5ca2
commit cc7a3435df
1 changed files with 42 additions and 5 deletions
Download Patch File Download Diff File Expand all files Collapse all files

47
Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml
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@@ -1,5 +1,5 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright 2021-2024 NXP
# Copyright 2021-2026 NXP
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/nxp,s32-dwmac.yaml#
@@ -16,6 +16,8 @@ description:
the SoC S32R45 has two instances. The devices can use RGMII/RMII/MII
interface over Pinctrl device or the output can be routed
to the embedded SerDes for SGMII connectivity.
The DWMAC instances have connected all RX/TX queues interrupts,
enabling load balancing of data traffic across all CPU cores.
properties:
compatible:
@@ -45,10 +47,25 @@ properties:
FlexTimer Modules connect to GMAC_0.
interrupts:
maxItems: 1
minItems: 1
maxItems: 11
interrupt-names:
const: macirq
oneOf:
- items:
- const: macirq
- items:
- const: macirq
- const: tx-queue-0
- const: rx-queue-0
- const: tx-queue-1
- const: rx-queue-1
- const: tx-queue-2
- const: rx-queue-2
- const: tx-queue-3
- const: rx-queue-3
- const: tx-queue-4
- const: rx-queue-4
clocks:
items:
@@ -88,8 +105,28 @@ examples:
<0x0 0x4007c004 0x0 0x4>; /* GMAC_0_CTRL_STS */
nxp,phy-sel = <&gpr 0x4>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
/* CHN 0: tx, rx */
<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
/* CHN 1: tx, rx */
<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
/* CHN 2: tx, rx */
<GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,
/* CHN 3: tx, rx */
<GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
/* CHN 4: tx, rx */
<GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq",
"tx-queue-0", "rx-queue-0",
"tx-queue-1", "rx-queue-1",
"tx-queue-2", "rx-queue-2",
"tx-queue-3", "rx-queue-3",
"tx-queue-4", "rx-queue-4";
snps,mtl-rx-config = <&mtl_rx_setup>;
snps,mtl-tx-config = <&mtl_tx_setup>;
clocks = <&clks 24>, <&clks 17>, <&clks 16>, <&clks 15>;