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synced 2026-05-03 20:34:23 -04:00
arm64: dts: Add support for Emtop SoM & Baseboard
Add device tree support for the i.MX8MM Based Emtop SOM-IMX8MMLPD4 (V1) and IMX8M Mini Baseboard (V1). Currently supported are serial console, eMMC. Signed-off-by: Himanshu Bhavani <himanshu.bhavani@siliconsignals.io> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Himanshu Bhavani
committed by
Shawn Guo
Shawn Guo
parent
b954d70abe
commit
cbd3ef64eb
@@ -54,6 +54,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-beacon-kit.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mm-data-modul-edm-sbc.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mm-ddr4-evk.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mm-emcon-avari.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mm-emtop-baseboard.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mm-evkb.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mm-icore-mx8mm-ctouch2.dtb
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15
arch/arm64/boot/dts/freescale/imx8mm-emtop-baseboard.dts
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15
arch/arm64/boot/dts/freescale/imx8mm-emtop-baseboard.dts
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@@ -0,0 +1,15 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright 2023 Emtop Embedded Solutions
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*/
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/dts-v1/;
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#include "imx8mm-emtop-som.dtsi"
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/ {
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model = "Emtop Embedded Solutions i.MX8M Mini Baseboard V1";
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compatible = "ees,imx8mm-emtop-baseboard", "ees,imx8mm-emtop-som",
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"fsl,imx8mm";
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};
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261
arch/arm64/boot/dts/freescale/imx8mm-emtop-som.dtsi
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261
arch/arm64/boot/dts/freescale/imx8mm-emtop-som.dtsi
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@@ -0,0 +1,261 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright 2023 Emtop Embedded Solutions
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*/
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/dts-v1/;
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/leds/common.h>
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#include <dt-bindings/usb/pd.h>
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#include "imx8mm.dtsi"
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/ {
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model = "Emtop Embedded Solutions i.MX8M Mini SOM-IMX8MMLPD4 SoM";
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compatible = "ees,imx8mm-emtop-som", "fsl,imx8mm";
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chosen {
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stdout-path = &uart2;
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};
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leds {
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compatible = "gpio-leds";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gpio_led>;
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led-0 {
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function = LED_FUNCTION_POWER;
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gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
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linux,default-trigger = "heartbeat";
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};
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};
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};
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&A53_0 {
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cpu-supply = <&buck2>;
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};
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&A53_1 {
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cpu-supply = <&buck2>;
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};
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&A53_2 {
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cpu-supply = <&buck2>;
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};
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&A53_3 {
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cpu-supply = <&buck2>;
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};
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&i2c1 {
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clock-frequency = <400000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c1>;
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status = "okay";
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pmic@25 {
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compatible = "nxp,pca9450c";
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reg = <0x25>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pmic>;
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interrupt-parent = <&gpio1>;
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interrupts = <3 IRQ_TYPE_EDGE_RISING>;
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regulators {
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buck1: BUCK1 {
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regulator-name = "BUCK1";
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <1000000>;
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regulator-boot-on;
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regulator-always-on;
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regulator-ramp-delay = <3125>;
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};
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buck2: BUCK2 {
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regulator-name = "BUCK2";
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <900000>;
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regulator-boot-on;
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regulator-always-on;
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regulator-ramp-delay = <3125>;
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};
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buck3: BUCK3 {
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regulator-name = "BUCK3";
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <1000000>;
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regulator-boot-on;
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regulator-always-on;
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};
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buck4: BUCK4 {
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regulator-name = "BUCK4";
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regulator-min-microvolt = <3000000>;
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regulator-max-microvolt = <3600000>;
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regulator-boot-on;
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regulator-always-on;
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};
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buck5: BUCK5 {
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regulator-name = "BUCK5";
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regulator-min-microvolt = <1650000>;
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regulator-max-microvolt = <1950000>;
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regulator-boot-on;
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regulator-always-on;
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};
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buck6: BUCK6 {
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regulator-name = "BUCK6";
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regulator-min-microvolt = <1100000>;
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regulator-max-microvolt = <1200000>;
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regulator-boot-on;
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regulator-always-on;
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};
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ldo1: LDO1 {
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regulator-name = "LDO1";
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regulator-min-microvolt = <1650000>;
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regulator-max-microvolt = <1950000>;
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regulator-boot-on;
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regulator-always-on;
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};
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ldo2: LDO2 {
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regulator-name = "LDO2";
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <945000>;
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regulator-boot-on;
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regulator-always-on;
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};
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ldo3: LDO3 {
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regulator-name = "LDO3";
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regulator-min-microvolt = <1710000>;
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regulator-max-microvolt = <1890000>;
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regulator-boot-on;
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regulator-always-on;
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};
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ldo4: LDO4 {
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regulator-name = "LDO4";
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regulator-min-microvolt = <810000>;
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regulator-max-microvolt = <945000>;
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regulator-boot-on;
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regulator-always-on;
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};
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ldo5: LDO5 {
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regulator-name = "LDO5";
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regulator-min-microvolt = <1650000>;
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regulator-max-microvolt = <3600000>;
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};
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};
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};
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};
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&uart2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart2>;
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status = "okay";
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};
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&usdhc3 {
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc3>;
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pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
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pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
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bus-width = <8>;
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non-removable;
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status = "okay";
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};
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&wdog1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_wdog>;
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fsl,ext-reset-output;
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status = "okay";
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};
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&iomuxc {
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pinctrl_gpio_led: emtop-gpio-led-grp {
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fsl,pins = <
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MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19
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MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29 0x19
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>;
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};
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pinctrl_i2c1: emtop-i2c1-grp {
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fsl,pins = <
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MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
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MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
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>;
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};
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pinctrl_pmic: emtop-pmic-grp {
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fsl,pins = <
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MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41
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>;
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};
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pinctrl_uart2: emtop-uart2-grp {
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fsl,pins = <
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MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
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MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
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>;
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};
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pinctrl_usdhc3: emtop-usdhc3-grp {
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fsl,pins = <
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MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
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MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
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MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
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MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
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MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
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MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
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MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
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MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
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MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
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MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
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MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
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>;
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};
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pinctrl_usdhc3_100mhz: emtop-usdhc3-100mhz-grp {
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fsl,pins = <
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MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
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MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
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MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
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MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
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MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
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MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
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MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
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MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
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MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
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MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
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MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
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>;
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};
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pinctrl_usdhc3_200mhz: emtop-usdhc3-200mhz-grp {
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fsl,pins = <
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MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
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MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
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MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
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MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
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MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
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MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
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MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
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MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
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MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
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MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
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MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
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>;
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};
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pinctrl_wdog: emtop-wdog-grp {
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fsl,pins = <
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MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
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>;
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};
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};
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