drm/amdgpu: reduce early full GPU access during SR-IOV init

Allow early FB reads to fall back to BAR0 when the VRAM aperture is not ready.
This lets SR-IOV VFs consume host-provided init data before requesting full GPU access.

For ASICs that support request_init_data,
defer full GPU access until after non-GPU early init to shorten the full-access window.

Legacy ASICs(before NV12) do not send request_init_data;
the host dumps init data only during full GPU access,
so keep the original early full-access request path for them.

Signed-off-by: chong li <chongli2@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
chong li
2026-07-15 18:41:15 +08:00
committed by Alex Deucher
parent 149f894a2a
commit cba4928cdf
2 changed files with 88 additions and 7 deletions

View File

@@ -745,6 +745,64 @@ void amdgpu_device_mm_access(struct amdgpu_device *adev, loff_t pos,
drm_dev_exit(idx);
}
#ifdef CONFIG_64BIT
/*
* During early SR-IOV VF init, host-provided init data can live in FB before
* the normal VRAM aperture mapping is ready. Use a temporary BAR0 mapping for
* reads only, and verify it matches the VRAM aperture when aperture information
* is already available.
*/
static int amdgpu_device_read_fb_via_bar0(struct amdgpu_device *adev,
u64 offset, void *buf, size_t size)
{
resource_size_t aper_base, aper_size, bar_start, bar_size, map_base;
void __iomem *vram;
size_t map_offset, map_size;
unsigned long flags;
u64 end;
if (!buf || !size)
return -EINVAL;
flags = pci_resource_flags(adev->pdev, 0);
if ((flags & IORESOURCE_UNSET) || !(flags & IORESOURCE_MEM))
return -EINVAL;
bar_start = pci_resource_start(adev->pdev, 0);
bar_size = pci_resource_len(adev->pdev, 0);
if (!bar_size)
return -ENODEV;
aper_base = adev->gmc.aper_base;
aper_size = adev->gmc.visible_vram_size ? adev->gmc.visible_vram_size :
adev->gmc.aper_size;
if (aper_base || aper_size) {
if (aper_base != bar_start || aper_size > bar_size)
return -EINVAL;
} else {
aper_base = bar_start;
aper_size = bar_size;
}
if (check_add_overflow(offset, size, &end) || end > aper_size)
return -EINVAL;
map_offset = offset_in_page(offset);
map_base = aper_base + (offset & PAGE_MASK);
map_size = PAGE_ALIGN(map_offset + size);
vram = ioremap_wc(map_base, map_size);
if (!vram)
return -ENOMEM;
memcpy_fromio(buf, (u8 __iomem *)vram + map_offset, size);
iounmap(vram);
return 0;
}
#endif
/**
* amdgpu_device_aper_access - access vram by vram aperture
*
@@ -764,8 +822,12 @@ size_t amdgpu_device_aper_access(struct amdgpu_device *adev, loff_t pos,
size_t count = 0;
uint64_t last;
if (!adev->mman.aper_base_kaddr)
if (!adev->mman.aper_base_kaddr) {
/* Writes still require the regular aperture/MM path. */
if (!write && !amdgpu_device_read_fb_via_bar0(adev, pos, buf, size))
return size;
return 0;
}
last = min(pos + size, adev->gmc.visible_vram_size);
if (last > pos) {
@@ -1862,16 +1924,25 @@ static int amdgpu_device_ip_early_init(struct amdgpu_device *adev)
{
struct amdgpu_ip_block *ip_block;
struct pci_dev *parent;
bool total, skip_bios;
bool total, skip_bios, early_full_gpu_access = false;
uint32_t bios_flags;
int i, r;
amdgpu_device_enable_virtual_display(adev);
if (amdgpu_sriov_vf(adev)) {
r = amdgpu_virt_request_full_gpu(adev, true);
if (r)
return r;
/*
* Legacy hosts do not provide init data before early init, so
* keep the original early full GPU access request for them. Newer
* hosts publish the init data through VF FB, which lets us defer
* full GPU access until after non-GPU early init work is done.
*/
early_full_gpu_access = (adev->virt.req_init_data_ver == 0);
if (early_full_gpu_access) {
r = amdgpu_virt_request_full_gpu(adev, true);
if (r)
return r;
}
r = amdgpu_virt_init_critical_region(adev);
if (r)
@@ -2034,6 +2105,13 @@ static int amdgpu_device_ip_early_init(struct amdgpu_device *adev)
if (!total)
return -ENODEV;
/* Request full GPU access only for the remaining SR-IOV init work. */
if (amdgpu_sriov_vf(adev) && !early_full_gpu_access) {
r = amdgpu_virt_request_full_gpu(adev, true);
if (r)
return r;
}
if (adev->gmc.xgmi.supported)
amdgpu_xgmi_early_init(adev);

View File

@@ -185,8 +185,11 @@ static int xgpu_ai_send_access_requests(struct amdgpu_device *adev,
} else if (req == IDH_REQ_GPU_INIT_DATA){
/* Dummy REQ_GPU_INIT_DATA handling */
r = xgpu_ai_poll_msg(adev, IDH_REQ_GPU_INIT_DATA_READY);
/* version set to 0 since dummy */
adev->virt.req_init_data_ver = 0;
/*
* AI uses the GPU_CRIT_REGION_V1 layout in practice, so fix the
* dummy version value to match the actual init-data format.
*/
adev->virt.req_init_data_ver = GPU_CRIT_REGION_V1;
}
return 0;