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drm/msm/dpu: get rid of DPU_DSC_OUTPUT_CTRL

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Continue migration to the MDSS-revision based checks and replace
DPU_DSC_OUTPUT_CTRL feature bit with the core_major_ver >= 5 check.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/655404/
Link: https://lore.kernel.org/r/20250522-dpu-drop-features-v5-24-3b2085a07884@oss.qualcomm.com
This commit is contained in:
Dmitry Baryshkov
2025-05-22 22:03:43 +03:00
committed by Dmitry Baryshkov
parent de72346295
commit ca4f289eef
10 changed files with 8 additions and 26 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
View File

@@ -259,19 +259,15 @@ static const struct dpu_dsc_cfg sm8150_dsc[] = {
{
.name = "dsc_0", .id = DSC_0,
.base = 0x80000, .len = 0x140,
.features = BIT(DPU_DSC_OUTPUT_CTRL),
}, {
.name = "dsc_1", .id = DSC_1,
.base = 0x80400, .len = 0x140,
.features = BIT(DPU_DSC_OUTPUT_CTRL),
}, {
.name = "dsc_2", .id = DSC_2,
.base = 0x80800, .len = 0x140,
.features = BIT(DPU_DSC_OUTPUT_CTRL),
}, {
.name = "dsc_3", .id = DSC_3,
.base = 0x80c00, .len = 0x140,
.features = BIT(DPU_DSC_OUTPUT_CTRL),
},
};

6
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
View File

@@ -259,27 +259,21 @@ static const struct dpu_dsc_cfg sc8180x_dsc[] = {
{
.name = "dsc_0", .id = DSC_0,
.base = 0x80000, .len = 0x140,
.features = BIT(DPU_DSC_OUTPUT_CTRL),
}, {
.name = "dsc_1", .id = DSC_1,
.base = 0x80400, .len = 0x140,
.features = BIT(DPU_DSC_OUTPUT_CTRL),
}, {
.name = "dsc_2", .id = DSC_2,
.base = 0x80800, .len = 0x140,
.features = BIT(DPU_DSC_OUTPUT_CTRL),
}, {
.name = "dsc_3", .id = DSC_3,
.base = 0x80c00, .len = 0x140,
.features = BIT(DPU_DSC_OUTPUT_CTRL),
}, {
.name = "dsc_4", .id = DSC_4,
.base = 0x81000, .len = 0x140,
.features = BIT(DPU_DSC_OUTPUT_CTRL),
}, {
.name = "dsc_5", .id = DSC_5,
.base = 0x81400, .len = 0x140,
.features = BIT(DPU_DSC_OUTPUT_CTRL),
},
};

2
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h
View File

@@ -193,11 +193,9 @@ static const struct dpu_dsc_cfg sm7150_dsc[] = {
{
.name = "dsc_0", .id = DSC_0,
.base = 0x80000, .len = 0x140,
.features = BIT(DPU_DSC_OUTPUT_CTRL),
}, {
.name = "dsc_1", .id = DSC_1,
.base = 0x80400, .len = 0x140,
.features = BIT(DPU_DSC_OUTPUT_CTRL),
},
};

4
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
View File

@@ -258,19 +258,15 @@ static const struct dpu_dsc_cfg sm8250_dsc[] = {
{
.name = "dsc_0", .id = DSC_0,
.base = 0x80000, .len = 0x140,
.features = BIT(DPU_DSC_OUTPUT_CTRL),
}, {
.name = "dsc_1", .id = DSC_1,
.base = 0x80400, .len = 0x140,
.features = BIT(DPU_DSC_OUTPUT_CTRL),
}, {
.name = "dsc_2", .id = DSC_2,
.base = 0x80800, .len = 0x140,
.features = BIT(DPU_DSC_OUTPUT_CTRL),
}, {
.name = "dsc_3", .id = DSC_3,
.base = 0x80c00, .len = 0x140,
.features = BIT(DPU_DSC_OUTPUT_CTRL),
},
};

1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
View File

@@ -135,7 +135,6 @@ static const struct dpu_dsc_cfg sm6350_dsc[] = {
{
.name = "dsc_0", .id = DSC_0,
.base = 0x80000, .len = 0x140,
.features = BIT(DPU_DSC_OUTPUT_CTRL),
},
};

1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
View File

@@ -87,7 +87,6 @@ static const struct dpu_dsc_cfg sm6375_dsc[] = {
{
.name = "dsc_0", .id = DSC_0,
.base = 0x80000, .len = 0x140,
.features = BIT(DPU_DSC_OUTPUT_CTRL),
},
};

5
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
View File

@@ -174,14 +174,11 @@ enum {
/**
* DSC sub-blocks/features
* @DPU_DSC_OUTPUT_CTRL Configure which PINGPONG block gets
* the pixel output from this DSC.
* @DPU_DSC_NATIVE_42x_EN Supports NATIVE_422_EN and NATIVE_420_EN encoding
* @DPU_DSC_MAX
*/
enum {
DPU_DSC_OUTPUT_CTRL = 0x1,
DPU_DSC_NATIVE_42x_EN,
DPU_DSC_NATIVE_42x_EN = 0x1,
DPU_DSC_MAX
};

6
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c
View File

@@ -186,11 +186,13 @@ static void dpu_hw_dsc_bind_pingpong_blk(
* @dev: Corresponding device for devres management
* @cfg: DSC catalog entry for which driver object is required
* @addr: Mapped register io address of MDP
* @mdss_ver: dpu core's major and minor versions
* Return: Error code or allocated dpu_hw_dsc context
*/
struct dpu_hw_dsc *dpu_hw_dsc_init(struct drm_device *dev,
const struct dpu_dsc_cfg *cfg,
void __iomem *addr)
void __iomem *addr,
const struct dpu_mdss_version *mdss_ver)
{
struct dpu_hw_dsc *c;
@@ -207,7 +209,7 @@ struct dpu_hw_dsc *dpu_hw_dsc_init(struct drm_device *dev,
c->ops.dsc_disable = dpu_hw_dsc_disable;
c->ops.dsc_config = dpu_hw_dsc_config;
c->ops.dsc_config_thresh = dpu_hw_dsc_config_thresh;
if (c->caps->features & BIT(DPU_DSC_OUTPUT_CTRL))
if (mdss_ver->core_major_ver >= 5)
c->ops.dsc_bind_pingpong_blk = dpu_hw_dsc_bind_pingpong_blk;
return c;

3
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h
View File

@@ -64,7 +64,8 @@ struct dpu_hw_dsc {
struct dpu_hw_dsc *dpu_hw_dsc_init(struct drm_device *dev,
const struct dpu_dsc_cfg *cfg,
void __iomem *addr);
void __iomem *addr,
const struct dpu_mdss_version *mdss_ver);
struct dpu_hw_dsc *dpu_hw_dsc_init_1_2(struct drm_device *dev,
const struct dpu_dsc_cfg *cfg,

2
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
View File

@@ -171,7 +171,7 @@ int dpu_rm_init(struct drm_device *dev,
if (cat->mdss_ver->core_major_ver >= 7)
hw = dpu_hw_dsc_init_1_2(dev, dsc, mmio);
else
hw = dpu_hw_dsc_init(dev, dsc, mmio);
hw = dpu_hw_dsc_init(dev, dsc, mmio, cat->mdss_ver);
if (IS_ERR(hw)) {
rc = PTR_ERR(hw);