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net: stmmac: Refactor FPE functions to generic version

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FPE implementation for DWMAC4 and DWXGMAC differs only for:
1) Offset address of MAC_FPE_CTRL_STS and MTL_FPE_CTRL_STS
2) FPRQ(Frame Preemption Residue Queue) field in MAC_RxQ_Ctrl1
3) Bit offset of Frame Preemption Interrupt Enable

Refactor FPE functions to avoid code duplication and
to simplify the code flow by avoiding the use of
function pointers.

Signed-off-by: Furong Xu <0x1207@gmail.com>
Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
Link: https://patch.msgid.link/49de4607bae69ffe751b13329a3c07a990b82419.1730449003.git.0x1207@gmail.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Furong Xu
2024-11-01 21:31:31 +08:00
committed by Jakub Kicinski
parent af478ca822
commit c9cd9a5a83
11 changed files with 104 additions and 136 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
drivers/net/ethernet/stmicro/stmmac/dwmac4.h
View File

@@ -69,7 +69,6 @@
#define GMAC_RXQCTRL_TACPQE BIT(21)
#define GMAC_RXQCTRL_TACPQE_SHIFT 21
#define GMAC_RXQCTRL_FPRQ GENMASK(26, 24)
#define GMAC_RXQCTRL_FPRQ_SHIFT 24
/* MAC Packet Filtering */
#define GMAC_PACKET_FILTER_PR BIT(0)

10
drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
View File

@@ -1262,11 +1262,6 @@ const struct stmmac_ops dwmac410_ops = {
.set_arp_offload = dwmac4_set_arp_offload,
.config_l3_filter = dwmac4_config_l3_filter,
.config_l4_filter = dwmac4_config_l4_filter,
.fpe_configure = dwmac5_fpe_configure,
.fpe_send_mpacket = dwmac5_fpe_send_mpacket,
.fpe_irq_status = dwmac5_fpe_irq_status,
.fpe_get_add_frag_size = dwmac5_fpe_get_add_frag_size,
.fpe_set_add_frag_size = dwmac5_fpe_set_add_frag_size,
.fpe_map_preemption_class = dwmac5_fpe_map_preemption_class,
.add_hw_vlan_rx_fltr = dwmac4_add_hw_vlan_rx_fltr,
.del_hw_vlan_rx_fltr = dwmac4_del_hw_vlan_rx_fltr,
@@ -1317,11 +1312,6 @@ const struct stmmac_ops dwmac510_ops = {
.set_arp_offload = dwmac4_set_arp_offload,
.config_l3_filter = dwmac4_config_l3_filter,
.config_l4_filter = dwmac4_config_l4_filter,
.fpe_configure = dwmac5_fpe_configure,
.fpe_send_mpacket = dwmac5_fpe_send_mpacket,
.fpe_irq_status = dwmac5_fpe_irq_status,
.fpe_get_add_frag_size = dwmac5_fpe_get_add_frag_size,
.fpe_set_add_frag_size = dwmac5_fpe_set_add_frag_size,
.fpe_map_preemption_class = dwmac5_fpe_map_preemption_class,
.add_hw_vlan_rx_fltr = dwmac4_add_hw_vlan_rx_fltr,
.del_hw_vlan_rx_fltr = dwmac4_del_hw_vlan_rx_fltr,

2
drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h
View File

@@ -85,7 +85,6 @@
#define XGMAC_MCBCQ GENMASK(11, 8)
#define XGMAC_MCBCQ_SHIFT 8
#define XGMAC_RQ GENMASK(7, 4)
#define XGMAC_RQ_SHIFT 4
#define XGMAC_UPQ GENMASK(3, 0)
#define XGMAC_UPQ_SHIFT 0
#define XGMAC_RXQ_CTRL2 0x000000a8
@@ -96,6 +95,7 @@
#define XGMAC_LPIIS BIT(5)
#define XGMAC_PMTIS BIT(4)
#define XGMAC_INT_EN 0x000000b4
#define XGMAC_FPEIE BIT(15)
#define XGMAC_TSIE BIT(12)
#define XGMAC_LPIIE BIT(5)
#define XGMAC_PMTIE BIT(4)

2
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
View File

@@ -1545,7 +1545,6 @@ const struct stmmac_ops dwxgmac210_ops = {
.config_l3_filter = dwxgmac2_config_l3_filter,
.config_l4_filter = dwxgmac2_config_l4_filter,
.set_arp_offload = dwxgmac2_set_arp_offload,
.fpe_configure = dwxgmac3_fpe_configure,
};
static void dwxlgmac2_rx_queue_enable(struct mac_device_info *hw, u8 mode,
@@ -1602,7 +1601,6 @@ const struct stmmac_ops dwxlgmac2_ops = {
.config_l3_filter = dwxgmac2_config_l3_filter,
.config_l4_filter = dwxgmac2_config_l4_filter,
.set_arp_offload = dwxgmac2_set_arp_offload,
.fpe_configure = dwxgmac3_fpe_configure,
};
int dwxgmac2_setup(struct stmmac_priv *priv)

7
drivers/net/ethernet/stmicro/stmmac/hwif.c
View File

@@ -6,6 +6,7 @@
#include "common.h"
#include "stmmac.h"
#include "stmmac_fpe.h"
#include "stmmac_ptp.h"
#include "stmmac_est.h"
@@ -185,6 +186,7 @@ static const struct stmmac_hwif_entry {
.ptp_off = PTP_GMAC4_OFFSET,
.mmc_off = MMC_GMAC4_OFFSET,
.est_off = EST_GMAC4_OFFSET,
.fpe_reg = &dwmac5_fpe_reg,
},
.desc = &dwmac4_desc_ops,
.dma = &dwmac4_dma_ops,
@@ -205,6 +207,7 @@ static const struct stmmac_hwif_entry {
.ptp_off = PTP_GMAC4_OFFSET,
.mmc_off = MMC_GMAC4_OFFSET,
.est_off = EST_GMAC4_OFFSET,
.fpe_reg = &dwmac5_fpe_reg,
},
.desc = &dwmac4_desc_ops,
.dma = &dwmac410_dma_ops,
@@ -225,6 +228,7 @@ static const struct stmmac_hwif_entry {
.ptp_off = PTP_GMAC4_OFFSET,
.mmc_off = MMC_GMAC4_OFFSET,
.est_off = EST_GMAC4_OFFSET,
.fpe_reg = &dwmac5_fpe_reg,
},
.desc = &dwmac4_desc_ops,
.dma = &dwmac410_dma_ops,
@@ -246,6 +250,7 @@ static const struct stmmac_hwif_entry {
.ptp_off = PTP_XGMAC_OFFSET,
.mmc_off = MMC_XGMAC_OFFSET,
.est_off = EST_XGMAC_OFFSET,
.fpe_reg = &dwxgmac3_fpe_reg,
},
.desc = &dwxgmac210_desc_ops,
.dma = &dwxgmac210_dma_ops,
@@ -267,6 +272,7 @@ static const struct stmmac_hwif_entry {
.ptp_off = PTP_XGMAC_OFFSET,
.mmc_off = MMC_XGMAC_OFFSET,
.est_off = EST_XGMAC_OFFSET,
.fpe_reg = &dwxgmac3_fpe_reg,
},
.desc = &dwxgmac210_desc_ops,
.dma = &dwxgmac210_dma_ops,
@@ -353,6 +359,7 @@ int stmmac_hwif_init(struct stmmac_priv *priv)
mac->est = mac->est ? : entry->est;
priv->hw = mac;
priv->fpe_cfg.reg = entry->regs.fpe_reg;
priv->ptpaddr = priv->ioaddr + entry->regs.ptp_off;
priv->mmcaddr = priv->ioaddr + entry->regs.mmc_off;
if (entry->est)

20
drivers/net/ethernet/stmicro/stmmac/hwif.h
View File

@@ -420,15 +420,6 @@ struct stmmac_ops {
bool en, bool udp, bool sa, bool inv,
u32 match);
void (*set_arp_offload)(struct mac_device_info *hw, bool en, u32 addr);
void (*fpe_configure)(void __iomem *ioaddr, struct stmmac_fpe_cfg *cfg,
u32 num_txq, u32 num_rxq,
bool tx_enable, bool pmac_enable);
void (*fpe_send_mpacket)(void __iomem *ioaddr,
struct stmmac_fpe_cfg *cfg,
enum stmmac_mpacket_type type);
int (*fpe_irq_status)(void __iomem *ioaddr, struct net_device *dev);
int (*fpe_get_add_frag_size)(const void __iomem *ioaddr);
void (*fpe_set_add_frag_size)(void __iomem *ioaddr, u32 add_frag_size);
int (*fpe_map_preemption_class)(struct net_device *ndev,
struct netlink_ext_ack *extack,
u32 pclass);
@@ -530,16 +521,6 @@ struct stmmac_ops {
stmmac_do_callback(__priv, mac, config_l4_filter, __args)
#define stmmac_set_arp_offload(__priv, __args...) \
stmmac_do_void_callback(__priv, mac, set_arp_offload, __args)
#define stmmac_fpe_configure(__priv, __args...) \
stmmac_do_void_callback(__priv, mac, fpe_configure, __args)
#define stmmac_fpe_send_mpacket(__priv, __args...) \
stmmac_do_void_callback(__priv, mac, fpe_send_mpacket, __args)
#define stmmac_fpe_irq_status(__priv, __args...) \
stmmac_do_callback(__priv, mac, fpe_irq_status, __args)
#define stmmac_fpe_get_add_frag_size(__priv, __args...) \
stmmac_do_callback(__priv, mac, fpe_get_add_frag_size, __args)
#define stmmac_fpe_set_add_frag_size(__priv, __args...) \
stmmac_do_void_callback(__priv, mac, fpe_set_add_frag_size, __args)
#define stmmac_fpe_map_preemption_class(__priv, __args...) \
stmmac_do_void_callback(__priv, mac, fpe_map_preemption_class, __args)
@@ -678,6 +659,7 @@ struct stmmac_est_ops {
stmmac_do_void_callback(__priv, est, irq_status, __args)
struct stmmac_regs_off {
const struct stmmac_fpe_reg *fpe_reg;
u32 ptp_off;
u32 mmc_off;
u32 est_off;

1
drivers/net/ethernet/stmicro/stmmac/stmmac.h
View File

@@ -152,6 +152,7 @@ struct stmmac_fpe_cfg {
*/
spinlock_t lock;
const struct stmmac_fpe_reg *reg;
u32 fpe_csr; /* MAC_FPE_CTRL_STS reg cache */
enum ethtool_mm_verify_status status;

4
drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c
View File

@@ -1294,7 +1294,7 @@ static int stmmac_get_mm(struct net_device *ndev,
else
state->tx_active = false;
frag_size = stmmac_fpe_get_add_frag_size(priv, priv->ioaddr);
frag_size = stmmac_fpe_get_add_frag_size(priv);
state->tx_min_frag_size = ethtool_mm_frag_size_add_to_min(frag_size);
spin_unlock_irqrestore(&priv->fpe_cfg.lock, flags);
@@ -1329,7 +1329,7 @@ static int stmmac_set_mm(struct net_device *ndev, struct ethtool_mm_cfg *cfg,
if (!cfg->verify_enabled)
fpe_cfg->status = ETHTOOL_MM_VERIFY_STATUS_DISABLED;
stmmac_fpe_set_add_frag_size(priv, priv->ioaddr, frag_size);
stmmac_fpe_set_add_frag_size(priv, frag_size);
stmmac_fpe_apply(priv);
spin_unlock_irqrestore(&fpe_cfg->lock, flags);

160
drivers/net/ethernet/stmicro/stmmac/stmmac_fpe.c
View File

@@ -27,58 +27,80 @@
#define STMMAC_MAC_FPE_CTRL_STS_SVER BIT(1)
#define STMMAC_MAC_FPE_CTRL_STS_EFPE BIT(0)
/* FPE link-partner hand-shaking mPacket type */
enum stmmac_mpacket_type {
MPACKET_VERIFY = 0,
MPACKET_RESPONSE = 1,
};
struct stmmac_fpe_reg {
const u32 mac_fpe_reg; /* offset of MAC_FPE_CTRL_STS */
const u32 mtl_fpe_reg; /* offset of MTL_FPE_CTRL_STS */
const u32 rxq_ctrl1_reg; /* offset of MAC_RxQ_Ctrl1 */
const u32 fprq_mask; /* Frame Preemption Residue Queue */
const u32 int_en_reg; /* offset of MAC_Interrupt_Enable */
const u32 int_en_bit; /* Frame Preemption Interrupt Enable */
};
bool stmmac_fpe_supported(struct stmmac_priv *priv)
{
return priv->dma_cap.fpesel;
return priv->dma_cap.fpesel && priv->fpe_cfg.reg &&
priv->hw->mac->fpe_map_preemption_class;
}
void dwmac5_fpe_configure(void __iomem *ioaddr, struct stmmac_fpe_cfg *cfg,
u32 num_txq, u32 num_rxq,
bool tx_enable, bool pmac_enable)
static void stmmac_fpe_configure(struct stmmac_priv *priv, bool tx_enable,
bool pmac_enable)
{
struct stmmac_fpe_cfg *cfg = &priv->fpe_cfg;
const struct stmmac_fpe_reg *reg = cfg->reg;
u32 num_rxq = priv->plat->rx_queues_to_use;
void __iomem *ioaddr = priv->ioaddr;
u32 value;
if (tx_enable) {
cfg->fpe_csr = STMMAC_MAC_FPE_CTRL_STS_EFPE;
value = readl(ioaddr + GMAC_RXQ_CTRL1);
value &= ~GMAC_RXQCTRL_FPRQ;
value |= (num_rxq - 1) << GMAC_RXQCTRL_FPRQ_SHIFT;
writel(value, ioaddr + GMAC_RXQ_CTRL1);
value = readl(ioaddr + reg->rxq_ctrl1_reg);
value &= ~reg->fprq_mask;
/* Keep this SHIFT, FIELD_PREP() expects a constant mask :-/ */
value |= (num_rxq - 1) << __ffs(reg->fprq_mask);
writel(value, ioaddr + reg->rxq_ctrl1_reg);
} else {
cfg->fpe_csr = 0;
}
writel(cfg->fpe_csr, ioaddr + GMAC5_MAC_FPE_CTRL_STS);
writel(cfg->fpe_csr, ioaddr + reg->mac_fpe_reg);
value = readl(ioaddr + GMAC_INT_EN);
value = readl(ioaddr + reg->int_en_reg);
if (pmac_enable) {
if (!(value & GMAC_INT_FPE_EN)) {
if (!(value & reg->int_en_bit)) {
/* Dummy read to clear any pending masked interrupts */
readl(ioaddr + GMAC5_MAC_FPE_CTRL_STS);
readl(ioaddr + reg->mac_fpe_reg);
value |= GMAC_INT_FPE_EN;
value |= reg->int_en_bit;
}
} else {
value &= ~GMAC_INT_FPE_EN;
value &= ~reg->int_en_bit;
}
writel(value, ioaddr + GMAC_INT_EN);
writel(value, ioaddr + reg->int_en_reg);
}
void dwmac5_fpe_send_mpacket(void __iomem *ioaddr, struct stmmac_fpe_cfg *cfg,
enum stmmac_mpacket_type type)
static void stmmac_fpe_send_mpacket(struct stmmac_priv *priv,
enum stmmac_mpacket_type type)
{
u32 value = cfg->fpe_csr;
const struct stmmac_fpe_reg *reg = priv->fpe_cfg.reg;
void __iomem *ioaddr = priv->ioaddr;
u32 value = priv->fpe_cfg.fpe_csr;
if (type == MPACKET_VERIFY)
value |= STMMAC_MAC_FPE_CTRL_STS_SVER;
else if (type == MPACKET_RESPONSE)
value |= STMMAC_MAC_FPE_CTRL_STS_SRSP;
writel(value, ioaddr + GMAC5_MAC_FPE_CTRL_STS);
writel(value, ioaddr + reg->mac_fpe_reg);
}
void stmmac_fpe_event_status(struct stmmac_priv *priv, int status)
static void stmmac_fpe_event_status(struct stmmac_priv *priv, int status)
{
struct stmmac_fpe_cfg *fpe_cfg = &priv->fpe_cfg;
@@ -90,8 +112,7 @@ void stmmac_fpe_event_status(struct stmmac_priv *priv, int status)
/* LP has sent verify mPacket */
if ((status & FPE_EVENT_RVER) == FPE_EVENT_RVER)
stmmac_fpe_send_mpacket(priv, priv->ioaddr, fpe_cfg,
MPACKET_RESPONSE);
stmmac_fpe_send_mpacket(priv, MPACKET_RESPONSE);
/* Local has sent verify mPacket */
if ((status & FPE_EVENT_TVER) == FPE_EVENT_TVER &&
@@ -107,17 +128,18 @@ void stmmac_fpe_event_status(struct stmmac_priv *priv, int status)
spin_unlock(&fpe_cfg->lock);
}
int dwmac5_fpe_irq_status(void __iomem *ioaddr, struct net_device *dev)
void stmmac_fpe_irq_status(struct stmmac_priv *priv)
{
const struct stmmac_fpe_reg *reg = priv->fpe_cfg.reg;
void __iomem *ioaddr = priv->ioaddr;
struct net_device *dev = priv->dev;
int status = FPE_EVENT_UNKNOWN;
u32 value;
int status;
status = FPE_EVENT_UNKNOWN;
/* Reads from the MAC_FPE_CTRL_STS register should only be performed
* here, since the status flags of MAC_FPE_CTRL_STS are "clear on read"
*/
value = readl(ioaddr + GMAC5_MAC_FPE_CTRL_STS);
value = readl(ioaddr + reg->mac_fpe_reg);
if (value & STMMAC_MAC_FPE_CTRL_STS_TRSP) {
status |= FPE_EVENT_TRSP;
@@ -139,7 +161,7 @@ int dwmac5_fpe_irq_status(void __iomem *ioaddr, struct net_device *dev)
netdev_dbg(dev, "FPE: Verify mPacket is received\n");
}
return status;
stmmac_fpe_event_status(priv, status);
}
/**
@@ -164,8 +186,7 @@ static void stmmac_fpe_verify_timer(struct timer_list *t)
case ETHTOOL_MM_VERIFY_STATUS_INITIAL:
case ETHTOOL_MM_VERIFY_STATUS_VERIFYING:
if (fpe_cfg->verify_retries != 0) {
stmmac_fpe_send_mpacket(priv, priv->ioaddr,
fpe_cfg, MPACKET_VERIFY);
stmmac_fpe_send_mpacket(priv, MPACKET_VERIFY);
rearm = true;
} else {
fpe_cfg->status = ETHTOOL_MM_VERIFY_STATUS_FAILED;
@@ -175,10 +196,7 @@ static void stmmac_fpe_verify_timer(struct timer_list *t)
break;
case ETHTOOL_MM_VERIFY_STATUS_SUCCEEDED:
stmmac_fpe_configure(priv, priv->ioaddr, fpe_cfg,
priv->plat->tx_queues_to_use,
priv->plat->rx_queues_to_use,
true, true);
stmmac_fpe_configure(priv, true, true);
break;
default:
@@ -211,6 +229,10 @@ void stmmac_fpe_init(struct stmmac_priv *priv)
priv->fpe_cfg.status = ETHTOOL_MM_VERIFY_STATUS_DISABLED;
timer_setup(&priv->fpe_cfg.verify_timer, stmmac_fpe_verify_timer, 0);
spin_lock_init(&priv->fpe_cfg.lock);
if ((!priv->fpe_cfg.reg || !priv->hw->mac->fpe_map_preemption_class) &&
priv->dma_cap.fpesel)
dev_info(priv->device, "FPE is not supported by driver.\n");
}
void stmmac_fpe_apply(struct stmmac_priv *priv)
@@ -221,10 +243,7 @@ void stmmac_fpe_apply(struct stmmac_priv *priv)
* Otherwise let the timer code do it.
*/
if (!fpe_cfg->verify_enabled) {
stmmac_fpe_configure(priv, priv->ioaddr, fpe_cfg,
priv->plat->tx_queues_to_use,
priv->plat->rx_queues_to_use,
fpe_cfg->tx_enabled,
stmmac_fpe_configure(priv, fpe_cfg->tx_enabled,
fpe_cfg->pmac_enabled);
} else {
fpe_cfg->status = ETHTOOL_MM_VERIFY_STATUS_INITIAL;
@@ -246,37 +265,35 @@ void stmmac_fpe_link_state_handle(struct stmmac_priv *priv, bool is_up)
if (is_up && fpe_cfg->pmac_enabled) {
/* VERIFY process requires pmac enabled when NIC comes up */
stmmac_fpe_configure(priv, priv->ioaddr, fpe_cfg,
priv->plat->tx_queues_to_use,
priv->plat->rx_queues_to_use,
false, true);
stmmac_fpe_configure(priv, false, true);
/* New link => maybe new partner => new verification process */
stmmac_fpe_apply(priv);
} else {
/* No link => turn off EFPE */
stmmac_fpe_configure(priv, priv->ioaddr, fpe_cfg,
priv->plat->tx_queues_to_use,
priv->plat->rx_queues_to_use,
false, false);
stmmac_fpe_configure(priv, false, false);
}
spin_unlock_irqrestore(&fpe_cfg->lock, flags);
}
int dwmac5_fpe_get_add_frag_size(const void __iomem *ioaddr)
int stmmac_fpe_get_add_frag_size(struct stmmac_priv *priv)
{
return FIELD_GET(FPE_MTL_ADD_FRAG_SZ,
readl(ioaddr + GMAC5_MTL_FPE_CTRL_STS));
const struct stmmac_fpe_reg *reg = priv->fpe_cfg.reg;
void __iomem *ioaddr = priv->ioaddr;
return FIELD_GET(FPE_MTL_ADD_FRAG_SZ, readl(ioaddr + reg->mtl_fpe_reg));
}
void dwmac5_fpe_set_add_frag_size(void __iomem *ioaddr, u32 add_frag_size)
void stmmac_fpe_set_add_frag_size(struct stmmac_priv *priv, u32 add_frag_size)
{
const struct stmmac_fpe_reg *reg = priv->fpe_cfg.reg;
void __iomem *ioaddr = priv->ioaddr;
u32 value;
value = readl(ioaddr + GMAC5_MTL_FPE_CTRL_STS);
value = readl(ioaddr + reg->mtl_fpe_reg);
writel(u32_replace_bits(value, add_frag_size, FPE_MTL_ADD_FRAG_SZ),
ioaddr + GMAC5_MTL_FPE_CTRL_STS);
ioaddr + reg->mtl_fpe_reg);
}
#define ALG_ERR_MSG "TX algorithm SP is not suitable for one-to-many mapping"
@@ -334,27 +351,20 @@ int dwmac5_fpe_map_preemption_class(struct net_device *ndev,
return 0;
}
void dwxgmac3_fpe_configure(void __iomem *ioaddr, struct stmmac_fpe_cfg *cfg,
u32 num_txq, u32 num_rxq,
bool tx_enable, bool pmac_enable)
{
u32 value;
const struct stmmac_fpe_reg dwmac5_fpe_reg = {
.mac_fpe_reg = GMAC5_MAC_FPE_CTRL_STS,
.mtl_fpe_reg = GMAC5_MTL_FPE_CTRL_STS,
.rxq_ctrl1_reg = GMAC_RXQ_CTRL1,
.fprq_mask = GMAC_RXQCTRL_FPRQ,
.int_en_reg = GMAC_INT_EN,
.int_en_bit = GMAC_INT_FPE_EN,
};
if (!tx_enable) {
value = readl(ioaddr + XGMAC_MAC_FPE_CTRL_STS);
value &= ~STMMAC_MAC_FPE_CTRL_STS_EFPE;
writel(value, ioaddr + XGMAC_MAC_FPE_CTRL_STS);
return;
}
value = readl(ioaddr + XGMAC_RXQ_CTRL1);
value &= ~XGMAC_RQ;
value |= (num_rxq - 1) << XGMAC_RQ_SHIFT;
writel(value, ioaddr + XGMAC_RXQ_CTRL1);
value = readl(ioaddr + XGMAC_MAC_FPE_CTRL_STS);
value |= STMMAC_MAC_FPE_CTRL_STS_EFPE;
writel(value, ioaddr + XGMAC_MAC_FPE_CTRL_STS);
}
const struct stmmac_fpe_reg dwxgmac3_fpe_reg = {
.mac_fpe_reg = XGMAC_MAC_FPE_CTRL_STS,
.mtl_fpe_reg = XGMAC_MTL_FPE_CTRL_STS,
.rxq_ctrl1_reg = XGMAC_RXQ_CTRL1,
.fprq_mask = XGMAC_RQ,
.int_en_reg = XGMAC_INT_EN,
.int_en_bit = XGMAC_FPEIE,
};

25
drivers/net/ethernet/stmicro/stmmac/stmmac_fpe.h
View File

@@ -12,35 +12,20 @@
#define STMMAC_FPE_MM_MAX_VERIFY_RETRIES 3
#define STMMAC_FPE_MM_MAX_VERIFY_TIME_MS 128
/* FPE link-partner hand-shaking mPacket type */
enum stmmac_mpacket_type {
MPACKET_VERIFY = 0,
MPACKET_RESPONSE = 1,
};
struct stmmac_priv;
struct stmmac_fpe_cfg;
void stmmac_fpe_link_state_handle(struct stmmac_priv *priv, bool is_up);
void stmmac_fpe_event_status(struct stmmac_priv *priv, int status);
bool stmmac_fpe_supported(struct stmmac_priv *priv);
void stmmac_fpe_init(struct stmmac_priv *priv);
void stmmac_fpe_apply(struct stmmac_priv *priv);
void stmmac_fpe_irq_status(struct stmmac_priv *priv);
int stmmac_fpe_get_add_frag_size(struct stmmac_priv *priv);
void stmmac_fpe_set_add_frag_size(struct stmmac_priv *priv, u32 add_frag_size);
void dwmac5_fpe_configure(void __iomem *ioaddr, struct stmmac_fpe_cfg *cfg,
u32 num_txq, u32 num_rxq,
bool tx_enable, bool pmac_enable);
void dwmac5_fpe_send_mpacket(void __iomem *ioaddr,
struct stmmac_fpe_cfg *cfg,
enum stmmac_mpacket_type type);
int dwmac5_fpe_irq_status(void __iomem *ioaddr, struct net_device *dev);
int dwmac5_fpe_get_add_frag_size(const void __iomem *ioaddr);
void dwmac5_fpe_set_add_frag_size(void __iomem *ioaddr, u32 add_frag_size);
int dwmac5_fpe_map_preemption_class(struct net_device *ndev,
struct netlink_ext_ack *extack, u32 pclass);
void dwxgmac3_fpe_configure(void __iomem *ioaddr, struct stmmac_fpe_cfg *cfg,
u32 num_txq, u32 num_rxq,
bool tx_enable, bool pmac_enable);
extern const struct stmmac_fpe_reg dwmac5_fpe_reg;
extern const struct stmmac_fpe_reg dwxgmac3_fpe_reg;
#endif

8
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
View File

@@ -5955,12 +5955,8 @@ static void stmmac_common_interrupt(struct stmmac_priv *priv)
stmmac_est_irq_status(priv, priv, priv->dev,
&priv->xstats, tx_cnt);
if (stmmac_fpe_supported(priv)) {
int status = stmmac_fpe_irq_status(priv, priv->ioaddr,
priv->dev);
stmmac_fpe_event_status(priv, status);
}
if (stmmac_fpe_supported(priv))
stmmac_fpe_irq_status(priv);
/* To handle GMAC own interrupts */
if ((priv->plat->has_gmac) || xmac) {