mirrors/linux
2
0
Fork 0
mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git synced 2026-05-09 22:14:36 -04:00
Code Issues Packages Projects Releases Wiki Activity

drm/i915/display: convert the M/N functions to struct intel_display

Browse Source 
Going forward, struct intel_display is the main display device data
pointer. Convert the functions to set/get M/N values and check for M2/N2
support to struct intel_display.

Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/8ac3472fe8e6647c0da57013c8bef575d8324a88.1740502116.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
This commit is contained in:
Jani Nikula
2025-02-25 18:49:08 +02:00
parent 8266c81710
commit c9c672db1f
5 changed files with 59 additions and 62 deletions
Download Patch File Download Diff File Expand all files Collapse all files

88
drivers/gpu/drm/i915/display/intel_display.c
View File

@@ -2662,45 +2662,45 @@ void intel_zero_m_n(struct intel_link_m_n *m_n)
m_n->tu = 1;
}
void intel_set_m_n(struct drm_i915_private *i915,
void intel_set_m_n(struct intel_display *display,
const struct intel_link_m_n *m_n,
i915_reg_t data_m_reg, i915_reg_t data_n_reg,
i915_reg_t link_m_reg, i915_reg_t link_n_reg)
{
intel_de_write(i915, data_m_reg, TU_SIZE(m_n->tu) | m_n->data_m);
intel_de_write(i915, data_n_reg, m_n->data_n);
intel_de_write(i915, link_m_reg, m_n->link_m);
intel_de_write(display, data_m_reg, TU_SIZE(m_n->tu) | m_n->data_m);
intel_de_write(display, data_n_reg, m_n->data_n);
intel_de_write(display, link_m_reg, m_n->link_m);
/*
* On BDW+ writing LINK_N arms the double buffered update
* of all the M/N registers, so it must be written last.
*/
intel_de_write(i915, link_n_reg, m_n->link_n);
intel_de_write(display, link_n_reg, m_n->link_n);
}
bool intel_cpu_transcoder_has_m2_n2(struct drm_i915_private *dev_priv,
bool intel_cpu_transcoder_has_m2_n2(struct intel_display *display,
enum transcoder transcoder)
{
if (IS_HASWELL(dev_priv))
if (display->platform.haswell)
return transcoder == TRANSCODER_EDP;
return IS_DISPLAY_VER(dev_priv, 5, 7) || IS_CHERRYVIEW(dev_priv);
return IS_DISPLAY_VER(display, 5, 7) || display->platform.cherryview;
}
void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc,
enum transcoder transcoder,
const struct intel_link_m_n *m_n)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct intel_display *display = to_intel_display(crtc);
enum pipe pipe = crtc->pipe;
if (DISPLAY_VER(dev_priv) >= 5)
intel_set_m_n(dev_priv, m_n,
PIPE_DATA_M1(dev_priv, transcoder),
PIPE_DATA_N1(dev_priv, transcoder),
PIPE_LINK_M1(dev_priv, transcoder),
PIPE_LINK_N1(dev_priv, transcoder));
if (DISPLAY_VER(display) >= 5)
intel_set_m_n(display, m_n,
PIPE_DATA_M1(display, transcoder),
PIPE_DATA_N1(display, transcoder),
PIPE_LINK_M1(display, transcoder),
PIPE_LINK_N1(display, transcoder));
else
intel_set_m_n(dev_priv, m_n,
intel_set_m_n(display, m_n,
PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe),
PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe));
}
@@ -2709,16 +2709,16 @@ void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc,
enum transcoder transcoder,
const struct intel_link_m_n *m_n)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct intel_display *display = to_intel_display(crtc);
if (!intel_cpu_transcoder_has_m2_n2(dev_priv, transcoder))
if (!intel_cpu_transcoder_has_m2_n2(display, transcoder))
return;
intel_set_m_n(dev_priv, m_n,
PIPE_DATA_M2(dev_priv, transcoder),
PIPE_DATA_N2(dev_priv, transcoder),
PIPE_LINK_M2(dev_priv, transcoder),
PIPE_LINK_N2(dev_priv, transcoder));
intel_set_m_n(display, m_n,
PIPE_DATA_M2(display, transcoder),
PIPE_DATA_N2(display, transcoder),
PIPE_LINK_M2(display, transcoder),
PIPE_LINK_N2(display, transcoder));
}
static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
@@ -3404,33 +3404,33 @@ int ilk_get_lanes_required(int target_clock, int link_bw, int bpp)
return DIV_ROUND_UP(bps, link_bw * 8);
}
void intel_get_m_n(struct drm_i915_private *i915,
void intel_get_m_n(struct intel_display *display,
struct intel_link_m_n *m_n,
i915_reg_t data_m_reg, i915_reg_t data_n_reg,
i915_reg_t link_m_reg, i915_reg_t link_n_reg)
{
m_n->link_m = intel_de_read(i915, link_m_reg) & DATA_LINK_M_N_MASK;
m_n->link_n = intel_de_read(i915, link_n_reg) & DATA_LINK_M_N_MASK;
m_n->data_m = intel_de_read(i915, data_m_reg) & DATA_LINK_M_N_MASK;
m_n->data_n = intel_de_read(i915, data_n_reg) & DATA_LINK_M_N_MASK;
m_n->tu = REG_FIELD_GET(TU_SIZE_MASK, intel_de_read(i915, data_m_reg)) + 1;
m_n->link_m = intel_de_read(display, link_m_reg) & DATA_LINK_M_N_MASK;
m_n->link_n = intel_de_read(display, link_n_reg) & DATA_LINK_M_N_MASK;
m_n->data_m = intel_de_read(display, data_m_reg) & DATA_LINK_M_N_MASK;
m_n->data_n = intel_de_read(display, data_n_reg) & DATA_LINK_M_N_MASK;
m_n->tu = REG_FIELD_GET(TU_SIZE_MASK, intel_de_read(display, data_m_reg)) + 1;
}
void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc,
enum transcoder transcoder,
struct intel_link_m_n *m_n)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct intel_display *display = to_intel_display(crtc);
enum pipe pipe = crtc->pipe;
if (DISPLAY_VER(dev_priv) >= 5)
intel_get_m_n(dev_priv, m_n,
PIPE_DATA_M1(dev_priv, transcoder),
PIPE_DATA_N1(dev_priv, transcoder),
PIPE_LINK_M1(dev_priv, transcoder),
PIPE_LINK_N1(dev_priv, transcoder));
if (DISPLAY_VER(display) >= 5)
intel_get_m_n(display, m_n,
PIPE_DATA_M1(display, transcoder),
PIPE_DATA_N1(display, transcoder),
PIPE_LINK_M1(display, transcoder),
PIPE_LINK_N1(display, transcoder));
else
intel_get_m_n(dev_priv, m_n,
intel_get_m_n(display, m_n,
PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe),
PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe));
}
@@ -3439,16 +3439,16 @@ void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc,
enum transcoder transcoder,
struct intel_link_m_n *m_n)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct intel_display *display = to_intel_display(crtc);
if (!intel_cpu_transcoder_has_m2_n2(dev_priv, transcoder))
if (!intel_cpu_transcoder_has_m2_n2(display, transcoder))
return;
intel_get_m_n(dev_priv, m_n,
PIPE_DATA_M2(dev_priv, transcoder),
PIPE_DATA_N2(dev_priv, transcoder),
PIPE_LINK_M2(dev_priv, transcoder),
PIPE_LINK_N2(dev_priv, transcoder));
intel_get_m_n(display, m_n,
PIPE_DATA_M2(display, transcoder),
PIPE_DATA_N2(display, transcoder),
PIPE_LINK_M2(display, transcoder),
PIPE_LINK_N2(display, transcoder));
}
static void ilk_get_pfit_config(struct intel_crtc_state *crtc_state)

6
drivers/gpu/drm/i915/display/intel_display.h
View File

@@ -481,15 +481,15 @@ int ilk_get_lanes_required(int target_clock, int link_bw, int bpp);
bool intel_fuzzy_clock_check(int clock1, int clock2);
void intel_zero_m_n(struct intel_link_m_n *m_n);
void intel_set_m_n(struct drm_i915_private *i915,
void intel_set_m_n(struct intel_display *display,
const struct intel_link_m_n *m_n,
i915_reg_t data_m_reg, i915_reg_t data_n_reg,
i915_reg_t link_m_reg, i915_reg_t link_n_reg);
void intel_get_m_n(struct drm_i915_private *i915,
void intel_get_m_n(struct intel_display *display,
struct intel_link_m_n *m_n,
i915_reg_t data_m_reg, i915_reg_t data_n_reg,
i915_reg_t link_m_reg, i915_reg_t link_n_reg);
bool intel_cpu_transcoder_has_m2_n2(struct drm_i915_private *dev_priv,
bool intel_cpu_transcoder_has_m2_n2(struct intel_display *display,
enum transcoder transcoder);
void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc,
enum transcoder cpu_transcoder,

3
drivers/gpu/drm/i915/display/intel_dp.c
View File

@@ -2943,7 +2943,6 @@ intel_dp_drrs_compute_config(struct intel_connector *connector,
int link_bpp_x16)
{
struct intel_display *display = to_intel_display(connector);
struct drm_i915_private *i915 = to_i915(connector->base.dev);
const struct drm_display_mode *downclock_mode =
intel_panel_downclock_mode(connector, &pipe_config->hw.adjusted_mode);
int pixel_clock;
@@ -2956,7 +2955,7 @@ intel_dp_drrs_compute_config(struct intel_connector *connector,
pipe_config->update_m_n = true;
if (!can_enable_drrs(connector, pipe_config, downclock_mode)) {
if (intel_cpu_transcoder_has_m2_n2(i915, pipe_config->cpu_transcoder))
if (intel_cpu_transcoder_has_m2_n2(display, pipe_config->cpu_transcoder))
intel_zero_m_n(&pipe_config->dp_m2_n2);
return;
}

8
drivers/gpu/drm/i915/display/intel_drrs.c
View File

@@ -68,12 +68,10 @@ const char *intel_drrs_type_str(enum drrs_type drrs_type)
bool intel_cpu_transcoder_has_drrs(struct intel_display *display,
enum transcoder cpu_transcoder)
{
struct drm_i915_private *i915 = to_i915(display->drm);
if (HAS_DOUBLE_BUFFERED_M_N(display))
return true;
return intel_cpu_transcoder_has_m2_n2(i915, cpu_transcoder);
return intel_cpu_transcoder_has_m2_n2(display, cpu_transcoder);
}
static void
@@ -110,12 +108,12 @@ bool intel_drrs_is_active(struct intel_crtc *crtc)
static void intel_drrs_set_state(struct intel_crtc *crtc,
enum drrs_refresh_rate refresh_rate)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct intel_display *display = to_intel_display(crtc);
if (refresh_rate == crtc->drrs.refresh_rate)
return;
if (intel_cpu_transcoder_has_m2_n2(dev_priv, crtc->drrs.cpu_transcoder))
if (intel_cpu_transcoder_has_m2_n2(display, crtc->drrs.cpu_transcoder))
intel_drrs_set_refresh_rate_pipeconf(crtc, refresh_rate);
else
intel_drrs_set_refresh_rate_m_n(crtc, refresh_rate);

16
drivers/gpu/drm/i915/display/intel_pch_display.c
View File

@@ -181,10 +181,10 @@ static void ibx_sanitize_pch_ports(struct drm_i915_private *dev_priv)
static void intel_pch_transcoder_set_m1_n1(struct intel_crtc *crtc,
const struct intel_link_m_n *m_n)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct intel_display *display = to_intel_display(crtc);
enum pipe pipe = crtc->pipe;
intel_set_m_n(dev_priv, m_n,
intel_set_m_n(display, m_n,
PCH_TRANS_DATA_M1(pipe), PCH_TRANS_DATA_N1(pipe),
PCH_TRANS_LINK_M1(pipe), PCH_TRANS_LINK_N1(pipe));
}
@@ -192,10 +192,10 @@ static void intel_pch_transcoder_set_m1_n1(struct intel_crtc *crtc,
static void intel_pch_transcoder_set_m2_n2(struct intel_crtc *crtc,
const struct intel_link_m_n *m_n)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct intel_display *display = to_intel_display(crtc);
enum pipe pipe = crtc->pipe;
intel_set_m_n(dev_priv, m_n,
intel_set_m_n(display, m_n,
PCH_TRANS_DATA_M2(pipe), PCH_TRANS_DATA_N2(pipe),
PCH_TRANS_LINK_M2(pipe), PCH_TRANS_LINK_N2(pipe));
}
@@ -203,10 +203,10 @@ static void intel_pch_transcoder_set_m2_n2(struct intel_crtc *crtc,
void intel_pch_transcoder_get_m1_n1(struct intel_crtc *crtc,
struct intel_link_m_n *m_n)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct intel_display *display = to_intel_display(crtc);
enum pipe pipe = crtc->pipe;
intel_get_m_n(dev_priv, m_n,
intel_get_m_n(display, m_n,
PCH_TRANS_DATA_M1(pipe), PCH_TRANS_DATA_N1(pipe),
PCH_TRANS_LINK_M1(pipe), PCH_TRANS_LINK_N1(pipe));
}
@@ -214,10 +214,10 @@ void intel_pch_transcoder_get_m1_n1(struct intel_crtc *crtc,
void intel_pch_transcoder_get_m2_n2(struct intel_crtc *crtc,
struct intel_link_m_n *m_n)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct intel_display *display = to_intel_display(crtc);
enum pipe pipe = crtc->pipe;
intel_get_m_n(dev_priv, m_n,
intel_get_m_n(display, m_n,
PCH_TRANS_DATA_M2(pipe), PCH_TRANS_DATA_N2(pipe),
PCH_TRANS_LINK_M2(pipe), PCH_TRANS_LINK_N2(pipe));
}