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arm64: dts: exynos: add initial support for exynosautov920 SoC
Samsung ExynosAutov920 is ARMv8-based automotive-oriented SoC. It has AE(Automotive Enhanced) IPs for safety. * Cortex-A78AE 10-cores * GIC-600AE This is minimal support for ExynosAutov920 SoC. * Enumerate all pinctrl nodes * Enable Chip-Id * Serial0 for console * PWM Since the clock driver is not yet implemented, it is supported as fixed-clock. Signed-off-by: Jaewon Kim <jaewon02.kim@samsung.com> Link: https://lore.kernel.org/r/20231208074527.50840-2-jaewon02.kim@samsung.com [krzysztof: Re-order nodes to match coding style: UFS reset pins, gpg/gpp in peric0 and peric1, all nodes in the soc@0; drop fallback compatibles from wakeup-interrupt-controller] Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
This commit is contained in:
Jaewon Kim
committed by
Krzysztof Kozlowski
Krzysztof Kozlowski
parent
5f257922c5
commit
c96dab1993
1266
arch/arm64/boot/dts/exynos/exynosautov920-pinctrl.dtsi
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1266
arch/arm64/boot/dts/exynos/exynosautov920-pinctrl.dtsi
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File diff suppressed because it is too large
Load Diff
312
arch/arm64/boot/dts/exynos/exynosautov920.dtsi
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312
arch/arm64/boot/dts/exynos/exynosautov920.dtsi
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Samsung's ExynosAutov920 SoC device tree source
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*
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* Copyright (c) 2023 Samsung Electronics Co., Ltd.
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*
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/soc/samsung,exynos-usi.h>
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/ {
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compatible = "samsung,exynosautov920";
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#address-cells = <2>;
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#size-cells = <1>;
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interrupt-parent = <&gic>;
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aliases {
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pinctrl0 = &pinctrl_alive;
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pinctrl1 = &pinctrl_aud;
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pinctrl2 = &pinctrl_hsi0;
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pinctrl3 = &pinctrl_hsi1;
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pinctrl4 = &pinctrl_hsi2;
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pinctrl5 = &pinctrl_hsi2ufs;
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pinctrl6 = &pinctrl_peric0;
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pinctrl7 = &pinctrl_peric1;
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};
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arm-pmu {
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compatible = "arm,cortex-a78-pmu";
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interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
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};
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xtcxo: clock {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-output-names = "oscclk";
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};
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/*
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* FIXME: Keep the stub clock for serial driver, until proper clock
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* driver is implemented.
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*/
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clock_usi: clock-usi {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <200000000>;
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clock-output-names = "usi";
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};
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cpus: cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&cpu0>;
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};
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core1 {
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cpu = <&cpu1>;
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};
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core2 {
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cpu = <&cpu2>;
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};
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core3 {
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cpu = <&cpu3>;
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};
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};
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cluster1 {
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core0 {
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cpu = <&cpu4>;
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};
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core1 {
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cpu = <&cpu5>;
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};
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core2 {
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cpu = <&cpu6>;
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};
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core3 {
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cpu = <&cpu7>;
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};
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};
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cluster2 {
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core0 {
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cpu = <&cpu8>;
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};
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core1 {
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cpu = <&cpu9>;
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};
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};
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};
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a78ae";
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reg = <0x0 0x0>;
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enable-method = "psci";
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};
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cpu1: cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a78ae";
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reg = <0x0 0x100>;
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enable-method = "psci";
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};
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cpu2: cpu@200 {
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device_type = "cpu";
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compatible = "arm,cortex-a78ae";
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reg = <0x0 0x200>;
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enable-method = "psci";
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};
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cpu3: cpu@300 {
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device_type = "cpu";
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compatible = "arm,cortex-a78ae";
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reg = <0x0 0x300>;
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enable-method = "psci";
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};
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cpu4: cpu@10000 {
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device_type = "cpu";
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compatible = "arm,cortex-a78ae";
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reg = <0x0 0x10000>;
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enable-method = "psci";
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};
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cpu5: cpu@10100 {
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device_type = "cpu";
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compatible = "arm,cortex-a78ae";
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reg = <0x0 0x10100>;
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enable-method = "psci";
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};
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cpu6: cpu@10200 {
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device_type = "cpu";
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compatible = "arm,cortex-a78ae";
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reg = <0x0 0x10200>;
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enable-method = "psci";
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};
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cpu7: cpu@10300 {
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device_type = "cpu";
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compatible = "arm,cortex-a78ae";
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reg = <0x0 0x10300>;
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enable-method = "psci";
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};
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cpu8: cpu@20000 {
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device_type = "cpu";
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compatible = "arm,cortex-a78ae";
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reg = <0x0 0x20000>;
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enable-method = "psci";
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};
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cpu9: cpu@20100 {
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device_type = "cpu";
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compatible = "arm,cortex-a78ae";
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reg = <0x0 0x20100>;
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enable-method = "psci";
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};
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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soc: soc@0 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x0 0x0 0x20000000>;
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chipid@10000000 {
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compatible = "samsung,exynosautov920-chipid",
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"samsung,exynos850-chipid";
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reg = <0x10000000 0x24>;
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};
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gic: interrupt-controller@10400000 {
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compatible = "arm,gic-v3";
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#interrupt-cells = <3>;
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#address-cells = <0>;
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interrupt-controller;
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reg = <0x10400000 0x10000>,
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<0x10460000 0x140000>;
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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};
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syscon_peric0: syscon@10820000 {
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compatible = "samsung,exynosautov920-peric0-sysreg",
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"syscon";
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reg = <0x10820000 0x2000>;
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};
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pinctrl_peric0: pinctrl@10830000 {
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compatible = "samsung,exynosautov920-pinctrl";
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reg = <0x10830000 0x10000>;
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interrupts = <GIC_SPI 753 IRQ_TYPE_LEVEL_HIGH>;
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};
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usi_0: usi@108800c0 {
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compatible = "samsung,exynosautov920-usi",
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"samsung,exynos850-usi";
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reg = <0x108800c0 0x20>;
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samsung,sysreg = <&syscon_peric0 0x1000>;
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samsung,mode = <USI_V2_UART>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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clocks = <&clock_usi>, <&clock_usi>;
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clock-names = "pclk", "ipclk";
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status = "disabled";
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serial_0: serial@10880000 {
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compatible = "samsung,exynosautov920-uart",
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"samsung,exynos850-uart";
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reg = <0x10880000 0xc0>;
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interrupts = <GIC_SPI 764 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&uart0_bus>;
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clocks = <&clock_usi>, <&clock_usi>;
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clock-names = "uart", "clk_uart_baud0";
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samsung,uart-fifosize = <256>;
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status = "disabled";
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};
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};
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pwm: pwm@109b0000 {
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compatible = "samsung,exynosautov920-pwm",
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"samsung,exynos4210-pwm";
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reg = <0x109b0000 0x100>;
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samsung,pwm-outputs = <0>, <1>, <2>, <3>;
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#pwm-cells = <3>;
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clocks = <&xtcxo>;
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clock-names = "timers";
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status = "disabled";
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};
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syscon_peric1: syscon@10c20000 {
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compatible = "samsung,exynosautov920-peric1-sysreg",
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"syscon";
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reg = <0x10c20000 0x2000>;
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};
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pinctrl_peric1: pinctrl@10c30000 {
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compatible = "samsung,exynosautov920-pinctrl";
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reg = <0x10c30000 0x10000>;
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interrupts = <GIC_SPI 781 IRQ_TYPE_LEVEL_HIGH>;
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};
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pinctrl_alive: pinctrl@11850000 {
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compatible = "samsung,exynosautov920-pinctrl";
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reg = <0x11850000 0x10000>;
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wakeup-interrupt-controller {
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compatible = "samsung,exynosautov920-wakeup-eint";
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};
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};
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pmu_system_controller: system-controller@11860000 {
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compatible = "samsung,exynosautov920-pmu",
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"samsung,exynos7-pmu","syscon";
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reg = <0x11860000 0x10000>;
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};
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pinctrl_hsi0: pinctrl@16040000 {
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compatible = "samsung,exynosautov920-pinctrl";
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reg = <0x16040000 0x10000>;
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interrupts = <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>;
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};
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pinctrl_hsi1: pinctrl@16450000 {
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compatible = "samsung,exynosautov920-pinctrl";
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reg = <0x16450000 0x10000>;
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interrupts = <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>;
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};
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pinctrl_hsi2: pinctrl@16c10000 {
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compatible = "samsung,exynosautov920-pinctrl";
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reg = <0x16c10000 0x10000>;
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interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
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};
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pinctrl_hsi2ufs: pinctrl@16d20000 {
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compatible = "samsung,exynosautov920-pinctrl";
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reg = <0x16d20000 0x10000>;
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interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
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};
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pinctrl_aud: pinctrl@1a460000 {
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compatible = "samsung,exynosautov920-pinctrl";
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reg = <0x1a460000 0x10000>;
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};
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
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};
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};
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#include "exynosautov920-pinctrl.dtsi"
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