mirrors/linux
1
0
Fork 0
mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git synced 2026-05-02 06:17:26 -04:00
Code Issues Packages Projects Releases Wiki Activity

drm/i915: Move display_mmio_offset under INTEL_INFO->display

Browse Source 
The display register offsets are display stuff so stick
into the display portion of the device info.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220623130900.26078-4-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
This commit is contained in:
Ville Syrjälä
2022-06-23 16:08:54 +03:00
parent 12d7455372
commit c92df6aa39
3 changed files with 6 additions and 5 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/gpu/drm/i915/i915_pci.c
View File

@@ -529,7 +529,7 @@ static const struct intel_device_info vlv_info = {
.has_snoop = true,
.has_coherent_ggtt = false,
.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0),
.display_mmio_offset = VLV_DISPLAY_BASE,
.display.mmio_offset = VLV_DISPLAY_BASE,
I9XX_PIPE_OFFSETS,
I9XX_CURSOR_OFFSETS,
I965_COLORS,
@@ -627,7 +627,7 @@ static const struct intel_device_info chv_info = {
.has_reset_engine = 1,
.has_snoop = true,
.has_coherent_ggtt = false,
.display_mmio_offset = VLV_DISPLAY_BASE,
.display.mmio_offset = VLV_DISPLAY_BASE,
CHV_PIPE_OFFSETS,
CHV_CURSOR_OFFSETS,
CHV_COLORS,

2
drivers/gpu/drm/i915/i915_reg.h
View File

@@ -115,7 +115,7 @@
* #define GEN8_BAR _MMIO(0xb888)
*/
#define DISPLAY_MMIO_BASE(dev_priv) (INTEL_INFO(dev_priv)->display_mmio_offset)
#define DISPLAY_MMIO_BASE(dev_priv) (INTEL_INFO(dev_priv)->display.mmio_offset)
/*
* Given the first two numbers __a and __b of arbitrarily many evenly spaced

5
drivers/gpu/drm/i915/intel_device_info.h
View File

@@ -208,8 +208,6 @@ struct intel_device_info {
u32 memory_regions; /* regions supported by the HW */
u32 display_mmio_offset;
u8 gt; /* GT number, 0 if undefined */
#define DEFINE_FLAG(name) u8 name:1
@@ -234,6 +232,9 @@ struct intel_device_info {
DEV_INFO_DISPLAY_FOR_EACH_FLAG(DEFINE_FLAG);
#undef DEFINE_FLAG
/* Global register offset for the display engine */
u32 mmio_offset;
/* Register offsets for the various display pipes and transcoders */
int pipe_offsets[I915_MAX_TRANSCODERS];
int trans_offsets[I915_MAX_TRANSCODERS];