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drm/amd/display: For no plane case set pstate support in validation

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- Previously update_clocks was overriding pstate support if
  it checked that there were no planes
- However, P-State support should be determined in validation
  phase instead
- This fixes an issue where a transition from FPO -> no planes
  expects UCLK MAX, but update_clocks was overriding to set
  UCLK to min

Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alvin Lee
2023-04-12 15:42:41 -04:00
committed by Alex Deucher
parent 9c25ab167d
commit c8cefb99fc
4 changed files with 11 additions and 9 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c
View File

@@ -206,7 +206,6 @@ static void dcn3_update_clocks(struct clk_mgr *clk_mgr_base,
bool force_reset = false;
bool update_uclk = false;
bool p_state_change_support;
int total_plane_count;
if (dc->work_arounds.skip_clock_update || !clk_mgr->smu_present)
return;
@@ -247,8 +246,7 @@ static void dcn3_update_clocks(struct clk_mgr *clk_mgr_base,
clk_mgr_base->clks.socclk_khz = new_clocks->socclk_khz;
clk_mgr_base->clks.prev_p_state_change_support = clk_mgr_base->clks.p_state_change_support;
total_plane_count = clk_mgr_helper_get_active_plane_cnt(dc, context);
p_state_change_support = new_clocks->p_state_change_support || (total_plane_count == 0);
p_state_change_support = new_clocks->p_state_change_support;
// invalidate the current P-State forced min in certain dc_mode_softmax situations
if (dc->clk_mgr->dc_mode_softmax_enabled && safe_to_lower && !p_state_change_support) {

7
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
View File

@@ -459,7 +459,6 @@ static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base,
bool update_uclk = false, update_fclk = false;
bool p_state_change_support;
bool fclk_p_state_change_support;
int total_plane_count;
if (dc->work_arounds.skip_clock_update)
return;
@@ -488,8 +487,7 @@ static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base,
clk_mgr_base->clks.fclk_prev_p_state_change_support = clk_mgr_base->clks.fclk_p_state_change_support;
total_plane_count = clk_mgr_helper_get_active_plane_cnt(dc, context);
fclk_p_state_change_support = new_clocks->fclk_p_state_change_support || (total_plane_count == 0);
fclk_p_state_change_support = new_clocks->fclk_p_state_change_support;
if (should_update_pstate_support(safe_to_lower, fclk_p_state_change_support, clk_mgr_base->clks.fclk_p_state_change_support)) {
clk_mgr_base->clks.fclk_p_state_change_support = fclk_p_state_change_support;
@@ -528,8 +526,7 @@ static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base,
dcn32_smu_send_cab_for_uclk_message(clk_mgr, clk_mgr_base->clks.num_ways);
}
p_state_change_support = new_clocks->p_state_change_support || (total_plane_count == 0);
p_state_change_support = new_clocks->p_state_change_support;
if (should_update_pstate_support(safe_to_lower, p_state_change_support, clk_mgr_base->clks.p_state_change_support)) {
clk_mgr_base->clks.p_state_change_support = p_state_change_support;

8
drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
View File

@@ -1042,7 +1042,7 @@ void dcn20_calculate_dlg_params(struct dc *dc,
int pipe_cnt,
int vlevel)
{
int i, pipe_idx;
int i, pipe_idx, active_hubp_count = 0;
dc_assert_fp_enabled();
@@ -1078,6 +1078,8 @@ void dcn20_calculate_dlg_params(struct dc *dc,
for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
if (!context->res_ctx.pipe_ctx[i].stream)
continue;
if (context->res_ctx.pipe_ctx[i].plane_state)
active_hubp_count++;
pipes[pipe_idx].pipe.dest.vstartup_start = get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
pipes[pipe_idx].pipe.dest.vupdate_offset = get_vupdate_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
pipes[pipe_idx].pipe.dest.vupdate_width = get_vupdate_width(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
@@ -1104,6 +1106,10 @@ void dcn20_calculate_dlg_params(struct dc *dc,
pipe_idx++;
}
/* If DCN isn't making memory requests we can allow pstate change */
if (!active_hubp_count) {
context->bw_ctx.bw.dcn.clk.p_state_change_support = true;
}
/*save a original dppclock copy*/
context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.dppclk_khz;
context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz;

1
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
View File

@@ -1433,6 +1433,7 @@ static void dcn32_calculate_dlg_params(struct dc *dc, struct dc_state *context,
context->bw_ctx.bw.dcn.clk.dramclk_khz = 0;
context->bw_ctx.bw.dcn.clk.fclk_khz = 0;
context->bw_ctx.bw.dcn.clk.p_state_change_support = true;
context->bw_ctx.bw.dcn.clk.fclk_p_state_change_support = true;
}
/*save a original dppclock copy*/
context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.dppclk_khz;