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spi: dw: Introduce spi_frf and STD_SPI

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The DW APB SSI controllers of v4.x and newer and DW AHB SSI controllers
supports enhanced SPI modes which can be defined from SPI_FRF of
DW_SPI_CTRLR0 register. Without enhanced mode, these controllers will
work in the standard spi mode.

Signed-off-by: Sudip Mukherjee <sudip.mukherjee@sifive.com>
Co-developed-by: Changhuang Liang <changhuang.liang@starfivetech.com>
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
Link: https://patch.msgid.link/20260803124044.156998-2-changhuang.liang@starfivetech.com
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Sudip Mukherjee
2026-08-03 05:40:34 -07:00
committed by Mark Brown
parent 075b74841b
commit c87b4ba097
2 changed files with 19 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

13
drivers/spi/spi-dw-core.c
View File

@@ -330,6 +330,16 @@ void dw_spi_update_config(struct dw_spi *dws, struct spi_device *spi,
/* CTRLR0[11:10] Transfer Mode */
cr0 |= FIELD_PREP(DW_HSSI_CTRLR0_TMOD_MASK, cfg->tmode);
if (dw_spi_ver_is_ge(dws, HSSI, 103A)) {
cr0 &= ~DW_HSSI_CTRLR0_SPI_FRF_MASK;
cr0 |= FIELD_PREP(DW_HSSI_CTRLR0_SPI_FRF_MASK,
cfg->spi_frf);
} else if (dw_spi_ver_is_ge(dws, PSSI, 400A)) {
cr0 &= ~DW_PSSI_CTRLR0_SPI_FRF_MASK;
cr0 |= FIELD_PREP(DW_PSSI_CTRLR0_SPI_FRF_MASK,
cfg->spi_frf);
}
dw_writel(dws, DW_SPI_CTRLR0, cr0);
if (spi_controller_is_target(dws->ctlr))
@@ -422,6 +432,7 @@ static int dw_spi_transfer_one(struct spi_controller *ctlr,
.tmode = DW_SPI_CTRLR0_TMOD_TR,
.dfs = transfer->bits_per_word,
.freq = transfer->speed_hz,
.spi_frf = DW_SPI_CTRLR0_SPI_FRF_STD_SPI,
};
int ret;
@@ -677,7 +688,7 @@ static void dw_spi_stop_mem_op(struct dw_spi *dws, struct spi_device *spi)
static int dw_spi_exec_mem_op(struct spi_mem *mem, const struct spi_mem_op *op)
{
struct dw_spi *dws = spi_controller_get_devdata(mem->spi->controller);
struct dw_spi_cfg cfg;
struct dw_spi_cfg cfg = {0};
unsigned long flags;
int ret;

7
drivers/spi/spi-dw.h
View File

@@ -17,6 +17,9 @@
/* Synopsys DW SSI component versions (FourCC sequence) */
#define DW_HSSI_102A 0x3130322a
#define DW_HSSI_103A 0x3130332a
#define DW_HSSI_200A 0x3230302a
#define DW_PSSI_400A 0x3430302a
/* DW SSI IP-core ID and version check helpers */
#define dw_spi_ip_is(_dws, _ip) \
@@ -94,6 +97,9 @@
#define DW_HSSI_CTRLR0_TMOD_MASK GENMASK(11, 10)
#define DW_HSSI_CTRLR0_SRL BIT(13)
#define DW_HSSI_CTRLR0_MST BIT(31)
#define DW_HSSI_CTRLR0_SPI_FRF_MASK GENMASK(23, 22)
#define DW_PSSI_CTRLR0_SPI_FRF_MASK GENMASK(22, 21)
#define DW_SPI_CTRLR0_SPI_FRF_STD_SPI 0x0
/* Bit fields in CTRLR1 */
#define DW_SPI_NDF_MASK GENMASK(15, 0)
@@ -135,6 +141,7 @@ struct dw_spi_cfg {
u8 dfs;
u32 ndf;
u32 freq;
u8 spi_frf;
};
struct dw_spi;