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drm/i915/dsc: Add helper for writing DSC Selective Update ET parameters

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There are slice row per frame and pic height configuration in DSC Selective
Update Parameter Set 1 register. Add helper for configuring these.

v2:
  - Add WARN_ON_ONCE if vdsc instances per pipe > 2
  - instead of checking vdsc instances per pipe being > 1 check == 2

Bspec: 71709
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Link: https://patch.msgid.link/20260304113011.626542-4-jouni.hogander@intel.com
This commit is contained in:
Jouni Högander
2026-03-04 13:30:10 +02:00
parent 24f96d903d
commit c8698d61ae
2 changed files with 26 additions and 0 deletions
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23
drivers/gpu/drm/i915/display/intel_vdsc.c
View File

@@ -820,6 +820,29 @@ void intel_dsc_dp_pps_write(struct intel_encoder *encoder,
sizeof(dp_dsc_pps_sdp));
}
void intel_dsc_su_et_parameters_configure(struct intel_dsb *dsb, struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state, int su_lines)
{
struct intel_display *display = to_intel_display(crtc_state);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
enum pipe pipe = crtc->pipe;
int vdsc_instances_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state);
int slice_row_per_frame = su_lines / vdsc_cfg->slice_height;
u32 val;
drm_WARN_ON_ONCE(display->drm, su_lines % vdsc_cfg->slice_height);
drm_WARN_ON_ONCE(display->drm, vdsc_instances_per_pipe > 2);
val = DSC_SUPS0_SU_SLICE_ROW_PER_FRAME(slice_row_per_frame);
val |= DSC_SUPS0_SU_PIC_HEIGHT(su_lines);
intel_de_write_dsb(display, dsb, LNL_DSC0_SU_PARAMETER_SET_0(pipe), val);
if (vdsc_instances_per_pipe == 2)
intel_de_write_dsb(display, dsb, LNL_DSC1_SU_PARAMETER_SET_0(pipe), val);
}
static i915_reg_t dss_ctl1_reg(struct intel_crtc *crtc, enum transcoder cpu_transcoder)
{
return is_pipe_dsc(crtc, cpu_transcoder) ?

3
drivers/gpu/drm/i915/display/intel_vdsc.h
View File

@@ -14,6 +14,7 @@ enum transcoder;
struct intel_crtc;
struct intel_crtc_state;
struct intel_display;
struct intel_dsb;
struct intel_dsc_slice_config;
struct intel_encoder;
@@ -37,6 +38,8 @@ void intel_dsc_dsi_pps_write(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state);
void intel_dsc_dp_pps_write(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state);
void intel_dsc_su_et_parameters_configure(struct intel_dsb *dsb, struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state, int su_lines);
void intel_vdsc_state_dump(struct drm_printer *p, int indent,
const struct intel_crtc_state *crtc_state);
int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state);