mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2025-12-28 05:34:13 -05:00
Merge tag 'socfpga_dts_updates_for_v6.19' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into soc/dt
SoCFPGA DTS updates for v6.19 - Add 4-bit SPI bus width(n5x, stratix10, agilex and agilex5) - Agilex5 updates: - Add GMAC0 for NAND daughter card - Add SMMU support - Add VGIC maintenance interrupt - Add L2 and L3 cache - Add support for the 013b board - Add I3C support - Add support for the Enclustra Mercury+ SA1 SoM based on Cyclone5 - Add support for Agilex3 board(a variant of the Agilex5 board) - dt-bindings update: - Document iommu in cdns,hp-nfc, snps,dw-axi-dmac and Agilex5 - Document Enclustra Mercury SA1 and AA1 boards - Document Agilex5 013b board - Document Agilex3 board - Fix dtbs_check warnings: - stratix10-swvp - Agilex(NAND and Clock manager) - Move sdmmc-ecc to base DTSI file(Stratix10) * tag 'socfpga_dts_updates_for_v6.19' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux: (35 commits) arm64: dts: socfpga: agilex5: update qspi partitions for 013b board arm64: dts: socfpga: add Agilex3 board dt-bindings: intel: Add Agilex3 SoCFPGA board arm64: dts: intel: agilex5: Add Altera compatible for I3C controllers arm64: dts: socfpga: Add Agilex5 SVC node with memory region dt-bindings: firmware: svc: Add IOMMU support for Agilex5 arm64: dts: socfpga: agilex5: Add SMMU-V3-PMCG nodes arm64: dts: socfpga: agilex5: Add L2 and L3 cache arm64: dts: socfpga: agilex5: fix CHECK_DTBS warning for NAND arm64: dts: socfpga: agilex5: add support for 013b board dt-bindings: intel: Add Agilex5 SoCFPGA 013b board arm64: dts: socfpga: agilex5: add VGIC maintenance interrupt arm64: dts: socfpga: agilex: fix dtbs_check warning for NAND arm64: dts: socfpga: agilex: fix dtbs_check warning for clock manager arm64: dts: socfpga: stratix10-swvp: fix dtbs_check warnings swvp arm64: dts: socfpga: move sdmmc-ecc to the base DTSI file ARM: dts: socfpga: add Enclustra SoM dts files dt-bindings: altera: removal of generic PE1 dts ARM: dts: socfpga: removal of generic PE1 dts dt-bindings: altera: add Mercury AA1 variants ... Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
@@ -31,7 +31,9 @@ properties:
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- description: Mercury+ AA1 boards
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items:
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- enum:
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- enclustra,mercury-pe1
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- enclustra,mercury-aa1-pe1
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- enclustra,mercury-aa1-pe3
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- enclustra,mercury-aa1-st1
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- google,chameleon-v3
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- const: enclustra,mercury-aa1
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- const: altr,socfpga-arria10
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@@ -52,6 +54,26 @@ properties:
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- const: altr,socfpga-cyclone5
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- const: altr,socfpga
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- description: Mercury SA1 boards
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items:
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- enum:
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- enclustra,mercury-sa1-pe1
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- enclustra,mercury-sa1-pe3
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- enclustra,mercury-sa1-st1
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- const: enclustra,mercury-sa1
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- const: altr,socfpga-cyclone5
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- const: altr,socfpga
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- description: Mercury+ SA2 boards
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items:
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- enum:
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- enclustra,mercury-sa2-pe1
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- enclustra,mercury-sa2-pe3
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- enclustra,mercury-sa2-st1
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- const: enclustra,mercury-sa2
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- const: altr,socfpga-cyclone5
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- const: altr,socfpga
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- description: Stratix 10 boards
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items:
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- enum:
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@@ -21,10 +21,17 @@ properties:
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- intel,socfpga-agilex-n6000
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- intel,socfpga-agilex-socdk
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- const: intel,socfpga-agilex
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- description: Agilex3 boards
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items:
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- enum:
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- intel,socfpga-agilex3-socdk
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- const: intel,socfpga-agilex3
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- const: intel,socfpga-agilex5
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- description: Agilex5 boards
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items:
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- enum:
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- intel,socfpga-agilex5-socdk
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- intel,socfpga-agilex5-socdk-013b
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- intel,socfpga-agilex5-socdk-nand
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- const: intel,socfpga-agilex5
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@@ -42,6 +42,9 @@ properties:
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minItems: 1
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maxItems: 8
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iommus:
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maxItems: 1
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clocks:
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items:
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- description: Bus Clock
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@@ -34,6 +34,7 @@ properties:
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enum:
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- intel,stratix10-svc
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- intel,agilex-svc
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- intel,agilex5-svc
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method:
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description: |
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@@ -54,6 +55,9 @@ properties:
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reserved memory region for the service layer driver to
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communicate with the secure device manager.
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iommus:
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maxItems: 1
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fpga-mgr:
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$ref: /schemas/fpga/intel,stratix10-soc-fpga-mgr.yaml
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description: Optional child node for fpga manager to perform fabric configuration.
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@@ -63,6 +67,17 @@ required:
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- method
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- memory-region
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allOf:
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- if:
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properties:
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compatible:
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contains:
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enum:
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- intel,agilex5-svc
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then:
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required:
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- iommus
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additionalProperties: false
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examples:
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@@ -40,6 +40,9 @@ properties:
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dmas:
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maxItems: 1
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iommus:
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maxItems: 1
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cdns,board-delay-ps:
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description: |
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Estimated Board delay. The value includes the total round trip
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@@ -2,7 +2,30 @@
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dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += \
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socfpga_arria5_socdk.dtb \
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socfpga_arria10_chameleonv3.dtb \
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socfpga_arria10_mercury_pe1.dtb \
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socfpga_arria10_mercury_aa1_pe1_emmc.dtb \
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socfpga_arria10_mercury_aa1_pe1_qspi.dtb \
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socfpga_arria10_mercury_aa1_pe1_sdmmc.dtb \
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socfpga_arria10_mercury_aa1_pe3_emmc.dtb \
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socfpga_arria10_mercury_aa1_pe3_qspi.dtb \
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socfpga_arria10_mercury_aa1_pe3_sdmmc.dtb \
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socfpga_arria10_mercury_aa1_st1_emmc.dtb \
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socfpga_arria10_mercury_aa1_st1_qspi.dtb \
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socfpga_arria10_mercury_aa1_st1_sdmmc.dtb \
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socfpga_cyclone5_mercury_sa1_pe1_emmc.dtb \
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socfpga_cyclone5_mercury_sa1_pe1_qspi.dtb \
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socfpga_cyclone5_mercury_sa1_pe1_sdmmc.dtb \
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socfpga_cyclone5_mercury_sa1_pe3_emmc.dtb \
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socfpga_cyclone5_mercury_sa1_pe3_qspi.dtb \
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socfpga_cyclone5_mercury_sa1_pe3_sdmmc.dtb \
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socfpga_cyclone5_mercury_sa1_st1_emmc.dtb \
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socfpga_cyclone5_mercury_sa1_st1_qspi.dtb \
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socfpga_cyclone5_mercury_sa1_st1_sdmmc.dtb \
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socfpga_cyclone5_mercury_sa2_pe1_qspi.dtb \
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socfpga_cyclone5_mercury_sa2_pe1_sdmmc.dtb \
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socfpga_cyclone5_mercury_sa2_pe3_qspi.dtb \
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socfpga_cyclone5_mercury_sa2_pe3_sdmmc.dtb \
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socfpga_cyclone5_mercury_sa2_st1_qspi.dtb \
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socfpga_cyclone5_mercury_sa2_st1_sdmmc.dtb \
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socfpga_arria10_socdk_nand.dtb \
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socfpga_arria10_socdk_qspi.dtb \
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socfpga_arria10_socdk_sdmmc.dtb \
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@@ -7,12 +7,14 @@
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/ {
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model = "Enclustra Mercury AA1";
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compatible = "enclustra,mercury-aa1", "altr,socfpga-arria10", "altr,socfpga";
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model = "Enclustra Mercury+ AA1";
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compatible = "enclustra,mercury-aa1",
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"altr,socfpga-arria10", "altr,socfpga";
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aliases {
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ethernet0 = &gmac0;
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serial1 = &uart1;
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spi0 = &qspi;
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};
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memory@0 {
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@@ -24,52 +26,102 @@ memory@0 {
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chosen {
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stdout-path = "serial1:115200n8";
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};
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/* Adjusted the i2c labels to use generic base-board dtsi files for
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* Enclustra Arria10 and Cyclone5 SoMs.
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*
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* The set of i2c0 and i2c1 labels defined in socfpga_cyclone5.dtsi and in
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* socfpga_arria10.dtsi do not allow for using the same base-board .dtsi
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* fragments. Thus define generic labels here to match the correct i2c
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* bus in a generic base-board .dtsi file.
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*/
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soc {
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i2c_encl: i2c@ffc02300 {
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};
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i2c_encl_fpga: i2c@ffc02200 {
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};
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};
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};
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&i2c_encl {
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status = "okay";
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i2c-sda-hold-time-ns = <300>;
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clock-frequency = <100000>;
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atsha204a: crypto@64 {
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compatible = "atmel,atsha204a";
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reg = <0x64>;
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};
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isl12022: rtc@6f {
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compatible = "isil,isl12022";
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reg = <0x6f>;
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};
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};
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&i2c_encl_fpga {
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i2c-sda-hold-time-ns = <300>;
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status = "disabled";
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};
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&gmac0 {
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phy-mode = "rgmii";
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status = "okay";
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phy-mode = "rgmii-id";
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phy-addr = <0xffffffff>; /* probe for phy addr */
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max-frame-size = <3800>;
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phy-handle = <&phy3>;
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/delete-property/ mac-address;
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,dwmac-mdio";
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phy3: ethernet-phy@3 {
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txd0-skew-ps = <0>; /* -420ps */
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txd1-skew-ps = <0>; /* -420ps */
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txd2-skew-ps = <0>; /* -420ps */
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txd3-skew-ps = <0>; /* -420ps */
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reg = <3>;
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/* Add 2ns RX clock delay (1.2ns + 0.78ns)*/
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rxc-skew-ps = <1680>; /* 780ps */
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rxd0-skew-ps = <420>; /* 0ps */
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rxd1-skew-ps = <420>; /* 0ps */
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rxd2-skew-ps = <420>; /* 0ps */
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rxd3-skew-ps = <420>; /* 0ps */
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txen-skew-ps = <0>; /* -420ps */
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txc-skew-ps = <1860>; /* 960ps */
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rxdv-skew-ps = <420>; /* 0ps */
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rxc-skew-ps = <1680>; /* 780ps */
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reg = <3>;
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/* Add 1.38ns TX clock delay (0.96ns + 0.42ns)*/
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txc-skew-ps = <1860>; /* 960ps */
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txd0-skew-ps = <0>; /* -420ps */
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txd1-skew-ps = <0>; /* -420ps */
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txd2-skew-ps = <0>; /* -420ps */
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txd3-skew-ps = <0>; /* -420ps */
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txen-skew-ps = <0>; /* -420ps */
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};
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};
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};
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&i2c1 {
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atsha204a: crypto@64 {
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compatible = "atmel,atsha204a";
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reg = <0x64>;
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};
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&gpio0 {
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status = "okay";
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};
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isl12022: isl12022@6f {
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compatible = "isil,isl12022";
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reg = <0x6f>;
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};
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&gpio1 {
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status = "okay";
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};
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&gpio2 {
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status = "okay";
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};
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&uart0 {
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status = "disabled";
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};
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&uart1 {
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status = "okay";
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};
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/* Following mappings are taken from arria10 socdk dts */
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&mmc {
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status = "okay";
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cap-sd-highspeed;
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broken-cd;
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bus-width = <4>;
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@@ -79,3 +131,50 @@ &mmc {
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&osc1 {
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clock-frequency = <33330000>;
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};
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&eccmgr {
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sdmmca-ecc@ff8c2c00 {
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compatible = "altr,socfpga-sdmmc-ecc";
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reg = <0xff8c2c00 0x400>;
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altr,ecc-parent = <&mmc>;
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interrupts = <15 IRQ_TYPE_LEVEL_HIGH>,
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<47 IRQ_TYPE_LEVEL_HIGH>,
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<16 IRQ_TYPE_LEVEL_HIGH>,
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<48 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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|
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&qspi {
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status = "okay";
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flash0: flash@0 {
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u-boot,dm-pre-reloc;
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-rx-bus-width = <4>;
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spi-tx-bus-width = <4>;
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spi-max-frequency = <10000000>;
|
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|
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cdns,read-delay = <4>;
|
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cdns,tshsl-ns = <50>;
|
||||
cdns,tsd2d-ns = <50>;
|
||||
cdns,tchsh-ns = <4>;
|
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cdns,tslch-ns = <4>;
|
||||
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||||
partition@raw {
|
||||
label = "Flash Raw";
|
||||
reg = <0x0 0x4000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&watchdog1 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&usb0 {
|
||||
status = "okay";
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
||||
@@ -0,0 +1,16 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+ OR MIT
|
||||
/*
|
||||
* Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "socfpga_arria10_mercury_aa1.dtsi"
|
||||
#include "socfpga_enclustra_mercury_pe1.dtsi"
|
||||
#include "socfpga_enclustra_mercury_bootmode_emmc.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Enclustra Mercury SA1 on Mercury+ PE1 Base Board";
|
||||
compatible = "enclustra,mercury-sa1-pe1", "enclustra,mercury-sa1",
|
||||
"altr,socfpga-cyclone5", "altr,socfpga";
|
||||
};
|
||||
@@ -0,0 +1,16 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+ OR MIT
|
||||
/*
|
||||
* Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "socfpga_arria10_mercury_aa1.dtsi"
|
||||
#include "socfpga_enclustra_mercury_pe1.dtsi"
|
||||
#include "socfpga_enclustra_mercury_bootmode_qspi.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Enclustra Mercury+ AA1 on Mercury+ PE1 Base Board";
|
||||
compatible = "enclustra,mercury-aa1-pe1", "enclustra,mercury-aa1",
|
||||
"altr,socfpga-arria10", "altr,socfpga";
|
||||
};
|
||||
@@ -0,0 +1,16 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+ OR MIT
|
||||
/*
|
||||
* Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "socfpga_arria10_mercury_aa1.dtsi"
|
||||
#include "socfpga_enclustra_mercury_pe1.dtsi"
|
||||
#include "socfpga_enclustra_mercury_bootmode_sdmmc.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Enclustra Mercury+ AA1 on Mercury+ PE1 Base Board";
|
||||
compatible = "enclustra,mercury-aa1-pe1", "enclustra,mercury-aa1",
|
||||
"altr,socfpga-arria10", "altr,socfpga";
|
||||
};
|
||||
@@ -0,0 +1,16 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+ OR MIT
|
||||
/*
|
||||
* Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "socfpga_arria10_mercury_aa1.dtsi"
|
||||
#include "socfpga_enclustra_mercury_pe3.dtsi"
|
||||
#include "socfpga_enclustra_mercury_bootmode_emmc.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Enclustra Mercury+ AA1 on Mercury+ PE3 Base Board";
|
||||
compatible = "enclustra,mercury-aa1-pe3", "enclustra,mercury-aa1",
|
||||
"altr,socfpga-arria10", "altr,socfpga";
|
||||
};
|
||||
@@ -0,0 +1,16 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+ OR MIT
|
||||
/*
|
||||
* Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "socfpga_arria10_mercury_aa1.dtsi"
|
||||
#include "socfpga_enclustra_mercury_pe3.dtsi"
|
||||
#include "socfpga_enclustra_mercury_bootmode_qspi.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Enclustra Mercury+ AA1 on Mercury+ PE3 Base Board";
|
||||
compatible = "enclustra,mercury-aa1-pe3", "enclustra,mercury-aa1",
|
||||
"altr,socfpga-arria10", "altr,socfpga";
|
||||
};
|
||||
@@ -0,0 +1,16 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+ OR MIT
|
||||
/*
|
||||
* Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "socfpga_arria10_mercury_aa1.dtsi"
|
||||
#include "socfpga_enclustra_mercury_pe3.dtsi"
|
||||
#include "socfpga_enclustra_mercury_bootmode_sdmmc.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Enclustra Mercury+ AA1 on Mercury+ PE3 Base Board";
|
||||
compatible = "enclustra,mercury-aa1-pe3", "enclustra,mercury-aa1",
|
||||
"altr,socfpga-arria10", "altr,socfpga";
|
||||
};
|
||||
@@ -0,0 +1,16 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+ OR MIT
|
||||
/*
|
||||
* Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "socfpga_arria10_mercury_aa1.dtsi"
|
||||
#include "socfpga_enclustra_mercury_st1.dtsi"
|
||||
#include "socfpga_enclustra_mercury_bootmode_emmc.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Enclustra Mercury+ AA1 on Mercury+ ST1 Base Board";
|
||||
compatible = "enclustra,mercury-aa1-st1", "enclustra,mercury-aa1",
|
||||
"altr,socfpga-arria10", "altr,socfpga";
|
||||
};
|
||||
@@ -0,0 +1,16 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+ OR MIT
|
||||
/*
|
||||
* Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "socfpga_arria10_mercury_aa1.dtsi"
|
||||
#include "socfpga_enclustra_mercury_st1.dtsi"
|
||||
#include "socfpga_enclustra_mercury_bootmode_qspi.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Enclustra Mercury+ AA1 on Mercury+ ST1 Base Board";
|
||||
compatible = "enclustra,mercury-aa1-st1", "enclustra,mercury-aa1",
|
||||
"altr,socfpga-arria10", "altr,socfpga";
|
||||
};
|
||||
@@ -0,0 +1,16 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+ OR MIT
|
||||
/*
|
||||
* Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "socfpga_arria10_mercury_aa1.dtsi"
|
||||
#include "socfpga_enclustra_mercury_st1.dtsi"
|
||||
#include "socfpga_enclustra_mercury_bootmode_sdmmc.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Enclustra Mercury+ AA1 on Mercury+ ST1 Base Board";
|
||||
compatible = "enclustra,mercury-aa1-st1", "enclustra,mercury-aa1",
|
||||
"altr,socfpga-arria10", "altr,socfpga";
|
||||
};
|
||||
@@ -1,55 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright 2023 Steffen Trumtrar <kernel@pengutronix.de>
|
||||
*/
|
||||
/dts-v1/;
|
||||
#include "socfpga_arria10_mercury_aa1.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Enclustra Mercury+ PE1";
|
||||
compatible = "enclustra,mercury-pe1", "enclustra,mercury-aa1",
|
||||
"altr,socfpga-arria10", "altr,socfpga";
|
||||
|
||||
aliases {
|
||||
ethernet0 = &gmac0;
|
||||
serial0 = &uart0;
|
||||
serial1 = &uart1;
|
||||
};
|
||||
};
|
||||
|
||||
&gmac0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpio0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpio1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpio2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mmc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb0 {
|
||||
status = "okay";
|
||||
dr_mode = "host";
|
||||
};
|
||||
@@ -0,0 +1,143 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+ OR MIT
|
||||
/*
|
||||
* Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com
|
||||
*/
|
||||
|
||||
#include "socfpga_cyclone5.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Enclustra Mercury SA1";
|
||||
compatible = "altr,socfpga-cyclone5", "altr,socfpga";
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
aliases {
|
||||
ethernet0 = &gmac1;
|
||||
};
|
||||
|
||||
/* Adjusted the i2c labels to use generic base-board dtsi files for
|
||||
* Enclustra Arria10 and Cyclone5 SoMs.
|
||||
*
|
||||
* The set of i2c0 and i2c1 labels defined in socfpga_cyclone5.dtsi and in
|
||||
* socfpga_arria10.dtsi do not allow for using the same base-board .dtsi
|
||||
* fragments. Thus define generic labels here to match the correct i2c
|
||||
* bus in a generic base-board .dtsi file.
|
||||
*/
|
||||
soc {
|
||||
i2c_encl: i2c@ffc04000 {
|
||||
};
|
||||
i2c_encl_fpga: i2c@ffc05000 {
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
name = "memory";
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x40000000>; /* 1GB */
|
||||
};
|
||||
};
|
||||
|
||||
&osc1 {
|
||||
clock-frequency = <50000000>;
|
||||
};
|
||||
|
||||
&i2c_encl {
|
||||
i2c-sda-hold-time-ns = <300>;
|
||||
clock-frequency = <100000>;
|
||||
status = "okay";
|
||||
|
||||
isl12020: rtc@6f {
|
||||
compatible = "isil,isl12022";
|
||||
reg = <0x6f>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c_encl_fpga {
|
||||
i2c-sda-hold-time-ns = <300>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
clock-frequency = <100000000>;
|
||||
};
|
||||
|
||||
&mmc0 {
|
||||
status = "okay";
|
||||
/delete-property/ cap-mmc-highspeed;
|
||||
/delete-property/ cap-sd-highspeed;
|
||||
};
|
||||
|
||||
&qspi {
|
||||
status = "okay";
|
||||
|
||||
flash0: flash@0 {
|
||||
u-boot,dm-pre-reloc;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
|
||||
spi-rx-bus-width = <4>;
|
||||
spi-tx-bus-width = <4>;
|
||||
spi-max-frequency = <10000000>;
|
||||
|
||||
cdns,read-delay = <4>;
|
||||
cdns,tshsl-ns = <50>;
|
||||
cdns,tsd2d-ns = <50>;
|
||||
cdns,tchsh-ns = <4>;
|
||||
cdns,tslch-ns = <4>;
|
||||
|
||||
partition@raw {
|
||||
label = "Flash Raw";
|
||||
reg = <0x0 0x4000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&gpio0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpio1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gmac1 {
|
||||
status = "okay";
|
||||
/delete-property/ mac-address;
|
||||
phy-mode = "rgmii-id";
|
||||
phy-handle = <&phy3>;
|
||||
|
||||
mdio0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "snps,dwmac-mdio";
|
||||
|
||||
phy3: ethernet-phy@3 {
|
||||
reg = <3>;
|
||||
|
||||
/* Add 2ns RX clock delay (1.2ns + 0.78ns)*/
|
||||
rxc-skew-ps = <1680>;
|
||||
rxd0-skew-ps = <420>;
|
||||
rxd1-skew-ps = <420>;
|
||||
rxd2-skew-ps = <420>;
|
||||
rxd3-skew-ps = <420>;
|
||||
rxdv-skew-ps = <420>;
|
||||
|
||||
/* Add 1.38ns TX clock delay (0.96ns + 0.42ns)*/
|
||||
txc-skew-ps = <1860>;
|
||||
txd0-skew-ps = <0>;
|
||||
txd1-skew-ps = <0>;
|
||||
txd2-skew-ps = <0>;
|
||||
txd3-skew-ps = <0>;
|
||||
txen-skew-ps = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&usb1 {
|
||||
status = "okay";
|
||||
dr_mode = "host";
|
||||
};
|
||||
@@ -0,0 +1,16 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+ OR MIT
|
||||
/*
|
||||
* Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "socfpga_cyclone5_mercury_sa1.dtsi"
|
||||
#include "socfpga_enclustra_mercury_pe1.dtsi"
|
||||
#include "socfpga_enclustra_mercury_bootmode_emmc.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Enclustra Mercury SA1 on Mercury+ PE1 Base Board";
|
||||
compatible = "enclustra,mercury-sa1-pe1", "enclustra,mercury-aa1",
|
||||
"altr,socfpga-arria10", "altr,socfpga";
|
||||
};
|
||||
@@ -0,0 +1,16 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+ OR MIT
|
||||
/*
|
||||
* Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "socfpga_cyclone5_mercury_sa1.dtsi"
|
||||
#include "socfpga_enclustra_mercury_pe1.dtsi"
|
||||
#include "socfpga_enclustra_mercury_bootmode_qspi.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Enclustra Mercury SA1 on Mercury+ PE1 Base Board";
|
||||
compatible = "enclustra,mercury-sa1-pe1", "enclustra,mercury-sa1",
|
||||
"altr,socfpga-cyclone5", "altr,socfpga";
|
||||
};
|
||||
@@ -0,0 +1,16 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+ OR MIT
|
||||
/*
|
||||
* Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "socfpga_cyclone5_mercury_sa1.dtsi"
|
||||
#include "socfpga_enclustra_mercury_pe1.dtsi"
|
||||
#include "socfpga_enclustra_mercury_bootmode_sdmmc.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Enclustra Mercury SA1 on Mercury+ PE1 Base Board";
|
||||
compatible = "enclustra,mercury-sa1-pe1", "enclustra,mercury-sa1",
|
||||
"altr,socfpga-cyclone5", "altr,socfpga";
|
||||
};
|
||||
@@ -0,0 +1,16 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+ OR MIT
|
||||
/*
|
||||
* Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "socfpga_cyclone5_mercury_sa1.dtsi"
|
||||
#include "socfpga_enclustra_mercury_pe3.dtsi"
|
||||
#include "socfpga_enclustra_mercury_bootmode_emmc.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Enclustra Mercury SA1 on Mercury+ PE3 Base Board";
|
||||
compatible = "enclustra,mercury-sa1-pe3", "enclustra,mercury-sa1",
|
||||
"altr,socfpga-cyclone5", "altr,socfpga";
|
||||
};
|
||||
@@ -0,0 +1,16 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+ OR MIT
|
||||
/*
|
||||
* Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "socfpga_cyclone5_mercury_sa1.dtsi"
|
||||
#include "socfpga_enclustra_mercury_pe3.dtsi"
|
||||
#include "socfpga_enclustra_mercury_bootmode_qspi.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Enclustra Mercury SA1 on Mercury+ PE3 Base Board";
|
||||
compatible = "enclustra,mercury-sa1-pe3", "enclustra,mercury-sa1",
|
||||
"altr,socfpga-cyclone5", "altr,socfpga";
|
||||
};
|
||||
@@ -0,0 +1,16 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+ OR MIT
|
||||
/*
|
||||
* Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "socfpga_cyclone5_mercury_sa1.dtsi"
|
||||
#include "socfpga_enclustra_mercury_pe3.dtsi"
|
||||
#include "socfpga_enclustra_mercury_bootmode_sdmmc.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Enclustra Mercury SA1 on Mercury+ PE3 Base Board";
|
||||
compatible = "enclustra,mercury-sa1-pe3", "enclustra,mercury-sa1",
|
||||
"altr,socfpga-cyclone5", "altr,socfpga";
|
||||
};
|
||||
@@ -0,0 +1,16 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+ OR MIT
|
||||
/*
|
||||
* Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "socfpga_cyclone5_mercury_sa1.dtsi"
|
||||
#include "socfpga_enclustra_mercury_st1.dtsi"
|
||||
#include "socfpga_enclustra_mercury_bootmode_emmc.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Enclustra Mercury SA1 on Mercury+ ST1 Base Board";
|
||||
compatible = "enclustra,mercury-sa1-st1", "enclustra,mercury-sa1",
|
||||
"altr,socfpga-cyclone5", "altr,socfpga";
|
||||
};
|
||||
@@ -0,0 +1,16 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+ OR MIT
|
||||
/*
|
||||
* Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "socfpga_cyclone5_mercury_sa1.dtsi"
|
||||
#include "socfpga_enclustra_mercury_st1.dtsi"
|
||||
#include "socfpga_enclustra_mercury_bootmode_qspi.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Enclustra Mercury SA1 on Mercury+ ST1 Base Board";
|
||||
compatible = "enclustra,mercury-sa1-st1", "enclustra,mercury-sa1",
|
||||
"altr,socfpga-cyclone5", "altr,socfpga";
|
||||
};
|
||||
@@ -0,0 +1,16 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+ OR MIT
|
||||
/*
|
||||
* Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "socfpga_cyclone5_mercury_sa1.dtsi"
|
||||
#include "socfpga_enclustra_mercury_st1.dtsi"
|
||||
#include "socfpga_enclustra_mercury_bootmode_sdmmc.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Enclustra Mercury SA1 on Mercury+ ST1 Base Board";
|
||||
compatible = "enclustra,mercury-sa1-st1", "enclustra,mercury-sa1",
|
||||
"altr,socfpga-cyclone5", "altr,socfpga";
|
||||
};
|
||||
@@ -0,0 +1,146 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+ OR MIT
|
||||
/*
|
||||
* Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com
|
||||
*/
|
||||
|
||||
#include "socfpga_cyclone5.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Enclustra Mercury+ SA2";
|
||||
compatible = "altr,socfpga-cyclone5", "altr,socfpga";
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
aliases {
|
||||
ethernet0 = &gmac1;
|
||||
};
|
||||
|
||||
/* Adjusted the i2c labels to use generic base-board dtsi files for
|
||||
* Enclustra Arria10 and Cyclone5 SoMs.
|
||||
*
|
||||
* The set of i2c0 and i2c1 labels defined in socfpga_cyclone5.dtsi and in
|
||||
* socfpga_arria10.dtsi do not allow for using the same base-board .dtsi
|
||||
* fragments. Thus define generic labels here to match the correct i2c
|
||||
* bus in a generic base-board .dtsi file.
|
||||
*/
|
||||
soc {
|
||||
i2c_encl: i2c@ffc04000 {
|
||||
};
|
||||
i2c_encl_fpga: i2c@ffc05000 {
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
name = "memory";
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x80000000>; /* 2GB */
|
||||
};
|
||||
};
|
||||
|
||||
&osc1 {
|
||||
clock-frequency = <50000000>;
|
||||
};
|
||||
|
||||
&i2c_encl {
|
||||
i2c-sda-hold-time-ns = <300>;
|
||||
clock-frequency = <100000>;
|
||||
status = "okay";
|
||||
|
||||
isl12020: rtc@6f {
|
||||
compatible = "isil,isl12022";
|
||||
reg = <0x6f>;
|
||||
};
|
||||
|
||||
atsha204a: crypto@64 {
|
||||
compatible = "atmel,atsha204a";
|
||||
reg = <0x64>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c_encl_fpga {
|
||||
i2c-sda-hold-time-ns = <300>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
clock-frequency = <100000000>;
|
||||
};
|
||||
|
||||
&mmc0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&qspi {
|
||||
status = "okay";
|
||||
|
||||
flash0: flash@0 {
|
||||
u-boot,dm-pre-reloc;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
|
||||
spi-rx-bus-width = <4>;
|
||||
spi-tx-bus-width = <4>;
|
||||
spi-max-frequency = <10000000>;
|
||||
|
||||
cdns,read-delay = <4>;
|
||||
cdns,tshsl-ns = <50>;
|
||||
cdns,tsd2d-ns = <50>;
|
||||
cdns,tchsh-ns = <4>;
|
||||
cdns,tslch-ns = <4>;
|
||||
|
||||
partition@raw {
|
||||
label = "Flash Raw";
|
||||
reg = <0x0 0x4000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&gpio0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpio1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gmac1 {
|
||||
status = "okay";
|
||||
/delete-property/ mac-address;
|
||||
phy-mode = "rgmii-id";
|
||||
phy-handle = <&phy3>;
|
||||
|
||||
mdio0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "snps,dwmac-mdio";
|
||||
|
||||
phy3: ethernet-phy@3 {
|
||||
reg = <3>;
|
||||
|
||||
/* Add 2ns RX clock delay (1.2ns + 0.78ns)*/
|
||||
rxc-skew-ps = <1680>;
|
||||
rxd0-skew-ps = <420>;
|
||||
rxd1-skew-ps = <420>;
|
||||
rxd2-skew-ps = <420>;
|
||||
rxd3-skew-ps = <420>;
|
||||
rxdv-skew-ps = <420>;
|
||||
|
||||
/* Add 1.38ns TX clock delay (0.96ns + 0.42ns)*/
|
||||
txc-skew-ps = <1860>;
|
||||
txd0-skew-ps = <0>;
|
||||
txd1-skew-ps = <0>;
|
||||
txd2-skew-ps = <0>;
|
||||
txd3-skew-ps = <0>;
|
||||
txen-skew-ps = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&usb1 {
|
||||
status = "okay";
|
||||
dr_mode = "host";
|
||||
};
|
||||
@@ -0,0 +1,16 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+ OR MIT
|
||||
/*
|
||||
* Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "socfpga_cyclone5_mercury_sa2.dtsi"
|
||||
#include "socfpga_enclustra_mercury_pe1.dtsi"
|
||||
#include "socfpga_enclustra_mercury_bootmode_qspi.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Enclustra Mercury+ SA2 on Mercury+ PE1 Base Board";
|
||||
compatible = "enclustra,mercury-sa2-pe1", "enclustra,mercury-sa2",
|
||||
"altr,socfpga-cyclone5", "altr,socfpga";
|
||||
};
|
||||
@@ -0,0 +1,16 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+ OR MIT
|
||||
/*
|
||||
* Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "socfpga_cyclone5_mercury_sa2.dtsi"
|
||||
#include "socfpga_enclustra_mercury_pe1.dtsi"
|
||||
#include "socfpga_enclustra_mercury_bootmode_sdmmc.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Enclustra Mercury+ SA2 on Mercury+ PE1 Base Board";
|
||||
compatible = "enclustra,mercury-sa2-pe1", "enclustra,mercury-sa2",
|
||||
"altr,socfpga-cyclone5", "altr,socfpga";
|
||||
};
|
||||
@@ -0,0 +1,16 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+ OR MIT
|
||||
/*
|
||||
* Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "socfpga_cyclone5_mercury_sa2.dtsi"
|
||||
#include "socfpga_enclustra_mercury_pe3.dtsi"
|
||||
#include "socfpga_enclustra_mercury_bootmode_qspi.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Enclustra Mercury+ SA2 on Mercury+ PE3 Base Board";
|
||||
compatible = "enclustra,mercury-sa2-pe3", "enclustra,mercury-sa2",
|
||||
"altr,socfpga-cyclone5", "altr,socfpga";
|
||||
};
|
||||
@@ -0,0 +1,16 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+ OR MIT
|
||||
/*
|
||||
* Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "socfpga_cyclone5_mercury_sa2.dtsi"
|
||||
#include "socfpga_enclustra_mercury_pe3.dtsi"
|
||||
#include "socfpga_enclustra_mercury_bootmode_sdmmc.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Enclustra Mercury+ SA2 on Mercury+ PE3 Base Board";
|
||||
compatible = "enclustra,mercury-sa2-pe3", "enclustra,mercury-sa2",
|
||||
"altr,socfpga-cyclone5", "altr,socfpga";
|
||||
};
|
||||
@@ -0,0 +1,16 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+ OR MIT
|
||||
/*
|
||||
* Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "socfpga_cyclone5_mercury_sa2.dtsi"
|
||||
#include "socfpga_enclustra_mercury_st1.dtsi"
|
||||
#include "socfpga_enclustra_mercury_bootmode_qspi.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Enclustra Mercury+ SA2 on Mercury+ ST1 Base Board";
|
||||
compatible = "enclustra,mercury-sa2-st1", "enclustra,mercury-sa2",
|
||||
"altr,socfpga-cyclone5", "altr,socfpga";
|
||||
};
|
||||
@@ -0,0 +1,16 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+ OR MIT
|
||||
/*
|
||||
* Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "socfpga_cyclone5_mercury_sa2.dtsi"
|
||||
#include "socfpga_enclustra_mercury_st1.dtsi"
|
||||
#include "socfpga_enclustra_mercury_bootmode_sdmmc.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Enclustra Mercury+ SA2 on Mercury+ ST1 Base Board";
|
||||
compatible = "enclustra,mercury-sa2-st1", "enclustra,mercury-sa2",
|
||||
"altr,socfpga-cyclone5", "altr,socfpga";
|
||||
};
|
||||
@@ -0,0 +1,12 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+ OR MIT
|
||||
/*
|
||||
* Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com
|
||||
*/
|
||||
|
||||
&qspi {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mmc {
|
||||
bus-width = <8>;
|
||||
};
|
||||
@@ -0,0 +1,8 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+ OR MIT
|
||||
/*
|
||||
* Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com
|
||||
*/
|
||||
|
||||
&mmc {
|
||||
status = "disabled";
|
||||
};
|
||||
@@ -0,0 +1,8 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+ OR MIT
|
||||
/*
|
||||
* Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com
|
||||
*/
|
||||
|
||||
&qspi {
|
||||
status = "disabled";
|
||||
};
|
||||
@@ -0,0 +1,33 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+ OR MIT
|
||||
/*
|
||||
* Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com
|
||||
*/
|
||||
|
||||
&i2c_encl {
|
||||
status = "okay";
|
||||
|
||||
eeprom@57 {
|
||||
status = "okay";
|
||||
compatible = "microchip,24c128";
|
||||
reg = <0x57>;
|
||||
pagesize = <64>;
|
||||
label = "user eeprom";
|
||||
address-width = <16>;
|
||||
};
|
||||
|
||||
lm96080: temperature-sensor@2f {
|
||||
status = "okay";
|
||||
compatible = "national,lm80";
|
||||
reg = <0x2f>;
|
||||
};
|
||||
|
||||
si5338: clock-controller@70 {
|
||||
compatible = "silabs,si5338";
|
||||
reg = <0x70>;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
&i2c_encl_fpga {
|
||||
status = "okay";
|
||||
};
|
||||
@@ -0,0 +1,55 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+ OR MIT
|
||||
/*
|
||||
* Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com
|
||||
*/
|
||||
|
||||
&i2c_encl {
|
||||
i2c-mux@74 {
|
||||
status = "okay";
|
||||
compatible = "nxp,pca9547";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x74>;
|
||||
|
||||
i2c@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
|
||||
eeprom@56 {
|
||||
status = "okay";
|
||||
compatible = "microchip,24c128";
|
||||
reg = <0x56>;
|
||||
pagesize = <64>;
|
||||
label = "user eeprom";
|
||||
address-width = <16>;
|
||||
};
|
||||
|
||||
lm96080: temperature-sensor@2f {
|
||||
status = "okay";
|
||||
compatible = "national,lm80";
|
||||
reg = <0x2f>;
|
||||
};
|
||||
|
||||
pcal6416: gpio@20 {
|
||||
status = "okay";
|
||||
compatible = "nxp,pcal6416";
|
||||
reg = <0x20>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c_encl_fpga {
|
||||
status = "okay";
|
||||
|
||||
i2c-mux@75 {
|
||||
status = "okay";
|
||||
compatible = "nxp,pca9547";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x75>;
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,15 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+ OR MIT
|
||||
/*
|
||||
* Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com
|
||||
*/
|
||||
|
||||
&i2c_encl {
|
||||
si5338: clock-controller@70 {
|
||||
compatible = "silabs,si5338";
|
||||
reg = <0x70>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c_encl_fpga {
|
||||
status = "okay";
|
||||
};
|
||||
@@ -630,6 +630,15 @@ emac0-tx-ecc@ff8c0400 {
|
||||
interrupts = <5 4>;
|
||||
};
|
||||
|
||||
sdmmca-ecc@ff8c8c00 {
|
||||
compatible = "altr,socfpga-s10-sdmmc-ecc",
|
||||
"altr,socfpga-sdmmc-ecc";
|
||||
reg = <0xff8c8c00 0x100>;
|
||||
altr,ecc-parent = <&mmc>;
|
||||
interrupts = <14 4>,
|
||||
<15 4>;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
qspi: spi@ff8d2000 {
|
||||
|
||||
@@ -50,19 +50,6 @@ ref_033v: regulator-v-ref {
|
||||
regulator-min-microvolt = <330000>;
|
||||
regulator-max-microvolt = <330000>;
|
||||
};
|
||||
|
||||
soc@0 {
|
||||
eccmgr {
|
||||
sdmmca-ecc@ff8c8c00 {
|
||||
compatible = "altr,socfpga-s10-sdmmc-ecc",
|
||||
"altr,socfpga-sdmmc-ecc";
|
||||
reg = <0xff8c8c00 0x100>;
|
||||
altr,ecc-parent = <&mmc>;
|
||||
interrupts = <14 4>,
|
||||
<15 4>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl0 {
|
||||
@@ -190,6 +177,8 @@ flash@0 {
|
||||
cdns,tsd2d-ns = <50>;
|
||||
cdns,tchsh-ns = <4>;
|
||||
cdns,tslch-ns = <4>;
|
||||
spi-tx-bus-width = <4>;
|
||||
spi-rx-bus-width = <4>;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
|
||||
@@ -50,19 +50,6 @@ ref_033v: regulator-v-ref {
|
||||
regulator-min-microvolt = <330000>;
|
||||
regulator-max-microvolt = <330000>;
|
||||
};
|
||||
|
||||
soc@0 {
|
||||
eccmgr {
|
||||
sdmmca-ecc@ff8c8c00 {
|
||||
compatible = "altr,socfpga-s10-sdmmc-ecc",
|
||||
"altr,socfpga-sdmmc-ecc";
|
||||
reg = <0xff8c8c00 0x100>;
|
||||
altr,ecc-parent = <&mmc>;
|
||||
interrupts = <14 4>,
|
||||
<15 4>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&gpio1 {
|
||||
|
||||
@@ -62,7 +62,6 @@ &osc1 {
|
||||
&gmac0 {
|
||||
status = "okay";
|
||||
phy-mode = "rgmii";
|
||||
phy-addr = <0xffffffff>;
|
||||
};
|
||||
|
||||
&gmac1 {
|
||||
@@ -73,7 +72,6 @@ &gmac1 {
|
||||
&gmac2 {
|
||||
status = "okay";
|
||||
phy-mode = "rgmii";
|
||||
phy-addr = <0xffffffff>;
|
||||
};
|
||||
|
||||
&mmc {
|
||||
@@ -104,5 +102,4 @@ &usb1 {
|
||||
|
||||
&sysmgr {
|
||||
reg = <0xffd12000 0x1000>;
|
||||
interrupts = <0x0 0x10 0x4>;
|
||||
};
|
||||
|
||||
@@ -2,7 +2,9 @@
|
||||
dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga_agilex_n6000.dtb \
|
||||
socfpga_agilex_socdk.dtb \
|
||||
socfpga_agilex_socdk_nand.dtb \
|
||||
socfpga_agilex3_socdk.dtb \
|
||||
socfpga_agilex5_socdk.dtb \
|
||||
socfpga_agilex5_socdk_013b.dtb \
|
||||
socfpga_agilex5_socdk_nand.dtb \
|
||||
socfpga_n5x_socdk.dtb
|
||||
dtb-$(CONFIG_ARCH_KEEMBAY) += keembay-evm.dtb
|
||||
|
||||
@@ -167,6 +167,7 @@ clkmgr: clock-controller@ffd10000 {
|
||||
compatible = "intel,agilex-clkmgr";
|
||||
reg = <0xffd10000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&osc1>;
|
||||
};
|
||||
|
||||
gmac0: ethernet@ff800000 {
|
||||
|
||||
132
arch/arm64/boot/dts/intel/socfpga_agilex3_socdk.dts
Normal file
132
arch/arm64/boot/dts/intel/socfpga_agilex3_socdk.dts
Normal file
@@ -0,0 +1,132 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Copyright (C) 2025, Altera Corporation
|
||||
*/
|
||||
#include "socfpga_agilex5.dtsi"
|
||||
|
||||
/ {
|
||||
model = "SoCFPGA Agilex3 SoCDK";
|
||||
compatible = "intel,socfpga-agilex3-socdk", "intel,socfpga-agilex3",
|
||||
"intel,socfpga-agilex5";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
ethernet2 = &gmac2;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
cpus {
|
||||
/delete-node/ cpu@2;
|
||||
/delete-node/ cpu@3;
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
led0 {
|
||||
label = "hps_led0";
|
||||
gpios = <&porta 1 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
led1 {
|
||||
label = "hps_led1";
|
||||
gpios = <&porta 12 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
/* We expect the bootloader to fill in the reg */
|
||||
reg = <0x0 0x80000000 0x0 0x0>;
|
||||
};
|
||||
};
|
||||
|
||||
&gmac2 {
|
||||
status = "okay";
|
||||
phy-mode = "rgmii-id";
|
||||
phy-handle = <&emac2_phy0>;
|
||||
max-frame-size = <9000>;
|
||||
|
||||
mdio0 {
|
||||
compatible = "snps,dwmac-mdio";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
emac2_phy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
rxc-skew-ps = <0>;
|
||||
rxdv-skew-ps = <0>;
|
||||
rxd0-skew-ps = <0>;
|
||||
rxd1-skew-ps = <0>;
|
||||
rxd2-skew-ps = <0>;
|
||||
rxd3-skew-ps = <0>;
|
||||
txc-skew-ps = <0>;
|
||||
txen-skew-ps = <60>;
|
||||
txd0-skew-ps = <60>;
|
||||
txd1-skew-ps = <60>;
|
||||
txd2-skew-ps = <60>;
|
||||
txd3-skew-ps = <60>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&gpio0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpio1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&osc1 {
|
||||
clock-frequency = <25000000>;
|
||||
};
|
||||
|
||||
&qspi {
|
||||
status = "okay";
|
||||
flash@0 {
|
||||
compatible = "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <100000000>;
|
||||
m25p,fast-read;
|
||||
cdns,read-delay = <2>;
|
||||
cdns,tshsl-ns = <50>;
|
||||
cdns,tsd2d-ns = <50>;
|
||||
cdns,tchsh-ns = <4>;
|
||||
cdns,tslch-ns = <4>;
|
||||
spi-tx-bus-width = <4>;
|
||||
spi-rx-bus-width = <4>;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
qspi_boot: partition@0 {
|
||||
label = "u-boot";
|
||||
reg = <0x0 0x00c00000>;
|
||||
};
|
||||
|
||||
root: partition@c00000 {
|
||||
label = "root";
|
||||
reg = <0x00c00000 0x03400000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&smmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&watchdog0 {
|
||||
status = "okay";
|
||||
};
|
||||
@@ -37,6 +37,7 @@ cpu0: cpu@0 {
|
||||
reg = <0x0>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
|
||||
cpu1: cpu@1 {
|
||||
@@ -44,6 +45,7 @@ cpu1: cpu@1 {
|
||||
reg = <0x100>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
|
||||
cpu2: cpu@2 {
|
||||
@@ -51,6 +53,7 @@ cpu2: cpu@2 {
|
||||
reg = <0x200>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
|
||||
cpu3: cpu@3 {
|
||||
@@ -58,6 +61,30 @@ cpu3: cpu@3 {
|
||||
reg = <0x300>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
|
||||
L2: l2-cache {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
next-level-cache = <&L3>;
|
||||
cache-unified;
|
||||
};
|
||||
|
||||
L3: l3-cache {
|
||||
compatible = "cache";
|
||||
cache-level = <3>;
|
||||
cache-unified;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
firmware {
|
||||
svc {
|
||||
compatible = "intel,agilex5-svc";
|
||||
method = "smc";
|
||||
memory-region = <&service_reserved>;
|
||||
iommus = <&smmu 10>;
|
||||
};
|
||||
};
|
||||
|
||||
@@ -75,8 +102,11 @@ intc: interrupt-controller@1d000000 {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
interrupt-controller;
|
||||
interrupt-parent = <&intc>;
|
||||
#redistributor-regions = <1>;
|
||||
redistributor-stride = <0x0 0x20000>;
|
||||
/* VGIC maintenance interrupt */
|
||||
interrupts = <GIC_PPI 25 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
its: msi-controller@1d040000 {
|
||||
compatible = "arm,gic-v3-its";
|
||||
@@ -133,6 +163,12 @@ usbphy0: usbphy {
|
||||
compatible = "usb-nop-xceiv";
|
||||
};
|
||||
|
||||
pmu0: pmu {
|
||||
compatible = "arm,armv8-pmuv3";
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
|
||||
soc: soc@0 {
|
||||
compatible = "simple-bus";
|
||||
ranges = <0 0 0 0xffffffff>;
|
||||
@@ -203,7 +239,8 @@ i2c4: i2c@10c02c00 {
|
||||
};
|
||||
|
||||
i3c0: i3c@10da0000 {
|
||||
compatible = "snps,dw-i3c-master-1.00a";
|
||||
compatible = "altr,agilex5-dw-i3c-master",
|
||||
"snps,dw-i3c-master-1.00a";
|
||||
reg = <0x10da0000 0x1000>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <0>;
|
||||
@@ -213,7 +250,8 @@ i3c0: i3c@10da0000 {
|
||||
};
|
||||
|
||||
i3c1: i3c@10da1000 {
|
||||
compatible = "snps,dw-i3c-master-1.00a";
|
||||
compatible = "altr,agilex5-dw-i3c-master",
|
||||
"snps,dw-i3c-master-1.00a";
|
||||
reg = <0x10da1000 0x1000>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <0>;
|
||||
@@ -271,7 +309,9 @@ nand: nand-controller@10b80000 {
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clkmgr AGILEX5_NAND_NF_CLK>;
|
||||
clock-names = "nf_clk";
|
||||
cdns,board-delay-ps = <4830>;
|
||||
iommus = <&smmu 4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@@ -298,6 +338,7 @@ dmac0: dma-controller@10db0000 {
|
||||
snps,block-size = <32767 32767 32767 32767>;
|
||||
snps,priority = <0 1 2 3>;
|
||||
snps,axi-max-burst-len = <8>;
|
||||
iommus = <&smmu 8>;
|
||||
};
|
||||
|
||||
dmac1: dma-controller@10dc0000 {
|
||||
@@ -315,6 +356,7 @@ dmac1: dma-controller@10dc0000 {
|
||||
snps,block-size = <32767 32767 32767 32767>;
|
||||
snps,priority = <0 1 2 3>;
|
||||
snps,axi-max-burst-len = <8>;
|
||||
iommus = <&smmu 9>;
|
||||
};
|
||||
|
||||
rst: rstmgr@10d11000 {
|
||||
@@ -323,6 +365,18 @@ rst: rstmgr@10d11000 {
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
smmu: iommu@16000000 {
|
||||
compatible = "arm,smmu-v3";
|
||||
reg = <0x16000000 0x30000>;
|
||||
interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 129 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 132 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupt-names = "eventq", "gerror", "priq";
|
||||
dma-coherent;
|
||||
#iommu-cells = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi0: spi@10da4000 {
|
||||
compatible = "snps,dw-apb-ssi";
|
||||
reg = <0x10da4000 0x1000>;
|
||||
@@ -423,6 +477,7 @@ usb0: usb@10b00000 {
|
||||
phy-names = "usb2-phy";
|
||||
resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>;
|
||||
reset-names = "dwc2", "dwc2-ecc";
|
||||
iommus = <&smmu 6>;
|
||||
clocks = <&clkmgr AGILEX5_USB2OTG_HCLK>;
|
||||
clock-names = "otg";
|
||||
status = "disabled";
|
||||
@@ -822,5 +877,61 @@ queue7 {
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pmu0_tcu: pmu@16002000 {
|
||||
compatible = "arm,smmu-v3-pmcg";
|
||||
reg = <0x16002000 0x1000>,
|
||||
<0x16022000 0x1000>;
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>;
|
||||
};
|
||||
|
||||
pmu0_tbu0: pmu@16042000 {
|
||||
compatible = "arm,smmu-v3-pmcg";
|
||||
reg = <0x16042000 0x1000>,
|
||||
<0x16052000 0x1000>;
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>;
|
||||
};
|
||||
|
||||
pmu0_tbu1: pmu@16062000 {
|
||||
compatible = "arm,smmu-v3-pmcg";
|
||||
reg = <0x16062000 0x1000>,
|
||||
<0x16072000 0x1000>;
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>;
|
||||
};
|
||||
|
||||
pmu0_tbu2: pmu@16082000 {
|
||||
compatible = "arm,smmu-v3-pmcg";
|
||||
reg = <0x16082000 0x1000>,
|
||||
<0x16092000 0x1000>;
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>;
|
||||
};
|
||||
|
||||
pmu0_tbu3: pmu@160a2000 {
|
||||
compatible = "arm,smmu-v3-pmcg";
|
||||
reg = <0x160A2000 0x1000>,
|
||||
<0x160B2000 0x1000>;
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>;
|
||||
};
|
||||
|
||||
pmu0_tbu4: pmu@160c2000 {
|
||||
compatible = "arm,smmu-v3-pmcg";
|
||||
reg = <0x160C2000 0x1000>,
|
||||
<0x160D2000 0x1000>;
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <GIC_SPI 146 IRQ_TYPE_EDGE_RISING>;
|
||||
};
|
||||
|
||||
pmu0_tbu5: pmu@160e2000 {
|
||||
compatible = "arm,smmu-v3-pmcg";
|
||||
reg = <0x160E2000 0x1000>,
|
||||
<0x160F2000 0x1000>;
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <GIC_SPI 150 IRQ_TYPE_EDGE_RISING>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@@ -77,6 +77,8 @@ flash@0 {
|
||||
cdns,tsd2d-ns = <50>;
|
||||
cdns,tchsh-ns = <4>;
|
||||
cdns,tslch-ns = <4>;
|
||||
spi-tx-bus-width = <4>;
|
||||
spi-rx-bus-width = <4>;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
|
||||
126
arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_013b.dts
Normal file
126
arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_013b.dts
Normal file
@@ -0,0 +1,126 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Copyright (C) 2025, Altera Corporation
|
||||
*/
|
||||
#include "socfpga_agilex5.dtsi"
|
||||
|
||||
/ {
|
||||
model = "SoCFPGA Agilex5 013B SoCDK";
|
||||
compatible = "intel,socfpga-agilex5-socdk-013b", "intel,socfpga-agilex5";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
ethernet2 = &gmac2;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
led0 {
|
||||
label = "hps_led0";
|
||||
gpios = <&porta 1 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
led1 {
|
||||
label = "hps_led1";
|
||||
gpios = <&porta 12 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
/* We expect the bootloader to fill in the reg */
|
||||
reg = <0x0 0x80000000 0x0 0x0>;
|
||||
};
|
||||
};
|
||||
|
||||
&gmac2 {
|
||||
status = "okay";
|
||||
phy-mode = "rgmii-id";
|
||||
phy-handle = <&emac2_phy0>;
|
||||
max-frame-size = <9000>;
|
||||
|
||||
mdio0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "snps,dwmac-mdio";
|
||||
|
||||
emac2_phy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
rxc-skew-ps = <0>;
|
||||
rxdv-skew-ps = <0>;
|
||||
rxd0-skew-ps = <0>;
|
||||
rxd1-skew-ps = <0>;
|
||||
rxd2-skew-ps = <0>;
|
||||
rxd3-skew-ps = <0>;
|
||||
txc-skew-ps = <0>;
|
||||
txen-skew-ps = <60>;
|
||||
txd0-skew-ps = <60>;
|
||||
txd1-skew-ps = <60>;
|
||||
txd2-skew-ps = <60>;
|
||||
txd3-skew-ps = <60>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&gpio0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpio1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&osc1 {
|
||||
clock-frequency = <25000000>;
|
||||
};
|
||||
|
||||
&qspi {
|
||||
status = "okay";
|
||||
flash@0 {
|
||||
compatible = "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <100000000>;
|
||||
m25p,fast-read;
|
||||
cdns,read-delay = <2>;
|
||||
cdns,tshsl-ns = <50>;
|
||||
cdns,tsd2d-ns = <50>;
|
||||
cdns,tchsh-ns = <4>;
|
||||
cdns,tslch-ns = <4>;
|
||||
spi-tx-bus-width = <4>;
|
||||
spi-rx-bus-width = <4>;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
qspi_boot: partition@0 {
|
||||
label = "u-boot";
|
||||
reg = <0x0 0x00c00000>;
|
||||
};
|
||||
|
||||
root: partition@c00000 {
|
||||
label = "root";
|
||||
reg = <0x00c00000 0x03400000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&smmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&watchdog0 {
|
||||
status = "okay";
|
||||
};
|
||||
@@ -10,6 +10,7 @@ / {
|
||||
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
ethernet0 = &gmac0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
@@ -36,6 +37,23 @@ memory@80000000 {
|
||||
};
|
||||
};
|
||||
|
||||
&gmac0 {
|
||||
status = "okay";
|
||||
phy-mode = "rgmii-id";
|
||||
phy-handle = <&emac0_phy0>;
|
||||
max-frame-size = <9000>;
|
||||
|
||||
mdio0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "snps,dwmac-mdio";
|
||||
|
||||
emac0_phy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&gpio0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
@@ -116,6 +116,8 @@ flash@0 {
|
||||
cdns,tsd2d-ns = <50>;
|
||||
cdns,tchsh-ns = <4>;
|
||||
cdns,tslch-ns = <4>;
|
||||
spi-tx-bus-width = <4>;
|
||||
spi-rx-bus-width = <4>;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
|
||||
@@ -81,7 +81,7 @@ phy0: ethernet-phy@0 {
|
||||
&nand {
|
||||
status = "okay";
|
||||
|
||||
flash@0 {
|
||||
nand@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0>;
|
||||
|
||||
@@ -93,6 +93,8 @@ flash@0 {
|
||||
cdns,tsd2d-ns = <50>;
|
||||
cdns,tchsh-ns = <4>;
|
||||
cdns,tslch-ns = <4>;
|
||||
spi-tx-bus-width = <4>;
|
||||
spi-rx-bus-width = <4>;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
|
||||
Reference in New Issue
Block a user