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drm/amd/display: Fix CRC engine 1 enable/disable on DCN3.1.2+

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[Why]
Multi-ROI CRC uses OTG_CRC1_EN for the second engine, but the driver
only toggled OTG_CRC_EN and cleared the whole OTG_CRC_CNTL register on
disable.

[How]
Program engine 1 via OTG_CRC1_EN where supported, disable each
engine independently by crc_eng_inst, and add the missing mask on
relevant DCN ASICs.

Reviewed-by: ChiaHsuan (Tom) Chung <chiahsuan.chung@amd.com>
Signed-off-by: Wayne Lin <Wayne.Lin@amd.com>
Signed-off-by: Roman Li <roman.li@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Wayne Lin
2026-07-23 16:37:02 +08:00
committed by Alex Deucher
parent fdd9ca8878
commit c79354d12c
11 changed files with 69 additions and 18 deletions
Download Patch File Download Diff File Expand all files Collapse all files

36
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
View File

@@ -1471,8 +1471,21 @@ bool optc1_configure_crc(struct timing_generator *optc,
if (!optc1_is_tg_enabled(optc))
return false;
if (!params->enable || params->reset)
REG_WRITE(OTG_CRC_CNTL, 0);
if (!params->enable || params->reset) {
switch (params->crc_eng_inst) {
case 0:
REG_UPDATE(OTG_CRC_CNTL, OTG_CRC_EN, 0);
break;
case 1:
if (optc1->tg_mask->OTG_CRC1_EN != 0)
REG_UPDATE(OTG_CRC_CNTL, OTG_CRC1_EN, 0);
else
REG_UPDATE(OTG_CRC_CNTL, OTG_CRC_EN, 0);
break;
default:
return false;
}
}
if (!params->enable)
return true;
@@ -1528,10 +1541,16 @@ bool optc1_configure_crc(struct timing_generator *optc,
OTG_CRC1_WINDOWB_Y_END, params->windowb_y_end);
/* Set crc mode and selection, and enable.*/
REG_UPDATE_3(OTG_CRC_CNTL,
OTG_CRC_CONT_EN, params->continuous_mode ? 1 : 0,
OTG_CRC1_SELECT, params->selection,
OTG_CRC_EN, 1);
if (optc1->tg_mask->OTG_CRC1_EN != 0)
REG_UPDATE_3(OTG_CRC_CNTL,
OTG_CRC_CONT_EN, params->continuous_mode ? 1 : 0,
OTG_CRC1_SELECT, params->selection,
OTG_CRC1_EN, 1);
else
REG_UPDATE_3(OTG_CRC_CNTL,
OTG_CRC_CONT_EN, params->continuous_mode ? 1 : 0,
OTG_CRC1_SELECT, params->selection,
OTG_CRC_EN, 1);
break;
default:
return false;
@@ -1562,7 +1581,10 @@ bool optc1_get_crc(struct timing_generator *optc, uint8_t idx,
uint32_t field = 0;
struct optc *optc1 = DCN10TG_FROM_TG(optc);
REG_GET(OTG_CRC_CNTL, OTG_CRC_EN, &field);
if (idx == 1 && optc1->tg_mask->OTG_CRC1_EN != 0)
REG_GET(OTG_CRC_CNTL, OTG_CRC1_EN, &field);
else
REG_GET(OTG_CRC_CNTL, OTG_CRC_EN, &field);
/* Early return if CRC is not enabled for this CRTC */
if (!field)

3
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
View File

@@ -655,7 +655,8 @@ struct dcn_optc_registers {
type OTG0_IHC_OTG_VERTICAL_INTERRUPT2_DEST;
#define TG_REG_FIELD_LIST_DCN3_2(type) \
type OTG_H_TIMING_DIV_MODE_MANUAL;
type OTG_H_TIMING_DIV_MODE_MANUAL;\
type OTG_CRC1_EN;
#define TG_REG_FIELD_LIST_DCN3_5(type) \
type OTG_CRC0_WINDOWA_X_START_READBACK;\

4
drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
View File

@@ -263,6 +263,10 @@
SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_VUPDATE_KEEPOUT_STATUS, mask_sh),\
SF(OTG0_INTERRUPT_DEST, OTG0_IHC_OTG_VERTICAL_INTERRUPT2_DEST, mask_sh)
#define OPTC_COMMON_MASK_SH_LIST_DCN31X(mask_sh)\
OPTC_COMMON_MASK_SH_LIST_DCN3_1(mask_sh),\
SF(OTG0_OTG_CRC_CNTL, OTG_CRC1_EN, mask_sh)
void dcn31_timing_generator_init(struct optc *optc1);
bool optc31_immediate_disable_crtc(struct timing_generator *optc);

1
drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
View File

@@ -205,6 +205,7 @@
SF(OTG0_OTG_CRC_CNTL, OTG_CRC_CONT_EN, mask_sh),\
SF(OTG0_OTG_CRC_CNTL, OTG_CRC0_SELECT, mask_sh),\
SF(OTG0_OTG_CRC_CNTL, OTG_CRC_EN, mask_sh),\
SF(OTG0_OTG_CRC_CNTL, OTG_CRC1_EN, mask_sh),\
SF(OTG0_OTG_CRC0_DATA_RG, CRC0_R_CR, mask_sh),\
SF(OTG0_OTG_CRC0_DATA_RG, CRC0_G_Y, mask_sh),\
SF(OTG0_OTG_CRC0_DATA_B, CRC0_B_CB, mask_sh),\

1
drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
View File

@@ -134,6 +134,7 @@
SF(OTG0_OTG_CRC_CNTL, OTG_CRC0_SELECT, mask_sh),\
SF(OTG0_OTG_CRC_CNTL, OTG_CRC1_SELECT, mask_sh),\
SF(OTG0_OTG_CRC_CNTL, OTG_CRC_EN, mask_sh),\
SF(OTG0_OTG_CRC_CNTL, OTG_CRC1_EN, mask_sh),\
SF(OTG0_OTG_CRC0_DATA_RG, CRC0_R_CR, mask_sh),\
SF(OTG0_OTG_CRC0_DATA_RG, CRC0_G_Y, mask_sh),\
SF(OTG0_OTG_CRC0_DATA_B, CRC0_B_CB, mask_sh),\

26
drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c
View File

@@ -205,7 +205,10 @@ static bool optc35_get_crc(struct timing_generator *optc, uint8_t idx,
uint32_t field = 0;
struct optc *optc1 = DCN10TG_FROM_TG(optc);
REG_GET(OTG_CRC_CNTL, OTG_CRC_EN, &field);
if (idx == 1 && optc1->tg_mask->OTG_CRC1_EN != 0)
REG_GET(OTG_CRC_CNTL, OTG_CRC1_EN, &field);
else
REG_GET(OTG_CRC_CNTL, OTG_CRC_EN, &field);
/* Early return if CRC is not enabled for this CRTC */
if (!field)
@@ -275,8 +278,21 @@ bool optc35_configure_crc(struct timing_generator *optc,
if (!optc1_is_tg_enabled(optc))
return false;
if (!params->enable || params->reset)
REG_WRITE(OTG_CRC_CNTL, 0);
if (!params->enable || params->reset) {
switch (params->crc_eng_inst) {
case 0:
REG_UPDATE(OTG_CRC_CNTL, OTG_CRC_EN, 0);
break;
case 1:
if (optc1->tg_mask->OTG_CRC1_EN != 0)
REG_UPDATE(OTG_CRC_CNTL, OTG_CRC1_EN, 0);
else
REG_UPDATE(OTG_CRC_CNTL, OTG_CRC_EN, 0);
break;
default:
return false;
}
}
if (!params->enable)
return true;
@@ -341,13 +357,13 @@ bool optc35_configure_crc(struct timing_generator *optc,
REG_UPDATE_4(OTG_CRC_CNTL,
OTG_CRC_CONT_EN, params->continuous_mode ? 1 : 0,
OTG_CRC1_SELECT, params->selection,
OTG_CRC_EN, 1,
OTG_CRC1_EN, 1,
OTG_CRC_WINDOW_DB_EN, 1);
else
REG_UPDATE_3(OTG_CRC_CNTL,
OTG_CRC_CONT_EN, params->continuous_mode ? 1 : 0,
OTG_CRC1_SELECT, params->selection,
OTG_CRC_EN, 1);
OTG_CRC1_EN, 1);
break;
default:
return false;

1
drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
View File

@@ -111,6 +111,7 @@
SF(OTG0_OTG_CRC_CNTL, OTG_CRC_CONT_EN, mask_sh),\
SF(OTG0_OTG_CRC_CNTL, OTG_CRC0_SELECT, mask_sh),\
SF(OTG0_OTG_CRC_CNTL, OTG_CRC_EN, mask_sh),\
SF(OTG0_OTG_CRC_CNTL, OTG_CRC1_EN, mask_sh),\
SF(OTG0_OTG_CRC0_DATA_RG, CRC0_R_CR, mask_sh),\
SF(OTG0_OTG_CRC0_DATA_RG, CRC0_G_Y, mask_sh),\
SF(OTG0_OTG_CRC0_DATA_B, CRC0_B_CB, mask_sh),\

5
drivers/gpu/drm/amd/display/dc/optc/dcn42/dcn42_optc.c
View File

@@ -46,7 +46,10 @@ bool optc42_get_crc(struct timing_generator *optc, uint8_t idx,
uint32_t field = 0;
struct optc *optc1 = DCN10TG_FROM_TG(optc);
REG_GET(OTG_CRC_CNTL, OTG_CRC_EN, &field);
if (idx == 1 && optc1->tg_mask->OTG_CRC1_EN != 0)
REG_GET(OTG_CRC_CNTL, OTG_CRC1_EN, &field);
else
REG_GET(OTG_CRC_CNTL, OTG_CRC_EN, &field);
/* Early return if CRC is not enabled for this CRTC */
if (!field)

2
drivers/gpu/drm/amd/display/dc/optc/dcn42/dcn42_optc.h
View File

@@ -138,6 +138,7 @@
SF(OTG0_OTG_CRC_CNTL, OTG_CRC_CONT_EN, mask_sh),\
SF(OTG0_OTG_CRC_CNTL, OTG_CRC0_SELECT, mask_sh),\
SF(OTG0_OTG_CRC_CNTL, OTG_CRC_EN, mask_sh),\
SF(OTG0_OTG_CRC_CNTL, OTG_CRC1_EN, mask_sh),\
SF(OTG0_OTG_CRC0_DATA_R, CRC0_R_CR, mask_sh),\
SF(OTG0_OTG_CRC0_DATA_G, CRC0_G_Y, mask_sh),\
SF(OTG0_OTG_CRC0_DATA_B, CRC0_B_CB, mask_sh),\
@@ -316,6 +317,7 @@
SF(OTG0_OTG_CRC_CNTL, OTG_CRC_CONT_EN, mask_sh),\
SF(OTG0_OTG_CRC_CNTL, OTG_CRC0_SELECT, mask_sh),\
SF(OTG0_OTG_CRC_CNTL, OTG_CRC_EN, mask_sh),\
SF(OTG0_OTG_CRC_CNTL, OTG_CRC1_EN, mask_sh),\
SF(OTG0_OTG_CRC0_DATA_R, CRC0_R_CR, mask_sh),\
SF(OTG0_OTG_CRC0_DATA_G, CRC0_G_Y, mask_sh),\
SF(OTG0_OTG_CRC0_DATA_B, CRC0_B_CB, mask_sh),\

4
drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
View File

@@ -659,11 +659,11 @@ static const struct dcn_optc_registers optc_regs[] = {
};
static const struct dcn_optc_shift optc_shift = {
OPTC_COMMON_MASK_SH_LIST_DCN3_1(__SHIFT)
OPTC_COMMON_MASK_SH_LIST_DCN31X(__SHIFT)
};
static const struct dcn_optc_mask optc_mask = {
OPTC_COMMON_MASK_SH_LIST_DCN3_1(_MASK)
OPTC_COMMON_MASK_SH_LIST_DCN31X(_MASK)
};
#define hubp_regs(id)\

4
drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
View File

@@ -654,11 +654,11 @@ static const struct dcn_optc_registers optc_regs[] = {
};
static const struct dcn_optc_shift optc_shift = {
OPTC_COMMON_MASK_SH_LIST_DCN3_1(__SHIFT)
OPTC_COMMON_MASK_SH_LIST_DCN31X(__SHIFT)
};
static const struct dcn_optc_mask optc_mask = {
OPTC_COMMON_MASK_SH_LIST_DCN3_1(_MASK)
OPTC_COMMON_MASK_SH_LIST_DCN31X(_MASK)
};
#define hubp_regs(id)\