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PCI: rockchip: Fix order of rockchip_pci_core_rsts

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The order of rockchip_pci_core_rsts introduced in the offending commit
followed the previous comment that warned not to reorder them. But the
commit failed to take into account that reset_control_bulk_deassert()
deasserts the resets in reverse order. So this leads to the link getting
downgraded to 2.5 GT/s.

Hence, restore the deassert order and also add back the comments for
rockchip_pci_core_rsts.

Tested on NanoPC-T4 with Samsung 970 Pro.

Fixes: 18715931a5 ("PCI: rockchip: Simplify reset control handling by using reset_control_bulk*() function")
Signed-off-by: Jensen Huang <jensenhuang@friendlyarm.com>
[mani: reworded the commit message and the comment above rockchip_pci_core_rsts]
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Acked-by: Shawn Lin <shawn.lin@rock-chips.com>
Link: https://patch.msgid.link/20250328105822.3946767-1-jensenhuang@friendlyarm.com
This commit is contained in:
Jensen Huang
2025-03-28 18:58:22 +08:00
committed by Manivannan Sadhasivam
parent 0af2f6be1b
commit c7540e5423
1 changed files with 4 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
drivers/pci/controller/pcie-rockchip.h
View File

@@ -319,11 +319,12 @@ static const char * const rockchip_pci_pm_rsts[] = {
"aclk",
};
/* NOTE: Do not reorder the deassert sequence of the following reset pins */
static const char * const rockchip_pci_core_rsts[] = {
"mgmt-sticky",
"core",
"mgmt",
"pipe",
"mgmt",
"core",
"mgmt-sticky",
};
struct rockchip_pcie {