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arm64: dts: ti: k3-j7200-ti-ipc-firmware: Refactor IPC cfg into new dtsi
The TI K3 J7200 SoCs have multiple programmable remote processors like R5Fs. The TI SDKs for J7200 SoCs offer sample firmwares which could be run on these cores to demonstrate an "echo" IPC test. Those firmware require certain memory carveouts to be reserved from system memory, timers to be reserved, and certain mailbox configurations for interrupt based messaging. These configurations could be different for a different firmware. While DT is not meant for system configurations, at least refactor these configurations from board level DTS into a dtsi for now. This dtsi for TI IPC firmware is board-independent and can be applied to all boards from the same SoC Family. This gets rid of code duplication and allows more freedom for users developing custom firmware (or no firmware) to utilize system resources better; easily by swapping out this dtsi. To maintain backward compatibility, the dtsi is included in all boards. Signed-off-by: Beleswar Padhi <b-padhi@ti.com> Link: https://patch.msgid.link/20250908142826.1828676-25-b-padhi@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
This commit is contained in:
Beleswar Padhi
committed by
Nishanth Menon
Nishanth Menon
parent
897117c6bb
commit
c5b645dbec
@@ -40,48 +40,6 @@ mcu_r5fss0_core0_memory_region: memory@a0100000 {
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reg = <0x00 0xa0100000 0x00 0xf00000>;
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no-map;
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};
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mcu_r5fss0_core1_dma_memory_region: memory@a1000000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa1000000 0x00 0x100000>;
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no-map;
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};
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mcu_r5fss0_core1_memory_region: memory@a1100000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa1100000 0x00 0xf00000>;
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no-map;
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};
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main_r5fss0_core0_dma_memory_region: memory@a2000000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa2000000 0x00 0x100000>;
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no-map;
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};
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main_r5fss0_core0_memory_region: memory@a2100000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa2100000 0x00 0xf00000>;
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no-map;
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};
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main_r5fss0_core1_dma_memory_region: memory@a3000000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa3000000 0x00 0x100000>;
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no-map;
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};
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main_r5fss0_core1_memory_region: memory@a3100000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa3100000 0x00 0xf00000>;
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no-map;
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};
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rtos_ipc_memory_region: memory@a4000000 {
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reg = <0x00 0xa4000000 0x00 0x00800000>;
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alignment = <0x1000>;
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no-map;
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};
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};
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mux0: mux-controller-0 {
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@@ -224,86 +182,6 @@ partition@800000 {
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};
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};
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&mailbox0_cluster0 {
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status = "okay";
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interrupts = <436>;
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mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
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ti,mbox-rx = <0 0 0>;
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ti,mbox-tx = <1 0 0>;
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};
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mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
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ti,mbox-rx = <2 0 0>;
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ti,mbox-tx = <3 0 0>;
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};
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};
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&mailbox0_cluster1 {
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status = "okay";
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interrupts = <432>;
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mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
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ti,mbox-rx = <0 0 0>;
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ti,mbox-tx = <1 0 0>;
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};
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mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
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ti,mbox-rx = <2 0 0>;
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ti,mbox-tx = <3 0 0>;
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};
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};
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&mcu_r5fss0 {
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status = "okay";
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};
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&mcu_r5fss0_core0 {
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mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
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memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
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<&mcu_r5fss0_core0_memory_region>;
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status = "okay";
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};
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&mcu_r5fss0_core1 {
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mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>;
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memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
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<&mcu_r5fss0_core1_memory_region>;
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status = "okay";
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};
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&main_r5fss0 {
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ti,cluster-mode = <0>;
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status = "okay";
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};
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/* Timers are used by Remoteproc firmware */
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&main_timer0 {
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status = "reserved";
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};
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&main_timer1 {
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status = "reserved";
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};
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&main_timer2 {
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status = "reserved";
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};
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&main_r5fss0_core0 {
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mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>;
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memory-region = <&main_r5fss0_core0_dma_memory_region>,
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<&main_r5fss0_core0_memory_region>;
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status = "okay";
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};
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&main_r5fss0_core1 {
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mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>;
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memory-region = <&main_r5fss0_core1_dma_memory_region>,
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<&main_r5fss0_core1_memory_region>;
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status = "okay";
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};
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&main_i2c0 {
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pinctrl-names = "default";
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pinctrl-0 = <&main_i2c0_pins_default>;
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@@ -546,3 +424,5 @@ &main_mcan0 {
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pinctrl-names = "default";
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phys = <&transceiver0>;
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};
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#include "k3-j7200-ti-ipc-firmware.dtsi"
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130
arch/arm64/boot/dts/ti/k3-j7200-ti-ipc-firmware.dtsi
Normal file
130
arch/arm64/boot/dts/ti/k3-j7200-ti-ipc-firmware.dtsi
Normal file
@@ -0,0 +1,130 @@
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// SPDX-License-Identifier: GPL-2.0-only OR MIT
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/**
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* Device Tree Source for enabling IPC using TI SDK firmware on J7200 SoCs
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*
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* Copyright (C) 2020-2025 Texas Instruments Incorporated - https://www.ti.com/
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*/
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&reserved_memory {
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mcu_r5fss0_core1_dma_memory_region: memory@a1000000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa1000000 0x00 0x100000>;
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no-map;
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};
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mcu_r5fss0_core1_memory_region: memory@a1100000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa1100000 0x00 0xf00000>;
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no-map;
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};
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main_r5fss0_core0_dma_memory_region: memory@a2000000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa2000000 0x00 0x100000>;
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no-map;
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};
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main_r5fss0_core0_memory_region: memory@a2100000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa2100000 0x00 0xf00000>;
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no-map;
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};
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main_r5fss0_core1_dma_memory_region: memory@a3000000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa3000000 0x00 0x100000>;
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no-map;
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};
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main_r5fss0_core1_memory_region: memory@a3100000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa3100000 0x00 0xf00000>;
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no-map;
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};
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rtos_ipc_memory_region: memory@a4000000 {
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reg = <0x00 0xa4000000 0x00 0x00800000>;
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alignment = <0x1000>;
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no-map;
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};
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};
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&mailbox0_cluster0 {
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status = "okay";
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interrupts = <436>;
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mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
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ti,mbox-rx = <0 0 0>;
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ti,mbox-tx = <1 0 0>;
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};
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mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
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ti,mbox-rx = <2 0 0>;
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ti,mbox-tx = <3 0 0>;
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};
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};
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&mailbox0_cluster1 {
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status = "okay";
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interrupts = <432>;
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mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
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ti,mbox-rx = <0 0 0>;
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ti,mbox-tx = <1 0 0>;
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};
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mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
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ti,mbox-rx = <2 0 0>;
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ti,mbox-tx = <3 0 0>;
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};
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};
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/* Timers are used by Remoteproc firmware */
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&main_timer0 {
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status = "reserved";
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};
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&main_timer1 {
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status = "reserved";
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};
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&main_timer2 {
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status = "reserved";
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};
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&mcu_r5fss0 {
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status = "okay";
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};
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&mcu_r5fss0_core0 {
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mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
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memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
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<&mcu_r5fss0_core0_memory_region>;
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status = "okay";
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};
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&mcu_r5fss0_core1 {
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mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>;
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memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
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<&mcu_r5fss0_core1_memory_region>;
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status = "okay";
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};
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&main_r5fss0 {
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ti,cluster-mode = <0>;
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status = "okay";
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};
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&main_r5fss0_core0 {
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mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>;
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memory-region = <&main_r5fss0_core0_dma_memory_region>,
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<&main_r5fss0_core0_memory_region>;
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status = "okay";
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};
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&main_r5fss0_core1 {
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mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>;
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memory-region = <&main_r5fss0_core1_dma_memory_region>,
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<&main_r5fss0_core1_memory_region>;
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status = "okay";
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};
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