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scsi: ufs: renesas: Replace init data by init code
Since initialization of the UFS controller on R-Car S4-8 ES1.0 requires only static values, the driver uses initialization data stored in the const ufs_param[] array. However, other UFS controller variants (R-Car S4-8 ES1.2) require dynamic values, like those obtained from E-FUSE. Refactor the initialization code to prepare for this. This also reduces kernel size by almost 30 KiB. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/3520e27ac7ff512de6508f630eee3c1689a7c73d.1741179611.git.geert+renesas@glider.be Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
This commit is contained in:
Yoshihiro Shimoda
committed by
Martin K. Petersen
Martin K. Petersen
parent
67407b84e0
commit
c4e83573c3
@@ -39,98 +39,6 @@ enum ufs_renesas_init_param_mode {
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MODE_WRITE,
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};
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#define PARAM_RESTORE(_reg, _index) \
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{ .mode = MODE_RESTORE, .reg = _reg, .index = _index }
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#define PARAM_SET(_index, _set) \
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{ .mode = MODE_SET, .index = _index, .u.set = _set }
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#define PARAM_SAVE(_reg, _mask, _index) \
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{ .mode = MODE_SAVE, .reg = _reg, .mask = (u32)(_mask), \
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.index = _index }
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#define PARAM_POLL(_reg, _expected, _mask) \
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{ .mode = MODE_POLL, .reg = _reg, .u.expected = _expected, \
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.mask = (u32)(_mask) }
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#define PARAM_WAIT(_delay_us) \
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{ .mode = MODE_WAIT, .u.delay_us = _delay_us }
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#define PARAM_WRITE(_reg, _val) \
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{ .mode = MODE_WRITE, .reg = _reg, .u.val = _val }
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#define PARAM_WRITE_D0_D4(_d0, _d4) \
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PARAM_WRITE(0xd0, _d0), PARAM_WRITE(0xd4, _d4)
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#define PARAM_WRITE_800_80C_POLL(_addr, _data_800) \
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PARAM_WRITE_D0_D4(0x0000080c, 0x00000100), \
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PARAM_WRITE_D0_D4(0x00000800, ((_data_800) << 16) | BIT(8) | (_addr)), \
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PARAM_WRITE(0xd0, 0x0000080c), \
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PARAM_POLL(0xd4, BIT(8), BIT(8))
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#define PARAM_RESTORE_800_80C_POLL(_index) \
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PARAM_WRITE_D0_D4(0x0000080c, 0x00000100), \
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PARAM_WRITE(0xd0, 0x00000800), \
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PARAM_RESTORE(0xd4, _index), \
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PARAM_WRITE(0xd0, 0x0000080c), \
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PARAM_POLL(0xd4, BIT(8), BIT(8))
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#define PARAM_WRITE_804_80C_POLL(_addr, _data_804) \
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PARAM_WRITE_D0_D4(0x0000080c, 0x00000100), \
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PARAM_WRITE_D0_D4(0x00000804, ((_data_804) << 16) | BIT(8) | (_addr)), \
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PARAM_WRITE(0xd0, 0x0000080c), \
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PARAM_POLL(0xd4, BIT(8), BIT(8))
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#define PARAM_WRITE_828_82C_POLL(_data_828) \
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PARAM_WRITE_D0_D4(0x0000082c, 0x0f000000), \
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PARAM_WRITE_D0_D4(0x00000828, _data_828), \
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PARAM_WRITE(0xd0, 0x0000082c), \
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PARAM_POLL(0xd4, _data_828, _data_828)
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#define PARAM_WRITE_PHY(_addr16, _data16) \
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PARAM_WRITE(0xf0, 1), \
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PARAM_WRITE_800_80C_POLL(0x16, (_addr16) & 0xff), \
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PARAM_WRITE_800_80C_POLL(0x17, ((_addr16) >> 8) & 0xff), \
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PARAM_WRITE_800_80C_POLL(0x18, (_data16) & 0xff), \
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PARAM_WRITE_800_80C_POLL(0x19, ((_data16) >> 8) & 0xff), \
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PARAM_WRITE_800_80C_POLL(0x1c, 0x01), \
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PARAM_WRITE_828_82C_POLL(0x0f000000), \
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PARAM_WRITE(0xf0, 0)
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#define PARAM_SET_PHY(_addr16, _data16) \
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PARAM_WRITE(0xf0, 1), \
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PARAM_WRITE_800_80C_POLL(0x16, (_addr16) & 0xff), \
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PARAM_WRITE_800_80C_POLL(0x17, ((_addr16) >> 8) & 0xff), \
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PARAM_WRITE_800_80C_POLL(0x1c, 0x01), \
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PARAM_WRITE_828_82C_POLL(0x0f000000), \
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PARAM_WRITE_804_80C_POLL(0x1a, 0), \
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PARAM_WRITE(0xd0, 0x00000808), \
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PARAM_SAVE(0xd4, 0xff, SET_PHY_INDEX_LO), \
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PARAM_WRITE_804_80C_POLL(0x1b, 0), \
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PARAM_WRITE(0xd0, 0x00000808), \
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PARAM_SAVE(0xd4, 0xff, SET_PHY_INDEX_HI), \
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PARAM_WRITE_828_82C_POLL(0x0f000000), \
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PARAM_WRITE(0xf0, 0), \
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PARAM_WRITE(0xf0, 1), \
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PARAM_WRITE_800_80C_POLL(0x16, (_addr16) & 0xff), \
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PARAM_WRITE_800_80C_POLL(0x17, ((_addr16) >> 8) & 0xff), \
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PARAM_SET(SET_PHY_INDEX_LO, ((_data16 & 0xff) << 16) | BIT(8) | 0x18), \
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PARAM_RESTORE_800_80C_POLL(SET_PHY_INDEX_LO), \
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PARAM_SET(SET_PHY_INDEX_HI, (((_data16 >> 8) & 0xff) << 16) | BIT(8) | 0x19), \
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PARAM_RESTORE_800_80C_POLL(SET_PHY_INDEX_HI), \
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PARAM_WRITE_800_80C_POLL(0x1c, 0x01), \
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PARAM_WRITE_828_82C_POLL(0x0f000000), \
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PARAM_WRITE(0xf0, 0)
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#define PARAM_INDIRECT_WRITE(_gpio, _addr, _data_800) \
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PARAM_WRITE(0xf0, _gpio), \
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PARAM_WRITE_800_80C_POLL(_addr, _data_800), \
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PARAM_WRITE_828_82C_POLL(0x0f000000), \
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PARAM_WRITE(0xf0, 0)
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#define PARAM_INDIRECT_POLL(_gpio, _addr, _expected, _mask) \
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PARAM_WRITE(0xf0, _gpio), \
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PARAM_WRITE_800_80C_POLL(_addr, 0), \
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PARAM_WRITE(0xd0, 0x00000808), \
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PARAM_POLL(0xd4, _expected, _mask), \
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PARAM_WRITE(0xf0, 0)
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struct ufs_renesas_init_param {
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enum ufs_renesas_init_param_mode mode;
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u32 reg;
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@@ -144,135 +52,6 @@ struct ufs_renesas_init_param {
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u32 index;
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};
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/* This setting is for SERIES B */
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static const struct ufs_renesas_init_param ufs_param[] = {
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PARAM_WRITE(0xc0, 0x49425308),
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PARAM_WRITE_D0_D4(0x00000104, 0x00000002),
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PARAM_WAIT(1),
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PARAM_WRITE_D0_D4(0x00000828, 0x00000200),
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PARAM_WAIT(1),
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PARAM_WRITE_D0_D4(0x00000828, 0x00000000),
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PARAM_WRITE_D0_D4(0x00000104, 0x00000001),
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PARAM_WRITE_D0_D4(0x00000940, 0x00000001),
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PARAM_WAIT(1),
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PARAM_WRITE_D0_D4(0x00000940, 0x00000000),
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PARAM_WRITE(0xc0, 0x49425308),
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PARAM_WRITE(0xc0, 0x41584901),
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PARAM_WRITE_D0_D4(0x0000080c, 0x00000100),
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PARAM_WRITE_D0_D4(0x00000804, 0x00000000),
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PARAM_WRITE(0xd0, 0x0000080c),
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PARAM_POLL(0xd4, BIT(8), BIT(8)),
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PARAM_WRITE(REG_CONTROLLER_ENABLE, 0x00000001),
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PARAM_WRITE(0xd0, 0x00000804),
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PARAM_POLL(0xd4, BIT(8) | BIT(6) | BIT(0), BIT(8) | BIT(6) | BIT(0)),
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PARAM_WRITE(0xd0, 0x00000d00),
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PARAM_SAVE(0xd4, 0x0000ffff, TIMER_INDEX),
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PARAM_WRITE(0xd4, 0x00000000),
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PARAM_WRITE_D0_D4(0x0000082c, 0x0f000000),
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PARAM_WRITE_D0_D4(0x00000828, 0x08000000),
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PARAM_WRITE(0xd0, 0x0000082c),
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PARAM_POLL(0xd4, BIT(27), BIT(27)),
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PARAM_WRITE(0xd0, 0x00000d2c),
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PARAM_POLL(0xd4, BIT(0), BIT(0)),
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/* phy setup */
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PARAM_INDIRECT_WRITE(1, 0x01, 0x001f),
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PARAM_INDIRECT_WRITE(7, 0x5d, 0x0014),
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PARAM_INDIRECT_WRITE(7, 0x5e, 0x0014),
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PARAM_INDIRECT_WRITE(7, 0x0d, 0x0003),
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PARAM_INDIRECT_WRITE(7, 0x0e, 0x0007),
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PARAM_INDIRECT_WRITE(7, 0x5f, 0x0003),
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PARAM_INDIRECT_WRITE(7, 0x60, 0x0003),
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PARAM_INDIRECT_WRITE(7, 0x5b, 0x00a6),
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PARAM_INDIRECT_WRITE(7, 0x5c, 0x0003),
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PARAM_INDIRECT_POLL(7, 0x3c, 0, BIT(7)),
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PARAM_INDIRECT_POLL(7, 0x4c, 0, BIT(4)),
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PARAM_INDIRECT_WRITE(1, 0x32, 0x0080),
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PARAM_INDIRECT_WRITE(1, 0x1f, 0x0001),
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PARAM_INDIRECT_WRITE(0, 0x2c, 0x0001),
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PARAM_INDIRECT_WRITE(0, 0x32, 0x0087),
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PARAM_INDIRECT_WRITE(1, 0x4d, 0x0061),
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PARAM_INDIRECT_WRITE(4, 0x9b, 0x0009),
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PARAM_INDIRECT_WRITE(4, 0xa6, 0x0005),
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PARAM_INDIRECT_WRITE(4, 0xa5, 0x0058),
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PARAM_INDIRECT_WRITE(1, 0x39, 0x0027),
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PARAM_INDIRECT_WRITE(1, 0x47, 0x004c),
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PARAM_INDIRECT_WRITE(7, 0x0d, 0x0002),
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PARAM_INDIRECT_WRITE(7, 0x0e, 0x0007),
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PARAM_WRITE_PHY(0x0028, 0x0061),
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PARAM_WRITE_PHY(0x4014, 0x0061),
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PARAM_SET_PHY(0x401c, BIT(2)),
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PARAM_WRITE_PHY(0x4000, 0x0000),
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PARAM_WRITE_PHY(0x4001, 0x0000),
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PARAM_WRITE_PHY(0x10ae, 0x0001),
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PARAM_WRITE_PHY(0x10ad, 0x0000),
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PARAM_WRITE_PHY(0x10af, 0x0001),
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PARAM_WRITE_PHY(0x10b6, 0x0001),
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PARAM_WRITE_PHY(0x10ae, 0x0000),
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PARAM_WRITE_PHY(0x10ae, 0x0001),
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PARAM_WRITE_PHY(0x10ad, 0x0000),
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PARAM_WRITE_PHY(0x10af, 0x0002),
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PARAM_WRITE_PHY(0x10b6, 0x0001),
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PARAM_WRITE_PHY(0x10ae, 0x0000),
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PARAM_WRITE_PHY(0x10ae, 0x0001),
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PARAM_WRITE_PHY(0x10ad, 0x0080),
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PARAM_WRITE_PHY(0x10af, 0x0000),
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PARAM_WRITE_PHY(0x10b6, 0x0001),
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PARAM_WRITE_PHY(0x10ae, 0x0000),
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PARAM_WRITE_PHY(0x10ae, 0x0001),
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PARAM_WRITE_PHY(0x10ad, 0x0080),
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PARAM_WRITE_PHY(0x10af, 0x001a),
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PARAM_WRITE_PHY(0x10b6, 0x0001),
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PARAM_WRITE_PHY(0x10ae, 0x0000),
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PARAM_INDIRECT_WRITE(7, 0x70, 0x0016),
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PARAM_INDIRECT_WRITE(7, 0x71, 0x0016),
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PARAM_INDIRECT_WRITE(7, 0x72, 0x0014),
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PARAM_INDIRECT_WRITE(7, 0x73, 0x0014),
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PARAM_INDIRECT_WRITE(7, 0x74, 0x0000),
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PARAM_INDIRECT_WRITE(7, 0x75, 0x0000),
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PARAM_INDIRECT_WRITE(7, 0x76, 0x0010),
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PARAM_INDIRECT_WRITE(7, 0x77, 0x0010),
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PARAM_INDIRECT_WRITE(7, 0x78, 0x00ff),
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PARAM_INDIRECT_WRITE(7, 0x79, 0x0000),
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PARAM_INDIRECT_WRITE(7, 0x19, 0x0007),
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PARAM_INDIRECT_WRITE(7, 0x1a, 0x0007),
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PARAM_INDIRECT_WRITE(7, 0x24, 0x000c),
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PARAM_INDIRECT_WRITE(7, 0x25, 0x000c),
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PARAM_INDIRECT_WRITE(7, 0x62, 0x0000),
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PARAM_INDIRECT_WRITE(7, 0x63, 0x0000),
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PARAM_INDIRECT_WRITE(7, 0x5d, 0x0014),
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PARAM_INDIRECT_WRITE(7, 0x5e, 0x0017),
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PARAM_INDIRECT_WRITE(7, 0x5d, 0x0004),
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PARAM_INDIRECT_WRITE(7, 0x5e, 0x0017),
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PARAM_INDIRECT_POLL(7, 0x55, 0, BIT(6)),
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PARAM_INDIRECT_POLL(7, 0x41, 0, BIT(7)),
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/* end of phy setup */
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PARAM_WRITE(0xf0, 0),
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PARAM_WRITE(0xd0, 0x00000d00),
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PARAM_RESTORE(0xd4, TIMER_INDEX),
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};
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static void ufs_renesas_dbg_register_dump(struct ufs_hba *hba)
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{
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ufshcd_dump_regs(hba, 0xc0, 0x40, "regs: 0xc0 + ");
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@@ -320,13 +99,295 @@ static void ufs_renesas_reg_control(struct ufs_hba *hba,
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}
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}
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static void ufs_renesas_poll(struct ufs_hba *hba, u32 reg, u32 expected, u32 mask)
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{
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struct ufs_renesas_init_param param = {
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.mode = MODE_POLL,
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.reg = reg,
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.u.expected = expected,
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.mask = mask,
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};
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ufs_renesas_reg_control(hba, ¶m);
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}
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static void ufs_renesas_restore(struct ufs_hba *hba, u32 reg, u32 index)
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{
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struct ufs_renesas_init_param param = {
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.mode = MODE_RESTORE,
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.reg = reg,
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.index = index,
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};
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ufs_renesas_reg_control(hba, ¶m);
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}
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static void ufs_renesas_save(struct ufs_hba *hba, u32 reg, u32 mask, u32 index)
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{
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struct ufs_renesas_init_param param = {
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.mode = MODE_SAVE,
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.reg = reg,
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.mask = mask,
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.index = index,
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};
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ufs_renesas_reg_control(hba, ¶m);
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}
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static void ufs_renesas_set(struct ufs_hba *hba, u32 index, u32 set)
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{
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struct ufs_renesas_init_param param = {
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.mode = MODE_SAVE,
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.index = index,
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.u.set = set,
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};
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ufs_renesas_reg_control(hba, ¶m);
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}
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static void ufs_renesas_wait(struct ufs_hba *hba, u32 delay_us)
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{
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struct ufs_renesas_init_param param = {
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.mode = MODE_WAIT,
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.u.delay_us = delay_us,
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};
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ufs_renesas_reg_control(hba, ¶m);
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}
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static void ufs_renesas_write(struct ufs_hba *hba, u32 reg, u32 value)
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{
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struct ufs_renesas_init_param param = {
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.mode = MODE_WRITE,
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.reg = reg,
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.u.val = value,
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};
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ufs_renesas_reg_control(hba, ¶m);
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}
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static void ufs_renesas_write_d0_d4(struct ufs_hba *hba, u32 data_d0, u32 data_d4)
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{
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ufs_renesas_write(hba, 0xd0, data_d0);
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ufs_renesas_write(hba, 0xd4, data_d4);
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}
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static void ufs_renesas_write_800_80c_poll(struct ufs_hba *hba, u32 addr,
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u32 data_800)
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{
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ufs_renesas_write_d0_d4(hba, 0x0000080c, 0x00000100);
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ufs_renesas_write_d0_d4(hba, 0x00000800, (data_800 << 16) | BIT(8) | addr);
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ufs_renesas_write(hba, 0xd0, 0x0000080c);
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ufs_renesas_poll(hba, 0xd4, BIT(8), BIT(8));
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}
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static void ufs_renesas_restore_800_80c_poll(struct ufs_hba *hba, u32 index)
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{
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ufs_renesas_write_d0_d4(hba, 0x0000080c, 0x00000100);
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ufs_renesas_write(hba, 0xd0, 0x00000800);
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ufs_renesas_restore(hba, 0xd4, index);
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ufs_renesas_write(hba, 0xd0, 0x0000080c);
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ufs_renesas_poll(hba, 0xd4, BIT(8), BIT(8));
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}
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static void ufs_renesas_write_804_80c_poll(struct ufs_hba *hba, u32 addr, u32 data_804)
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{
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ufs_renesas_write_d0_d4(hba, 0x0000080c, 0x00000100);
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ufs_renesas_write_d0_d4(hba, 0x00000804, (data_804 << 16) | BIT(8) | addr);
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ufs_renesas_write(hba, 0xd0, 0x0000080c);
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ufs_renesas_poll(hba, 0xd4, BIT(8), BIT(8));
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}
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static void ufs_renesas_write_828_82c_poll(struct ufs_hba *hba, u32 data_828)
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{
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ufs_renesas_write_d0_d4(hba, 0x0000082c, 0x0f000000);
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ufs_renesas_write_d0_d4(hba, 0x00000828, data_828);
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ufs_renesas_write(hba, 0xd0, 0x0000082c);
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ufs_renesas_poll(hba, 0xd4, data_828, data_828);
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}
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static void ufs_renesas_write_phy(struct ufs_hba *hba, u32 addr16, u32 data16)
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{
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ufs_renesas_write(hba, 0xf0, 1);
|
||||
ufs_renesas_write_800_80c_poll(hba, 0x16, addr16 & 0xff);
|
||||
ufs_renesas_write_800_80c_poll(hba, 0x17, (addr16 >> 8) & 0xff);
|
||||
ufs_renesas_write_800_80c_poll(hba, 0x18, data16 & 0xff);
|
||||
ufs_renesas_write_800_80c_poll(hba, 0x19, (data16 >> 8) & 0xff);
|
||||
ufs_renesas_write_800_80c_poll(hba, 0x1c, 0x01);
|
||||
ufs_renesas_write_828_82c_poll(hba, 0x0f000000);
|
||||
ufs_renesas_write(hba, 0xf0, 0);
|
||||
}
|
||||
|
||||
static void ufs_renesas_set_phy(struct ufs_hba *hba, u32 addr16, u32 data16)
|
||||
{
|
||||
ufs_renesas_write(hba, 0xf0, 1);
|
||||
ufs_renesas_write_800_80c_poll(hba, 0x16, addr16 & 0xff);
|
||||
ufs_renesas_write_800_80c_poll(hba, 0x17, (addr16 >> 8) & 0xff);
|
||||
ufs_renesas_write_800_80c_poll(hba, 0x1c, 0x01);
|
||||
ufs_renesas_write_828_82c_poll(hba, 0x0f000000);
|
||||
ufs_renesas_write_804_80c_poll(hba, 0x1a, 0);
|
||||
ufs_renesas_write(hba, 0xd0, 0x00000808);
|
||||
ufs_renesas_save(hba, 0xd4, 0xff, SET_PHY_INDEX_LO);
|
||||
ufs_renesas_write_804_80c_poll(hba, 0x1b, 0);
|
||||
ufs_renesas_write(hba, 0xd0, 0x00000808);
|
||||
ufs_renesas_save(hba, 0xd4, 0xff, SET_PHY_INDEX_HI);
|
||||
ufs_renesas_write_828_82c_poll(hba, 0x0f000000);
|
||||
ufs_renesas_write(hba, 0xf0, 0);
|
||||
ufs_renesas_write(hba, 0xf0, 1);
|
||||
ufs_renesas_write_800_80c_poll(hba, 0x16, addr16 & 0xff);
|
||||
ufs_renesas_write_800_80c_poll(hba, 0x17, (addr16 >> 8) & 0xff);
|
||||
ufs_renesas_set(hba, SET_PHY_INDEX_LO, ((data16 & 0xff) << 16) | BIT(8) | 0x18);
|
||||
ufs_renesas_restore_800_80c_poll(hba, SET_PHY_INDEX_LO);
|
||||
ufs_renesas_set(hba, SET_PHY_INDEX_HI, (((data16 >> 8) & 0xff) << 16) | BIT(8) | 0x19);
|
||||
ufs_renesas_restore_800_80c_poll(hba, SET_PHY_INDEX_HI);
|
||||
ufs_renesas_write_800_80c_poll(hba, 0x1c, 0x01);
|
||||
ufs_renesas_write_828_82c_poll(hba, 0x0f000000);
|
||||
ufs_renesas_write(hba, 0xf0, 0);
|
||||
}
|
||||
|
||||
static void ufs_renesas_indirect_write(struct ufs_hba *hba, u32 gpio, u32 addr,
|
||||
u32 data_800)
|
||||
{
|
||||
ufs_renesas_write(hba, 0xf0, gpio);
|
||||
ufs_renesas_write_800_80c_poll(hba, addr, data_800);
|
||||
ufs_renesas_write_828_82c_poll(hba, 0x0f000000);
|
||||
ufs_renesas_write(hba, 0xf0, 0);
|
||||
}
|
||||
|
||||
static void ufs_renesas_indirect_poll(struct ufs_hba *hba, u32 gpio, u32 addr,
|
||||
u32 expected, u32 mask)
|
||||
{
|
||||
ufs_renesas_write(hba, 0xf0, gpio);
|
||||
ufs_renesas_write_800_80c_poll(hba, addr, 0);
|
||||
ufs_renesas_write(hba, 0xd0, 0x00000808);
|
||||
ufs_renesas_poll(hba, 0xd4, expected, mask);
|
||||
ufs_renesas_write(hba, 0xf0, 0);
|
||||
}
|
||||
|
||||
static void ufs_renesas_pre_init(struct ufs_hba *hba)
|
||||
{
|
||||
const struct ufs_renesas_init_param *p = ufs_param;
|
||||
unsigned int i;
|
||||
/* This setting is for SERIES B */
|
||||
ufs_renesas_write(hba, 0xc0, 0x49425308);
|
||||
ufs_renesas_write_d0_d4(hba, 0x00000104, 0x00000002);
|
||||
ufs_renesas_wait(hba, 1);
|
||||
ufs_renesas_write_d0_d4(hba, 0x00000828, 0x00000200);
|
||||
ufs_renesas_wait(hba, 1);
|
||||
ufs_renesas_write_d0_d4(hba, 0x00000828, 0x00000000);
|
||||
ufs_renesas_write_d0_d4(hba, 0x00000104, 0x00000001);
|
||||
ufs_renesas_write_d0_d4(hba, 0x00000940, 0x00000001);
|
||||
ufs_renesas_wait(hba, 1);
|
||||
ufs_renesas_write_d0_d4(hba, 0x00000940, 0x00000000);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(ufs_param); i++)
|
||||
ufs_renesas_reg_control(hba, &p[i]);
|
||||
ufs_renesas_write(hba, 0xc0, 0x49425308);
|
||||
ufs_renesas_write(hba, 0xc0, 0x41584901);
|
||||
|
||||
ufs_renesas_write_d0_d4(hba, 0x0000080c, 0x00000100);
|
||||
ufs_renesas_write_d0_d4(hba, 0x00000804, 0x00000000);
|
||||
ufs_renesas_write(hba, 0xd0, 0x0000080c);
|
||||
ufs_renesas_poll(hba, 0xd4, BIT(8), BIT(8));
|
||||
|
||||
ufs_renesas_write(hba, REG_CONTROLLER_ENABLE, 0x00000001);
|
||||
|
||||
ufs_renesas_write(hba, 0xd0, 0x00000804);
|
||||
ufs_renesas_poll(hba, 0xd4, BIT(8) | BIT(6) | BIT(0), BIT(8) | BIT(6) | BIT(0));
|
||||
|
||||
ufs_renesas_write(hba, 0xd0, 0x00000d00);
|
||||
ufs_renesas_save(hba, 0xd4, 0x0000ffff, TIMER_INDEX);
|
||||
ufs_renesas_write(hba, 0xd4, 0x00000000);
|
||||
ufs_renesas_write_d0_d4(hba, 0x0000082c, 0x0f000000);
|
||||
ufs_renesas_write_d0_d4(hba, 0x00000828, 0x08000000);
|
||||
ufs_renesas_write(hba, 0xd0, 0x0000082c);
|
||||
ufs_renesas_poll(hba, 0xd4, BIT(27), BIT(27));
|
||||
ufs_renesas_write(hba, 0xd0, 0x00000d2c);
|
||||
ufs_renesas_poll(hba, 0xd4, BIT(0), BIT(0));
|
||||
|
||||
/* phy setup */
|
||||
ufs_renesas_indirect_write(hba, 1, 0x01, 0x001f);
|
||||
ufs_renesas_indirect_write(hba, 7, 0x5d, 0x0014);
|
||||
ufs_renesas_indirect_write(hba, 7, 0x5e, 0x0014);
|
||||
ufs_renesas_indirect_write(hba, 7, 0x0d, 0x0003);
|
||||
ufs_renesas_indirect_write(hba, 7, 0x0e, 0x0007);
|
||||
ufs_renesas_indirect_write(hba, 7, 0x5f, 0x0003);
|
||||
ufs_renesas_indirect_write(hba, 7, 0x60, 0x0003);
|
||||
ufs_renesas_indirect_write(hba, 7, 0x5b, 0x00a6);
|
||||
ufs_renesas_indirect_write(hba, 7, 0x5c, 0x0003);
|
||||
|
||||
ufs_renesas_indirect_poll(hba, 7, 0x3c, 0, BIT(7));
|
||||
ufs_renesas_indirect_poll(hba, 7, 0x4c, 0, BIT(4));
|
||||
|
||||
ufs_renesas_indirect_write(hba, 1, 0x32, 0x0080);
|
||||
ufs_renesas_indirect_write(hba, 1, 0x1f, 0x0001);
|
||||
ufs_renesas_indirect_write(hba, 0, 0x2c, 0x0001);
|
||||
ufs_renesas_indirect_write(hba, 0, 0x32, 0x0087);
|
||||
|
||||
ufs_renesas_indirect_write(hba, 1, 0x4d, 0x0061);
|
||||
ufs_renesas_indirect_write(hba, 4, 0x9b, 0x0009);
|
||||
ufs_renesas_indirect_write(hba, 4, 0xa6, 0x0005);
|
||||
ufs_renesas_indirect_write(hba, 4, 0xa5, 0x0058);
|
||||
ufs_renesas_indirect_write(hba, 1, 0x39, 0x0027);
|
||||
ufs_renesas_indirect_write(hba, 1, 0x47, 0x004c);
|
||||
|
||||
ufs_renesas_indirect_write(hba, 7, 0x0d, 0x0002);
|
||||
ufs_renesas_indirect_write(hba, 7, 0x0e, 0x0007);
|
||||
|
||||
ufs_renesas_write_phy(hba, 0x0028, 0x0061);
|
||||
ufs_renesas_write_phy(hba, 0x4014, 0x0061);
|
||||
ufs_renesas_set_phy(hba, 0x401c, BIT(2));
|
||||
ufs_renesas_write_phy(hba, 0x4000, 0x0000);
|
||||
ufs_renesas_write_phy(hba, 0x4001, 0x0000);
|
||||
|
||||
ufs_renesas_write_phy(hba, 0x10ae, 0x0001);
|
||||
ufs_renesas_write_phy(hba, 0x10ad, 0x0000);
|
||||
ufs_renesas_write_phy(hba, 0x10af, 0x0001);
|
||||
ufs_renesas_write_phy(hba, 0x10b6, 0x0001);
|
||||
ufs_renesas_write_phy(hba, 0x10ae, 0x0000);
|
||||
|
||||
ufs_renesas_write_phy(hba, 0x10ae, 0x0001);
|
||||
ufs_renesas_write_phy(hba, 0x10ad, 0x0000);
|
||||
ufs_renesas_write_phy(hba, 0x10af, 0x0002);
|
||||
ufs_renesas_write_phy(hba, 0x10b6, 0x0001);
|
||||
ufs_renesas_write_phy(hba, 0x10ae, 0x0000);
|
||||
|
||||
ufs_renesas_write_phy(hba, 0x10ae, 0x0001);
|
||||
ufs_renesas_write_phy(hba, 0x10ad, 0x0080);
|
||||
ufs_renesas_write_phy(hba, 0x10af, 0x0000);
|
||||
ufs_renesas_write_phy(hba, 0x10b6, 0x0001);
|
||||
ufs_renesas_write_phy(hba, 0x10ae, 0x0000);
|
||||
|
||||
ufs_renesas_write_phy(hba, 0x10ae, 0x0001);
|
||||
ufs_renesas_write_phy(hba, 0x10ad, 0x0080);
|
||||
ufs_renesas_write_phy(hba, 0x10af, 0x001a);
|
||||
ufs_renesas_write_phy(hba, 0x10b6, 0x0001);
|
||||
ufs_renesas_write_phy(hba, 0x10ae, 0x0000);
|
||||
|
||||
ufs_renesas_indirect_write(hba, 7, 0x70, 0x0016);
|
||||
ufs_renesas_indirect_write(hba, 7, 0x71, 0x0016);
|
||||
ufs_renesas_indirect_write(hba, 7, 0x72, 0x0014);
|
||||
ufs_renesas_indirect_write(hba, 7, 0x73, 0x0014);
|
||||
ufs_renesas_indirect_write(hba, 7, 0x74, 0x0000);
|
||||
ufs_renesas_indirect_write(hba, 7, 0x75, 0x0000);
|
||||
ufs_renesas_indirect_write(hba, 7, 0x76, 0x0010);
|
||||
ufs_renesas_indirect_write(hba, 7, 0x77, 0x0010);
|
||||
ufs_renesas_indirect_write(hba, 7, 0x78, 0x00ff);
|
||||
ufs_renesas_indirect_write(hba, 7, 0x79, 0x0000);
|
||||
|
||||
ufs_renesas_indirect_write(hba, 7, 0x19, 0x0007);
|
||||
ufs_renesas_indirect_write(hba, 7, 0x1a, 0x0007);
|
||||
ufs_renesas_indirect_write(hba, 7, 0x24, 0x000c);
|
||||
ufs_renesas_indirect_write(hba, 7, 0x25, 0x000c);
|
||||
ufs_renesas_indirect_write(hba, 7, 0x62, 0x0000);
|
||||
ufs_renesas_indirect_write(hba, 7, 0x63, 0x0000);
|
||||
ufs_renesas_indirect_write(hba, 7, 0x5d, 0x0014);
|
||||
ufs_renesas_indirect_write(hba, 7, 0x5e, 0x0017);
|
||||
ufs_renesas_indirect_write(hba, 7, 0x5d, 0x0004);
|
||||
ufs_renesas_indirect_write(hba, 7, 0x5e, 0x0017);
|
||||
ufs_renesas_indirect_poll(hba, 7, 0x55, 0, BIT(6));
|
||||
ufs_renesas_indirect_poll(hba, 7, 0x41, 0, BIT(7));
|
||||
/* end of phy setup */
|
||||
|
||||
ufs_renesas_write(hba, 0xf0, 0);
|
||||
ufs_renesas_write(hba, 0xd0, 0x00000d00);
|
||||
ufs_renesas_restore(hba, 0xd4, TIMER_INDEX);
|
||||
}
|
||||
|
||||
static int ufs_renesas_hce_enable_notify(struct ufs_hba *hba,
|
||||
|
||||
Reference in New Issue
Block a user