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drm/xe/rtp: Add kunit tests to exercise FIELD_SET_FUNC action

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Add a couple additional tests to the RTP kunit suite that ensure
FIELD_SET_FUNC() actions are evaluated properly and the values properly
consolidate/conflict with values coming from other literal SET/FIELD_SET
rules.

Suggested-by: Gustavo Sousa <gustavo.sousa@intel.com>
Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
Link: https://patch.msgid.link/20260617-rtp_with_dynamic_vals-v2-5-3f4cb34c2ea1@intel.com
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
This commit is contained in:
Matt Roper
2026-06-17 12:24:49 -07:00
parent 4ff7902a64
commit c47ffed42b
1 changed files with 52 additions and 0 deletions
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52
drivers/gpu/drm/xe/tests/xe_rtp_test.c
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@@ -280,6 +280,11 @@ static void xe_rtp_rules_tests(struct kunit *test)
KUNIT_EXPECT_EQ(test, err, param->expected_err);
}
static u32 bits_2_3_set(struct xe_gt *gt, struct xe_hw_engine *hwe)
{
return REG_BIT(2) | REG_BIT(3);
}
static const struct rtp_to_sr_test_case rtp_to_sr_cases[] = {
{
.name = "coalesce-same-reg",
@@ -300,6 +305,29 @@ static const struct rtp_to_sr_test_case rtp_to_sr_cases[] = {
},
),
},
{
.name = "coalesce-same-reg-literal-and-func",
.expected_reg = REGULAR_REG1,
.expected_set_bits = REG_BIT(0) | REG_BIT(1) | REG_BIT(2) | REG_BIT(3),
.expected_clr_bits = REG_BIT(0) | REG_BIT(1) | REG_BIT(2) | REG_BIT(3),
.expected_active = BIT(0) | BIT(1),
.expected_count_sr_entries = 1,
/* Different bits on the same register: create a single entry */
.table = XE_RTP_TABLE_SR(
{ XE_RTP_NAME("basic-1"),
XE_RTP_RULES(FUNC(match_yes)),
XE_RTP_ACTIONS(FIELD_SET(REGULAR_REG1,
REG_BIT(0) | REG_BIT(1),
REG_BIT(0) | REG_BIT(1)))
},
{ XE_RTP_NAME("basic-2"),
XE_RTP_RULES(FUNC(match_yes)),
XE_RTP_ACTIONS(FIELD_SET_FUNC(REGULAR_REG1,
REG_BIT(2) | REG_BIT(3),
bits_2_3_set))
},
),
},
{
.name = "no-match-no-add",
.expected_reg = REGULAR_REG1,
@@ -417,6 +445,30 @@ static const struct rtp_to_sr_test_case rtp_to_sr_cases[] = {
},
),
},
{
.name = "conflict-not-disjoint-literal-and-func",
.expected_reg = REGULAR_REG1,
.expected_set_bits = REG_BIT(1) | REG_BIT(2),
.expected_clr_bits = REG_BIT(1) | REG_BIT(2),
.expected_active = BIT(0) | BIT(1),
.expected_count_sr_entries = 1,
.expected_sr_errors = 1,
.table = XE_RTP_TABLE_SR(
{ XE_RTP_NAME("basic-1"),
XE_RTP_RULES(FUNC(match_yes)),
XE_RTP_ACTIONS(FIELD_SET(REGULAR_REG1,
REG_BIT(1) | REG_BIT(2),
REG_BIT(1) | REG_BIT(2)))
},
/* drop: bits are not disjoint with previous entries */
{ XE_RTP_NAME("basic-2"),
XE_RTP_RULES(FUNC(match_yes)),
XE_RTP_ACTIONS(FIELD_SET_FUNC(REGULAR_REG1,
REG_BIT(2) | REG_BIT(3),
bits_2_3_set))
},
),
},
{
.name = "conflict-reg-type",
.expected_reg = REGULAR_REG1,