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net: stmmac: convert plat_stmmacenet_data booleans to type bool

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Convert members of struct plat_stmmacenet_data that are booleans to
type 'bool' and ensure their initialisers are true/false. Move the
has_xxx for the GMAC cores together, and move the COE members to the
end of the list of bool to avoid unused holes in the struct.

Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Reviewed-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
Tested-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
Link: https://patch.msgid.link/E1vzX59-0000000CVs2-3MHc@rmk-PC.armlinux.org.uk
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Russell King (Oracle)
2026-03-09 09:39:23 +00:00
committed by Jakub Kicinski
parent 7a6387dec8
commit c3d08424e0
14 changed files with 31 additions and 31 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/net/ethernet/stmicro/stmmac/dwmac-dwc-qos-eth.c
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@@ -88,7 +88,7 @@ static int dwc_eth_dwmac_config_dt(struct platform_device *pdev,
plat_dat->core_type = DWMAC_CORE_GMAC4;
plat_dat->dma_cfg->aal = 1;
plat_dat->flags |= STMMAC_FLAG_TSO_EN;
plat_dat->pmt = 1;
plat_dat->pmt = true;
return 0;
}

2
drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c
View File

@@ -566,7 +566,7 @@ static void common_default_data(struct plat_stmmacenet_data *plat)
/* clk_csr_i = 20-35MHz & MDC = clk_csr_i/16 */
plat->clk_csr = STMMAC_CSR_20_35M;
plat->core_type = DWMAC_CORE_GMAC;
plat->force_sf_dma_mode = 1;
plat->force_sf_dma_mode = true;
plat->mdio_bus_data->needs_reset = true;
}

2
drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c
View File

@@ -94,7 +94,7 @@ static void loongson_default_data(struct pci_dev *pdev,
/* clk_csr_i = 100-150MHz & MDC = clk_csr_i/62 */
plat->clk_csr = STMMAC_CSR_100_150M;
plat->core_type = DWMAC_CORE_GMAC;
plat->force_sf_dma_mode = 1;
plat->force_sf_dma_mode = true;
/* Increase the default value for multicast hash bins */
plat->multicast_filter_bins = 256;

2
drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c
View File

@@ -564,7 +564,7 @@ static int mediatek_dwmac_common_data(struct platform_device *pdev,
plat->flags &= ~STMMAC_FLAG_USE_PHY_WOL;
else
plat->flags |= STMMAC_FLAG_USE_PHY_WOL;
plat->riwt_off = 1;
plat->riwt_off = true;
plat->maxmtu = ETH_DATA_LEN;
plat->host_dma_width = priv_plat->variant->dma_bit_mask;
plat->bsp_priv = priv_plat;

2
drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
View File

@@ -817,7 +817,7 @@ static int qcom_ethqos_probe(struct platform_device *pdev)
plat_dat->core_type = DWMAC_CORE_GMAC4;
if (ethqos->has_emac_ge_3)
plat_dat->dwmac4_addrs = &data->dwmac4_addrs;
plat_dat->pmt = 1;
plat_dat->pmt = true;
if (of_property_read_bool(np, "snps,tso"))
plat_dat->flags |= STMMAC_FLAG_TSO_EN;
if (of_device_is_compatible(np, "qcom,qcs404-ethqos"))

2
drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c
View File

@@ -163,7 +163,7 @@ static int s32_dwmac_probe(struct platform_device *pdev)
/* S32CC core feature set */
plat->core_type = DWMAC_CORE_GMAC4;
plat->pmt = 1;
plat->pmt = true;
plat->flags |= STMMAC_FLAG_SPH_DISABLE;
plat->rx_fifo_size = 20480;
plat->tx_fifo_size = 20480;

2
drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
View File

@@ -565,7 +565,7 @@ static void socfpga_gen5_setup_plat_dat(struct socfpga_dwmac *dwmac)
plat_dat->core_type = DWMAC_CORE_GMAC;
/* Rx watchdog timer in dwmac is buggy in this hw */
plat_dat->riwt_off = 1;
plat_dat->riwt_off = true;
}
static void socfpga_agilex5_setup_plat_dat(struct socfpga_dwmac *dwmac)

2
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
View File

@@ -1179,7 +1179,7 @@ static int sun8i_dwmac_probe(struct platform_device *pdev)
* hardware features were copied from Allwinner drivers.
*/
plat_dat->rx_coe = STMMAC_RX_COE_TYPE2;
plat_dat->tx_coe = 1;
plat_dat->tx_coe = true;
plat_dat->flags |= STMMAC_FLAG_HAS_SUN8I;
plat_dat->bsp_priv = gmac;
plat_dat->init = sun8i_dwmac_init;

2
drivers/net/ethernet/stmicro/stmmac/dwmac-sunxi.c
View File

@@ -135,7 +135,7 @@ static int sun7i_gmac_probe(struct platform_device *pdev)
/* platform data specifying hardware features and callbacks.
* hardware features were copied from Allwinner drivers. */
plat_dat->tx_coe = 1;
plat_dat->tx_coe = true;
plat_dat->core_type = DWMAC_CORE_GMAC;
plat_dat->bsp_priv = gmac;
plat_dat->init = sun7i_gmac_init;

2
drivers/net/ethernet/stmicro/stmmac/dwmac-tegra.c
View File

@@ -310,7 +310,7 @@ static int tegra_mgbe_probe(struct platform_device *pdev)
plat->core_type = DWMAC_CORE_XGMAC;
plat->flags |= STMMAC_FLAG_TSO_EN;
plat->pmt = 1;
plat->pmt = true;
plat->bsp_priv = mgbe;
if (!plat->mdio_node)

2
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
View File

@@ -7401,7 +7401,7 @@ static int stmmac_hw_init(struct stmmac_priv *priv)
/* TXCOE doesn't work in thresh DMA mode */
if (priv->plat->force_thresh_dma_mode)
priv->plat->tx_coe = 0;
priv->plat->tx_coe = false;
else
priv->plat->tx_coe = priv->dma_cap.tx_coe;

6
drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c
View File

@@ -25,7 +25,7 @@ static void common_default_data(struct plat_stmmacenet_data *plat)
/* clk_csr_i = 20-35MHz & MDC = clk_csr_i/16 */
plat->clk_csr = STMMAC_CSR_20_35M;
plat->core_type = DWMAC_CORE_GMAC;
plat->force_sf_dma_mode = 1;
plat->force_sf_dma_mode = true;
plat->mdio_bus_data->needs_reset = true;
}
@@ -58,9 +58,9 @@ static int snps_gmac5_default_data(struct pci_dev *pdev,
plat->clk_csr = STMMAC_CSR_250_300M;
plat->core_type = DWMAC_CORE_GMAC4;
plat->force_sf_dma_mode = 1;
plat->force_sf_dma_mode = true;
plat->flags |= STMMAC_FLAG_TSO_EN;
plat->pmt = 1;
plat->pmt = true;
/* Set default number of RX and TX queues to use */
plat->tx_queues_to_use = 4;

20
drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
View File

@@ -514,34 +514,34 @@ stmmac_probe_config_dt(struct platform_device *pdev, u8 *mac)
plat->multicast_filter_bins = dwmac1000_validate_mcast_bins(
&pdev->dev, plat->multicast_filter_bins);
plat->core_type = DWMAC_CORE_GMAC;
plat->pmt = 1;
plat->pmt = true;
}
if (of_device_is_compatible(np, "snps,dwmac-3.40a")) {
plat->core_type = DWMAC_CORE_GMAC;
plat->enh_desc = 1;
plat->tx_coe = 1;
plat->bugged_jumbo = 1;
plat->pmt = 1;
plat->enh_desc = true;
plat->tx_coe = true;
plat->bugged_jumbo = true;
plat->pmt = true;
}
if (of_device_compatible_match(np, stmmac_gmac4_compats)) {
plat->core_type = DWMAC_CORE_GMAC4;
plat->pmt = 1;
plat->pmt = true;
if (of_property_read_bool(np, "snps,tso"))
plat->flags |= STMMAC_FLAG_TSO_EN;
}
if (of_device_is_compatible(np, "snps,dwmac-3.610") ||
of_device_is_compatible(np, "snps,dwmac-3.710")) {
plat->enh_desc = 1;
plat->bugged_jumbo = 1;
plat->force_sf_dma_mode = 1;
plat->enh_desc = true;
plat->bugged_jumbo = true;
plat->force_sf_dma_mode = true;
}
if (of_device_is_compatible(np, "snps,dwxgmac")) {
plat->core_type = DWMAC_CORE_XGMAC;
plat->pmt = 1;
plat->pmt = true;
if (of_property_read_bool(np, "snps,tso"))
plat->flags |= STMMAC_FLAG_TSO_EN;
of_property_read_u32(np, "snps,multicast-filter-bins",

14
include/linux/stmmac.h
View File

@@ -229,14 +229,14 @@ struct plat_stmmacenet_data {
struct stmmac_dma_cfg *dma_cfg;
struct stmmac_safety_feature_cfg *safety_feat_cfg;
int clk_csr;
int enh_desc;
int tx_coe;
bool enh_desc;
bool tx_coe;
bool bugged_jumbo;
bool pmt;
bool force_sf_dma_mode;
bool force_thresh_dma_mode;
bool riwt_off;
int rx_coe;
int bugged_jumbo;
int pmt;
int force_sf_dma_mode;
int force_thresh_dma_mode;
int riwt_off;
int max_speed;
int maxmtu;
int multicast_filter_bins;