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media: rockchip: rkcif: add support for rk3568 vicap dvp capture

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The RK3568 Video Capture (VICAP) unit features a Digital Video Port
(DVP). Add support for it.

Tested-by: Gerald Loacker <gerald.loacker@wolfvision.net>
Reviewed-by: Gerald Loacker <gerald.loacker@wolfvision.net>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Mehdi Djait <mehdi.djait@linux.intel.com>
Signed-off-by: Michael Riesch <michael.riesch@collabora.com>
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Hans Verkuil <hverkuil+cisco@kernel.org>
This commit is contained in:
Michael Riesch
2025-11-14 16:20:20 +01:00
committed by Hans Verkuil
parent 75e2859462
commit c348d67169
3 changed files with 278 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

276
drivers/media/platform/rockchip/rkcif/rkcif-capture-dvp.c
View File

@@ -332,6 +332,282 @@ const struct rkcif_dvp_match_data rkcif_px30_vip_dvp_match_data = {
},
};
static const struct rkcif_input_fmt rk3568_dvp_in_fmts[] = {
{
.mbus_code = MEDIA_BUS_FMT_YUYV8_2X8,
.dvp_fmt_val = RKCIF_FORMAT_YUV_INPUT_422 |
RKCIF_FORMAT_YUV_INPUT_ORDER_YUYV,
.fmt_type = RKCIF_FMT_TYPE_YUV,
.field = V4L2_FIELD_NONE,
},
{
.mbus_code = MEDIA_BUS_FMT_YUYV8_2X8,
.dvp_fmt_val = RKCIF_FORMAT_YUV_INPUT_422 |
RKCIF_FORMAT_YUV_INPUT_ORDER_YUYV,
.fmt_type = RKCIF_FMT_TYPE_YUV,
.field = V4L2_FIELD_INTERLACED,
},
{
.mbus_code = MEDIA_BUS_FMT_YVYU8_2X8,
.dvp_fmt_val = RKCIF_FORMAT_YUV_INPUT_422 |
RKCIF_FORMAT_YUV_INPUT_ORDER_YVYU,
.fmt_type = RKCIF_FMT_TYPE_YUV,
.field = V4L2_FIELD_NONE,
},
{
.mbus_code = MEDIA_BUS_FMT_YVYU8_2X8,
.dvp_fmt_val = RKCIF_FORMAT_YUV_INPUT_422 |
RKCIF_FORMAT_YUV_INPUT_ORDER_YVYU,
.fmt_type = RKCIF_FMT_TYPE_YUV,
.field = V4L2_FIELD_INTERLACED,
},
{
.mbus_code = MEDIA_BUS_FMT_UYVY8_2X8,
.dvp_fmt_val = RKCIF_FORMAT_YUV_INPUT_422 |
RKCIF_FORMAT_YUV_INPUT_ORDER_UYVY,
.fmt_type = RKCIF_FMT_TYPE_YUV,
.field = V4L2_FIELD_NONE,
},
{
.mbus_code = MEDIA_BUS_FMT_UYVY8_2X8,
.dvp_fmt_val = RKCIF_FORMAT_YUV_INPUT_422 |
RKCIF_FORMAT_YUV_INPUT_ORDER_UYVY,
.fmt_type = RKCIF_FMT_TYPE_YUV,
.field = V4L2_FIELD_INTERLACED,
},
{
.mbus_code = MEDIA_BUS_FMT_VYUY8_2X8,
.dvp_fmt_val = RKCIF_FORMAT_YUV_INPUT_422 |
RKCIF_FORMAT_YUV_INPUT_ORDER_VYUY,
.fmt_type = RKCIF_FMT_TYPE_YUV,
.field = V4L2_FIELD_NONE,
},
{
.mbus_code = MEDIA_BUS_FMT_VYUY8_2X8,
.dvp_fmt_val = RKCIF_FORMAT_YUV_INPUT_422 |
RKCIF_FORMAT_YUV_INPUT_ORDER_VYUY,
.fmt_type = RKCIF_FMT_TYPE_YUV,
.field = V4L2_FIELD_INTERLACED,
},
{
.mbus_code = MEDIA_BUS_FMT_YUYV8_1X16,
.dvp_fmt_val = RKCIF_FORMAT_YUV_INPUT_422 |
RKCIF_FORMAT_YUV_INPUT_ORDER_YUYV |
RKCIF_FORMAT_INPUT_MODE_BT1120 |
RKCIF_FORMAT_BT1120_TRANSMIT_PROGRESS,
.field = V4L2_FIELD_NONE,
},
{
.mbus_code = MEDIA_BUS_FMT_YUYV8_1X16,
.dvp_fmt_val = RKCIF_FORMAT_YUV_INPUT_422 |
RKCIF_FORMAT_YUV_INPUT_ORDER_YUYV |
RKCIF_FORMAT_INPUT_MODE_BT1120,
.field = V4L2_FIELD_INTERLACED,
},
{
.mbus_code = MEDIA_BUS_FMT_YVYU8_1X16,
.dvp_fmt_val = RKCIF_FORMAT_YUV_INPUT_422 |
RKCIF_FORMAT_YUV_INPUT_ORDER_YVYU |
RKCIF_FORMAT_INPUT_MODE_BT1120 |
RKCIF_FORMAT_BT1120_TRANSMIT_PROGRESS,
.field = V4L2_FIELD_NONE,
},
{
.mbus_code = MEDIA_BUS_FMT_YVYU8_1X16,
.dvp_fmt_val = RKCIF_FORMAT_YUV_INPUT_422 |
RKCIF_FORMAT_YUV_INPUT_ORDER_YVYU |
RKCIF_FORMAT_INPUT_MODE_BT1120,
.field = V4L2_FIELD_INTERLACED,
},
{
.mbus_code = MEDIA_BUS_FMT_UYVY8_1X16,
.dvp_fmt_val = RKCIF_FORMAT_YUV_INPUT_422 |
RKCIF_FORMAT_YUV_INPUT_ORDER_YUYV |
RKCIF_FORMAT_INPUT_MODE_BT1120 |
RKCIF_FORMAT_BT1120_YC_SWAP |
RKCIF_FORMAT_BT1120_TRANSMIT_PROGRESS,
.field = V4L2_FIELD_NONE,
},
{
.mbus_code = MEDIA_BUS_FMT_UYVY8_1X16,
.dvp_fmt_val = RKCIF_FORMAT_YUV_INPUT_422 |
RKCIF_FORMAT_YUV_INPUT_ORDER_YUYV |
RKCIF_FORMAT_BT1120_YC_SWAP |
RKCIF_FORMAT_INPUT_MODE_BT1120,
.field = V4L2_FIELD_INTERLACED,
},
{
.mbus_code = MEDIA_BUS_FMT_VYUY8_1X16,
.dvp_fmt_val = RKCIF_FORMAT_YUV_INPUT_422 |
RKCIF_FORMAT_YUV_INPUT_ORDER_YVYU |
RKCIF_FORMAT_INPUT_MODE_BT1120 |
RKCIF_FORMAT_BT1120_YC_SWAP |
RKCIF_FORMAT_BT1120_TRANSMIT_PROGRESS,
.field = V4L2_FIELD_NONE,
},
{
.mbus_code = MEDIA_BUS_FMT_VYUY8_1X16,
.dvp_fmt_val = RKCIF_FORMAT_YUV_INPUT_422 |
RKCIF_FORMAT_YUV_INPUT_ORDER_YVYU |
RKCIF_FORMAT_BT1120_YC_SWAP |
RKCIF_FORMAT_INPUT_MODE_BT1120,
.field = V4L2_FIELD_INTERLACED,
},
{
.mbus_code = MEDIA_BUS_FMT_SBGGR8_1X8,
.dvp_fmt_val = RKCIF_FORMAT_INPUT_MODE_RAW |
RKCIF_FORMAT_RAW_DATA_WIDTH_8,
.fmt_type = RKCIF_FMT_TYPE_RAW,
.field = V4L2_FIELD_NONE,
},
{
.mbus_code = MEDIA_BUS_FMT_SGBRG8_1X8,
.dvp_fmt_val = RKCIF_FORMAT_INPUT_MODE_RAW |
RKCIF_FORMAT_RAW_DATA_WIDTH_8,
.fmt_type = RKCIF_FMT_TYPE_RAW,
.field = V4L2_FIELD_NONE,
},
{
.mbus_code = MEDIA_BUS_FMT_SGRBG8_1X8,
.dvp_fmt_val = RKCIF_FORMAT_INPUT_MODE_RAW |
RKCIF_FORMAT_RAW_DATA_WIDTH_8,
.fmt_type = RKCIF_FMT_TYPE_RAW,
.field = V4L2_FIELD_NONE,
},
{
.mbus_code = MEDIA_BUS_FMT_SRGGB8_1X8,
.dvp_fmt_val = RKCIF_FORMAT_INPUT_MODE_RAW |
RKCIF_FORMAT_RAW_DATA_WIDTH_8,
.fmt_type = RKCIF_FMT_TYPE_RAW,
.field = V4L2_FIELD_NONE,
},
{
.mbus_code = MEDIA_BUS_FMT_SBGGR10_1X10,
.dvp_fmt_val = RKCIF_FORMAT_INPUT_MODE_RAW |
RKCIF_FORMAT_RAW_DATA_WIDTH_10,
.fmt_type = RKCIF_FMT_TYPE_RAW,
.field = V4L2_FIELD_NONE,
},
{
.mbus_code = MEDIA_BUS_FMT_SGBRG10_1X10,
.dvp_fmt_val = RKCIF_FORMAT_INPUT_MODE_RAW |
RKCIF_FORMAT_RAW_DATA_WIDTH_10,
.fmt_type = RKCIF_FMT_TYPE_RAW,
.field = V4L2_FIELD_NONE,
},
{
.mbus_code = MEDIA_BUS_FMT_SGRBG10_1X10,
.dvp_fmt_val = RKCIF_FORMAT_INPUT_MODE_RAW |
RKCIF_FORMAT_RAW_DATA_WIDTH_10,
.fmt_type = RKCIF_FMT_TYPE_RAW,
.field = V4L2_FIELD_NONE,
},
{
.mbus_code = MEDIA_BUS_FMT_SRGGB10_1X10,
.dvp_fmt_val = RKCIF_FORMAT_INPUT_MODE_RAW |
RKCIF_FORMAT_RAW_DATA_WIDTH_10,
.fmt_type = RKCIF_FMT_TYPE_RAW,
.field = V4L2_FIELD_NONE,
},
{
.mbus_code = MEDIA_BUS_FMT_SBGGR12_1X12,
.dvp_fmt_val = RKCIF_FORMAT_INPUT_MODE_RAW |
RKCIF_FORMAT_RAW_DATA_WIDTH_12,
.fmt_type = RKCIF_FMT_TYPE_RAW,
.field = V4L2_FIELD_NONE,
},
{
.mbus_code = MEDIA_BUS_FMT_SGBRG12_1X12,
.dvp_fmt_val = RKCIF_FORMAT_INPUT_MODE_RAW |
RKCIF_FORMAT_RAW_DATA_WIDTH_12,
.fmt_type = RKCIF_FMT_TYPE_RAW,
.field = V4L2_FIELD_NONE,
},
{
.mbus_code = MEDIA_BUS_FMT_SGRBG12_1X12,
.dvp_fmt_val = RKCIF_FORMAT_INPUT_MODE_RAW |
RKCIF_FORMAT_RAW_DATA_WIDTH_12,
.fmt_type = RKCIF_FMT_TYPE_RAW,
.field = V4L2_FIELD_NONE,
},
{
.mbus_code = MEDIA_BUS_FMT_SRGGB12_1X12,
.dvp_fmt_val = RKCIF_FORMAT_INPUT_MODE_RAW |
RKCIF_FORMAT_RAW_DATA_WIDTH_12,
.fmt_type = RKCIF_FMT_TYPE_RAW,
.field = V4L2_FIELD_NONE,
},
{
.mbus_code = MEDIA_BUS_FMT_RGB888_1X24,
.field = V4L2_FIELD_NONE,
},
{
.mbus_code = MEDIA_BUS_FMT_Y8_1X8,
.dvp_fmt_val = RKCIF_FORMAT_INPUT_MODE_RAW |
RKCIF_FORMAT_RAW_DATA_WIDTH_8,
.fmt_type = RKCIF_FMT_TYPE_RAW,
.field = V4L2_FIELD_NONE,
},
{
.mbus_code = MEDIA_BUS_FMT_Y10_1X10,
.dvp_fmt_val = RKCIF_FORMAT_INPUT_MODE_RAW |
RKCIF_FORMAT_RAW_DATA_WIDTH_10,
.fmt_type = RKCIF_FMT_TYPE_RAW,
.field = V4L2_FIELD_NONE,
},
{
.mbus_code = MEDIA_BUS_FMT_Y12_1X12,
.dvp_fmt_val = RKCIF_FORMAT_INPUT_MODE_RAW |
RKCIF_FORMAT_RAW_DATA_WIDTH_12,
.fmt_type = RKCIF_FMT_TYPE_RAW,
.field = V4L2_FIELD_NONE,
},
};
static void rk3568_dvp_grf_setup(struct rkcif_device *rkcif)
{
u32 con1 = RK3568_GRF_WRITE_ENABLE(RK3568_GRF_VI_CON1_CIF_DATAPATH |
RK3568_GRF_VI_CON1_CIF_CLK_DELAYNUM);
if (!rkcif->grf)
return;
con1 |= rkcif->interfaces[RKCIF_DVP].dvp.dvp_clk_delay &
RK3568_GRF_VI_CON1_CIF_CLK_DELAYNUM;
if (rkcif->interfaces[RKCIF_DVP].vep.bus.parallel.flags &
V4L2_MBUS_PCLK_SAMPLE_DUALEDGE)
con1 |= RK3568_GRF_VI_CON1_CIF_DATAPATH;
regmap_write(rkcif->grf, RK3568_GRF_VI_CON1, con1);
}
const struct rkcif_dvp_match_data rkcif_rk3568_vicap_dvp_match_data = {
.in_fmts = rk3568_dvp_in_fmts,
.in_fmts_num = ARRAY_SIZE(rk3568_dvp_in_fmts),
.out_fmts = dvp_out_fmts,
.out_fmts_num = ARRAY_SIZE(dvp_out_fmts),
.setup = rk3568_dvp_grf_setup,
.has_scaler = false,
.regs = {
[RKCIF_DVP_CTRL] = 0x00,
[RKCIF_DVP_INTEN] = 0x04,
[RKCIF_DVP_INTSTAT] = 0x08,
[RKCIF_DVP_FOR] = 0x0c,
[RKCIF_DVP_LINE_NUM_ADDR] = 0x2c,
[RKCIF_DVP_FRM0_ADDR_Y] = 0x14,
[RKCIF_DVP_FRM0_ADDR_UV] = 0x18,
[RKCIF_DVP_FRM1_ADDR_Y] = 0x1c,
[RKCIF_DVP_FRM1_ADDR_UV] = 0x20,
[RKCIF_DVP_VIR_LINE_WIDTH] = 0x24,
[RKCIF_DVP_SET_SIZE] = 0x28,
[RKCIF_DVP_CROP] = 0x34,
[RKCIF_DVP_FRAME_STATUS] = 0x3c,
[RKCIF_DVP_LAST_LINE] = 0x44,
[RKCIF_DVP_LAST_PIX] = 0x48,
},
};
static inline unsigned int rkcif_dvp_get_addr(struct rkcif_device *rkcif,
unsigned int index)
{

1
drivers/media/platform/rockchip/rkcif/rkcif-capture-dvp.h
View File

@@ -14,6 +14,7 @@
#include "rkcif-common.h"
extern const struct rkcif_dvp_match_data rkcif_px30_vip_dvp_match_data;
extern const struct rkcif_dvp_match_data rkcif_rk3568_vicap_dvp_match_data;
int rkcif_dvp_register(struct rkcif_device *rkcif);

1
drivers/media/platform/rockchip/rkcif/rkcif-dev.c
View File

@@ -48,6 +48,7 @@ static const char *const rk3568_vicap_clks[] = {
static const struct rkcif_match_data rk3568_vicap_match_data = {
.clks = rk3568_vicap_clks,
.clks_num = ARRAY_SIZE(rk3568_vicap_clks),
.dvp = &rkcif_rk3568_vicap_dvp_match_data,
};
static const struct of_device_id rkcif_plat_of_match[] = {