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thermal: renesas: rzg3e: make calibration value retrieval per-chip
The Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs expose the temperature calibration data via SMC SIP calls. To prepare for supporting these SoCs, do the following changes. Rename rzg3e_thermal_parse_dt() to rzg3e_thermal_get_syscon_trim(). Move the syscon usage out of rzg3e_thermal_get_calibration() and into rzg3e_thermal_get_syscon_trim() and remove single-use variables from the private state. Place a pointer to rzg3e_thermal_get_syscon_trim() into the chip-specific struct, and use it in the probe function to retrieve the calibration values. Now that syscon usage has been moved out of rzg3e_thermal_get_calibration(), remove it and inline the calibration validation into the probe function. Also, reuse the TSU_CODE_MAX macro to mask the calibration values, as GEMASK(11, 0) and 0xFFF are equivalent, and replace the hardcoded 0xFFF with TSU_CODE_MAX in the calibration validation. Reviewed-by: John Madieu <john.madieu.xa@bp.renesas.com> Tested-by: John Madieu <john.madieu.xa@bp.renesas.com> Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260108195223.193531-4-cosmin-gabriel.tanislav.xa@renesas.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
This commit is contained in:
committed by
Daniel Lezcano
parent
6c7f87f517
commit
c33edd8f93
@@ -70,7 +70,10 @@
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#define TSU_POLL_DELAY_US 10 /* Polling interval */
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#define TSU_MIN_CLOCK_RATE 24000000 /* TSU_PCLK minimum 24MHz */
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struct rzg3e_thermal_priv;
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struct rzg3e_thermal_info {
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int (*get_trim)(struct rzg3e_thermal_priv *priv);
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int temp_d_mc;
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int temp_e_mc;
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};
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@@ -91,13 +94,11 @@ struct rzg3e_thermal_info {
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struct rzg3e_thermal_priv {
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void __iomem *base;
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struct device *dev;
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struct regmap *syscon;
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struct thermal_zone_device *zone;
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struct reset_control *rstc;
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const struct rzg3e_thermal_info *info;
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u16 trmval0;
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u16 trmval1;
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u32 trim_offset;
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struct mutex lock;
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};
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@@ -334,48 +335,30 @@ static const struct thermal_zone_device_ops rzg3e_tz_ops = {
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.set_trips = rzg3e_thermal_set_trips,
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};
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static int rzg3e_thermal_get_calibration(struct rzg3e_thermal_priv *priv)
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{
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u32 val;
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int ret;
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/* Read calibration values from syscon */
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ret = regmap_read(priv->syscon, priv->trim_offset, &val);
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if (ret)
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return ret;
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priv->trmval0 = val & GENMASK(11, 0);
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ret = regmap_read(priv->syscon, priv->trim_offset + 4, &val);
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if (ret)
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return ret;
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priv->trmval1 = val & GENMASK(11, 0);
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/* Validate calibration data */
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if (!priv->trmval0 || !priv->trmval1 ||
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priv->trmval0 == priv->trmval1 ||
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priv->trmval0 == 0xFFF || priv->trmval1 == 0xFFF) {
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dev_err(priv->dev, "Invalid calibration: b=0x%03x, c=0x%03x\n",
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priv->trmval0, priv->trmval1);
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return -EINVAL;
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}
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dev_dbg(priv->dev, "Calibration: b=0x%03x (%u), c=0x%03x (%u)\n",
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priv->trmval0, priv->trmval0, priv->trmval1, priv->trmval1);
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return 0;
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}
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static int rzg3e_thermal_parse_dt(struct rzg3e_thermal_priv *priv)
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static int rzg3e_thermal_get_syscon_trim(struct rzg3e_thermal_priv *priv)
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{
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struct device_node *np = priv->dev->of_node;
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struct regmap *syscon;
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u32 offset;
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int ret;
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u32 val;
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priv->syscon = syscon_regmap_lookup_by_phandle_args(np, "renesas,tsu-trim", 1, &offset);
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if (IS_ERR(priv->syscon))
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return dev_err_probe(priv->dev, PTR_ERR(priv->syscon),
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syscon = syscon_regmap_lookup_by_phandle_args(np, "renesas,tsu-trim", 1, &offset);
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if (IS_ERR(syscon))
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return dev_err_probe(priv->dev, PTR_ERR(syscon),
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"Failed to parse renesas,tsu-trim\n");
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priv->trim_offset = offset;
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/* Read calibration values from syscon */
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ret = regmap_read(syscon, offset, &val);
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if (ret)
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return ret;
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priv->trmval0 = val & TSU_CODE_MAX;
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ret = regmap_read(syscon, offset + 4, &val);
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if (ret)
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return ret;
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priv->trmval1 = val & TSU_CODE_MAX;
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return 0;
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}
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@@ -402,11 +385,20 @@ static int rzg3e_thermal_probe(struct platform_device *pdev)
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if (IS_ERR(priv->base))
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return PTR_ERR(priv->base);
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/* Parse device tree for trim register info */
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ret = rzg3e_thermal_parse_dt(priv);
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ret = priv->info->get_trim(priv);
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if (ret)
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return ret;
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if (!priv->trmval0 || !priv->trmval1 ||
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priv->trmval0 == priv->trmval1 ||
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priv->trmval0 == TSU_CODE_MAX || priv->trmval1 == TSU_CODE_MAX)
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return dev_err_probe(priv->dev, -EINVAL,
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"Invalid calibration: b=0x%03x, c=0x%03x\n",
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priv->trmval0, priv->trmval1);
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dev_dbg(priv->dev, "Calibration: b=0x%03x (%u), c=0x%03x (%u)\n",
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priv->trmval0, priv->trmval0, priv->trmval1, priv->trmval1);
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/* Get clock to verify frequency - clock is managed by power domain */
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clk = devm_clk_get(dev, NULL);
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if (IS_ERR(clk))
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@@ -423,12 +415,6 @@ static int rzg3e_thermal_probe(struct platform_device *pdev)
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return dev_err_probe(dev, PTR_ERR(priv->rstc),
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"Failed to get/deassert reset control\n");
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/* Get calibration data */
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ret = rzg3e_thermal_get_calibration(priv);
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if (ret)
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return dev_err_probe(dev, ret,
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"Failed to get valid calibration data\n");
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/* Get comparison interrupt */
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irq = platform_get_irq_byname(pdev, "adcmpi");
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if (irq < 0)
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@@ -533,6 +519,7 @@ static const struct dev_pm_ops rzg3e_thermal_pm_ops = {
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};
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static const struct rzg3e_thermal_info rzg3e_thermal_info = {
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.get_trim = rzg3e_thermal_get_syscon_trim,
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.temp_d_mc = -41000,
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.temp_e_mc = 126000,
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};
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