media: dt-bindings: venus: Add qcm2290 dt schema

Add a schema for the venus video encoder/decoder on the qcm2290.

The order of the IOMMU list is strict: the first two entries correspond
to non-secure IOMMUs, and the remaining three to secure IOMMUs.

Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Bryan O'Donoghue <bod@kernel.org>
Signed-off-by: Hans Verkuil <hverkuil+cisco@kernel.org>
This commit is contained in:
Jorge Ramirez-Ortiz
2025-08-14 10:52:41 +02:00
committed by Mauro Carvalho Chehab
parent 935f703d7e
commit c329055587

View File

@@ -0,0 +1,130 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/qcom,qcm2290-venus.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm QCM2290 Venus video encode and decode accelerators
maintainers:
- Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>
description:
The Venus AR50_LITE IP is a video encode and decode accelerator present
on Qualcomm platforms.
allOf:
- $ref: qcom,venus-common.yaml#
properties:
compatible:
const: qcom,qcm2290-venus
power-domains:
maxItems: 3
power-domain-names:
items:
- const: venus
- const: vcodec0
- const: cx
clocks:
maxItems: 6
clock-names:
items:
- const: core
- const: iface
- const: bus
- const: throttle
- const: vcodec0_core
- const: vcodec0_bus
iommus:
maxItems: 5
interconnects:
maxItems: 2
interconnect-names:
items:
- const: video-mem
- const: cpu-cfg
operating-points-v2: true
opp-table:
type: object
required:
- compatible
- power-domain-names
- iommus
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,gcc-qcm2290.h>
#include <dt-bindings/interconnect/qcom,qcm2290.h>
#include <dt-bindings/interconnect/qcom,rpm-icc.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/qcom-rpmpd.h>
venus: video-codec@5a00000 {
compatible = "qcom,qcm2290-venus";
reg = <0x5a00000 0xf0000>;
interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&gcc GCC_VENUS_GDSC>,
<&gcc GCC_VCODEC0_GDSC>,
<&rpmpd QCM2290_VDDCX>;
power-domain-names = "venus",
"vcodec0",
"cx";
operating-points-v2 = <&venus_opp_table>;
clocks = <&gcc GCC_VIDEO_VENUS_CTL_CLK>,
<&gcc GCC_VIDEO_AHB_CLK>,
<&gcc GCC_VENUS_CTL_AXI_CLK>,
<&gcc GCC_VIDEO_THROTTLE_CORE_CLK>,
<&gcc GCC_VIDEO_VCODEC0_SYS_CLK>,
<&gcc GCC_VCODEC0_AXI_CLK>;
clock-names = "core",
"iface",
"bus",
"throttle",
"vcodec0_core",
"vcodec0_bus";
memory-region = <&pil_video_mem>;
iommus = <&apps_smmu 0x860 0x0>,
<&apps_smmu 0x880 0x0>,
<&apps_smmu 0x861 0x04>,
<&apps_smmu 0x863 0x0>,
<&apps_smmu 0x804 0xe0>;
interconnects = <&mmnrt_virt MASTER_VIDEO_P0 RPM_ALWAYS_TAG
&bimc SLAVE_EBI1 RPM_ALWAYS_TAG>,
<&bimc MASTER_APPSS_PROC RPM_ACTIVE_TAG
&config_noc SLAVE_VENUS_CFG RPM_ACTIVE_TAG>;
interconnect-names = "video-mem",
"cpu-cfg";
venus_opp_table: opp-table {
compatible = "operating-points-v2";
opp-133333333 {
opp-hz = /bits/ 64 <133333333>;
required-opps = <&rpmpd_opp_low_svs>;
};
opp-240000000 {
opp-hz = /bits/ 64 <240000000>;
required-opps = <&rpmpd_opp_svs>;
};
};
};